[gem5-users] l3 cache

[Moussa, Ayman]

Does the standard system call script (se.py) model an L3 cache or is it only L1 
and L2? When I ran it with the -h option, I saw an option for L3 caches so I 
used that:


build/ARM/gem5.opt configs/example/se.py --caches --l2cache --num-dirs=1 
--num-l2caches=1 --num-l2caches=1 --l1d_size=16kB --l1i_size=16kB 
--l2_size=64kB --l3_size=128kB --l1d_assoc=4 --l1i_assoc=4 --l2_assoc=8 
--l3_assoc=16 --cpu-type=DerivO3CPU --mem-type=DDR3_2133_x64 -c 
tests/test-progs/hello/bin/arm/linux/hello


but when I check the output of stats.txt and config.ini, there is no data about 
L3 caches which was driving me crazy as it was in the options. I checked the 
se.py too and didn't see anything specifying L3 caches (maybe I'm looking in 
the wrong place?) If I want to model an L3 cache, do I need to manually add it?


Thanks

Ayman
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Re: [gem5-users] l3 cache

[Serhat Gesoglu]

Hello,
L3 cache is not implemented in gem5 but you can manually implement it (and add 
a command line option such as --l3caches), unless you are using ruby (as far as 
I know due to not having a 3-level coherence protocol).

You may want to check this tutorial for more information about adding caches: 
http://pages.cs.wisc.edu/~david/courses/cs752/Spring2015/gem5-tutorial/part1/cache_config.html

Hope this helps

Cheers
Serhat


From: gem5-users [gem5-users-boun...@gem5.org] on behalf of Moussa, Ayman 
[ayman.mouss...@imperial.ac.uk]
Sent: 27 February 2017 11:43
To: gem5 users mailing list
Subject: [gem5-users] l3 cache

Does the standard system call script (se.py) model an L3 cache or is it only L1 
and L2? When I ran it with the -h option, I saw an option for L3 caches so I 
used that:


build/ARM/gem5.opt configs/example/se.py --caches --l2cache --num-dirs=1 
--num-l2caches=1 --num-l2caches=1 --l1d_size=16kB --l1i_size=16kB 
--l2_size=64kB --l3_size=128kB --l1d_assoc=4 --l1i_assoc=4 --l2_assoc=8 
--l3_assoc=16 --cpu-type=DerivO3CPU --mem-type=DDR3_2133_x64 -c 
tests/test-progs/hello/bin/arm/linux/hello


but when I check the output of stats.txt and config.ini, there is no data about 
L3 caches which was driving me crazy as it was in the options. I checked the 
se.py too and didn't see anything specifying L3 caches (maybe I'm looking in 
the wrong place?) If I want to model an L3 cache, do I need to manually add it?


Thanks

Ayman

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Re: [gem5-users] Ubuntu, booted on gem5, is not syncing the file-system?

[Mukherjee, Somnath]

Jason,
I changed it RAW disk image following http://www.gem5.org/BBench-gem5. After 
that I see some files are reflected on the disk image. However, not all are 
seen on the mounted disk image. Earlier I had the COW disk image and there I 
didn’t see any of the files being written to the disk image!

Is there anything else I am missing?

Regards,
Somnath

From: gem5-users [mailto:gem5-users-boun...@gem5.org] On Behalf Of Jason 
Lowe-Power
Sent: Monday, February 27, 2017 8:48 PM
To: gem5 users mailing list
Subject: Re: [gem5-users] Ubuntu, booted on gem5, is not syncing the 
file-system?

Hi Somnath,

By default the disk image is created as a "COW" or copy-on-write image. Thus, 
all changes made to the disk are made to an new copy that is deleted when gem5 
exits. If you want your changes to be permanent you need to modify the way the 
disk image is created and use a raw disk image, not a COW image. It should be 
clear from the code what to change.

Jason

On Mon, Feb 27, 2017 at 1:15 AM Mukherjee, Somnath 
> wrote:
Dear Friends,
I got this working, partially; I see some files are being written to the disk 
image and some are not!
I have tried doing sync / halt etc.

Can anyone please help?

Regards,
Somnath

From: gem5-users 
[mailto:gem5-users-boun...@gem5.org] On 
Behalf Of Mukherjee, Somnath
Sent: Wednesday, February 22, 2017 2:27 PM
To: gem5 users mailing list
Subject: Re: [gem5-users] Ubuntu, booted on gem5, is not syncing the 
file-system?

Ok, I found the answer here at http://www.gem5.org/BBench-gem5
I will follow what’s suggested and get back if there’s any issues!

Regards,
Somnath

From: gem5-users [mailto:gem5-users-boun...@gem5.org] On Behalf Of Mukherjee, 
Somnath
Sent: Wednesday, February 22, 2017 11:44 AM
To: gem5-users@gem5.org
Subject: [gem5-users] Ubuntu, booted on gem5, is not syncing the file-system?

Friends,
I have gem5 simulator running on a Ubuntu host.

The gem5 itself is booting Ubuntu and then I am trying to run some benchmarking 
program.
There’s a filesystem .img file that’s mounted by gem5 while booting Ubuntu.
The problem is I don’t see the benchmark output files being written into the 
filesystem .img file after the benchmark program has  finished running.
However, on the Ubuntu command prompt on gem5 simulator, I can see those files.

Can someone tell me, how do I make gem5 flush all the content to the filesystem 
.img?
After it has written the content, I would like to mount the filesystem on 
Ubuntu host to view the output of the benchmark.

I ran simple touch command to create a file on Ubuntu booted by gem5. That file 
too is not visible when I locally mount the .img file.
Can someone please help? I am sure I’m missing something here.

Regards,
Somnath Mukherjee
Automotive Infotainment Systems
Bangalore

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Re: [gem5-users] flit size and int_link width in garnet2

[Krishna, Tushar]

On Feb 27, 2017, at 3:32 PM, raziye deylamsalehi 
> wrote:


Hi Tushar

as I see in mailing list and documentation the num_dir is equal with number of 
memory controllers. That is correct?


As far as I know, in most coherence protocols (e.g., MOESI_CMP_directory), the 
“directory” and the memory controller are the same.
In other words, the directory also simulates the behavior of the memory 
controller.
Some of the folks working on the coherence protocols may have a better idea.


So what is the meaning of num_dir in moesi_cmp_directory protocol? For example, 
if we want to simulate an n*n NoC (that has less than n*n memory controller), 
what is the meaning of equality between num_dir and number of memory 
controllers?

In this file: configs/topologies/MeshDirCorners_XY.py,  the network based on 
this topology has 4 dir. Then what does happen in its cache coherency protocol?


This just means that there are 4 memory controllers, one at each corner.
Each core in MOESI_CMP_directory is connected to a private L1 + shared L2 
slice. So each router is connected to a L1 and a L2.
The corner routers are also connected to the directories (memory controllers).


L1 is private in protocol. is there any directory for L1 ?


The directories are at the 4 corners in MeshDirCorners ...


On Fri, Feb 24, 2017 at 1:38 AM, Krishna, Tushar 
> wrote:
No. You can run any protocol with any network topology.


On Feb 23, 2017, at 5:06 PM, raziye deylamsalehi 
> wrote:

Thank you very much Tushar, I read most of them but you defined those very 
clear.
I have some more question: could this redundant link make us to change protocol 
file or another files?

On Thu, Feb 23, 2017 at 8:40 AM, Krishna, Tushar 
> wrote:


On Feb 22, 2017, at 7:03 AM, raziye deylamsalehi 
> wrote:

I read the following paragraph from “on-chip networks” book:
“Inoff-chip networks, channel widths are limited by pin bandwith; this 
limitation causes flits to be broken down into smaller chunks called phits. To 
date, in on-chip networks, flits are composed of a single phit and are the 
smallest subdivision of a message due to wide on-chip channels.”
“In some networks the flit size equals the phit size and thus, there is no need 
to split into smaller phits.” How I can know it for alpha processor?
You are getting confused between packets, flits and phits.

For a processor with cache coherence traffic, in gem5 the size of control 
packets (e.g., coherence requests) is 8B (64b) and data packets (e.g., 
coherence response) is 64B + 8B = 72B (576b).
Default flit (i.e., link) size is 16B (128b).
This means control packets fit in 1-flit, data packets fit in 5-flits.
Data packets are automatically split into 5-flits at the NI.

[Note: In off-chip networks, due to thinner links off-chip, a 64b flit might 
have to be sent over multiple cycles through the pins. Thats where phits come 
in, but you don’t need to worry about those].



Yes, I want to have some links to be wider. Do I need break flits into phits 
For adding multiple links in topology file?
If you want to make some links in the NoC wider, then those routers need to 
dynamically merge multiple flits into a packet, or vice versa, which you can 
imagine is hard.
If you want wider links just to give some parts of the NoC more bandwidth, you 
can add multiple links between the same routers (for e.g, adding 2 links will 
make the overall width 256b, allowing 2 flits to traverse in parallel).




On Wed, Feb 22, 2017 at 3:08 AM, Krishna, Tushar 
> wrote:
All links are equal sized in garnet.
If you have unequal widths, then you need a way to break flits into phits 
mid-way in routers.
If you want to have some links to be wider, I would recommend adding multiple 
links in the topology file.


On Feb 21, 2017, at 6:33 PM, raziye deylamsalehi 
> wrote:


I want to assign variation on some of links (with link id) not all of links. do 
I can change it in my topology with ni_flit_size?

On Feb 22, 2017 2:53 AM, "Krishna, Tushar" 
> wrote:
For that you will use --link-width-bits
ni_flit_size is set to link_width_bits / 8 inside configs/network/Network.py
You can see this file for other options as well.


On Feb 21, 2017, at 4:48 PM, raziye deylamsalehi 
> wrote:

Thank you for answering.
I saw this page. ni_flit_size is "network interface flit size in bytes", I want 
to change width of internal links (links between router) so I must use 
ni_flit_size?

On Mon, Feb 6, 2017 at 11:50 

Re: [gem5-users] Ubuntu, booted on gem5, is not syncing the file-system?

[Jason Lowe-Power]

Hi Somnath,

By default the disk image is created as a "COW" or copy-on-write image.
Thus, all changes made to the disk are made to an new copy that is deleted
when gem5 exits. If you want your changes to be permanent you need to
modify the way the disk image is created and use a raw disk image, not a
COW image. It should be clear from the code what to change.

Jason

On Mon, Feb 27, 2017 at 1:15 AM Mukherjee, Somnath  wrote:

> Dear Friends,
>
> I got this working, partially; I see some files are being written to the
> disk image and some are not!
>
> I have tried doing *sync* / *halt* etc.
>
>
>
> Can anyone please help?
>
>
>
> Regards,
>
> Somnath
>
>
>
> *From:* gem5-users [mailto:gem5-users-boun...@gem5.org] *On Behalf Of 
> *Mukherjee,
> Somnath
> *Sent:* Wednesday, February 22, 2017 2:27 PM
> *To:* gem5 users mailing list
> *Subject:* Re: [gem5-users] Ubuntu, booted on gem5, is not syncing the
> file-system?
>
>
>
> Ok, I found the answer here at http://www.gem5.org/BBench-gem5
>
> I will follow what’s suggested and get back if there’s any issues!
>
>
>
> Regards,
>
> Somnath
>
>
>
> *From:* gem5-users [mailto:gem5-users-boun...@gem5.org
> ] *On Behalf Of *Mukherjee, Somnath
> *Sent:* Wednesday, February 22, 2017 11:44 AM
> *To:* gem5-users@gem5.org
> *Subject:* [gem5-users] Ubuntu, booted on gem5, is not syncing the
> file-system?
>
>
>
> Friends,
>
> I have gem5 simulator running on a Ubuntu host.
>
>
>
> The gem5 itself is booting Ubuntu and then I am trying to run some
> benchmarking program.
>
> There’s a filesystem .img file that’s mounted by gem5 while booting Ubuntu.
>
> The problem is I don’t see the benchmark output files being written into
> the filesystem .img file after the benchmark program has  finished running.
>
> However, on the Ubuntu command prompt on gem5 simulator, I can see those
> files.
>
>
>
> Can someone tell me, how do I make gem5 flush all the content to the
> filesystem .img?
>
> After it has written the content, I would like to mount the filesystem on
> Ubuntu host to view the output of the benchmark.
>
>
>
> I ran simple touch command to create a file on Ubuntu booted by gem5. That
> file too is not visible when I locally mount the .img file.
>
> Can someone please help? I am sure I’m missing something here.
>
>
>
> Regards,
>
> Somnath Mukherjee
>
> Automotive Infotainment Systems
>
> Bangalore
>
>
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Re: [gem5-users] l3 cache

[Jason Lowe-Power]

A more up-to-date version of the tutorial can be found at
http://learning.gem5.org. This is where it will live for the foreseeable
future.

Jason

On Mon, Feb 27, 2017 at 5:58 AM Serhat Gesoglu <
serhat.geso...@manchester.ac.uk> wrote:

> Hello,
> L3 cache is not implemented in gem5 but you can manually implement it (and
> add a command line option such as --l3caches), unless you are using ruby
> (as far as I know due to not having a 3-level coherence protocol).
>
> You may want to check this tutorial for more information about adding
> caches:
> http://pages.cs.wisc.edu/~david/courses/cs752/Spring2015/gem5-tutorial/part1/cache_config.html
>
> Hope this helps
>
> Cheers
> Serhat
>
> 
> From: gem5-users [gem5-users-boun...@gem5.org] on behalf of Moussa, Ayman
> [ayman.mouss...@imperial.ac.uk]
> Sent: 27 February 2017 11:43
> To: gem5 users mailing list
> Subject: [gem5-users] l3 cache
>
> Does the standard system call script (se.py) model an L3 cache or is it
> only L1 and L2? When I ran it with the -h option, I saw an option for L3
> caches so I used that:
>
>
> build/ARM/gem5.opt configs/example/se.py --caches --l2cache --num-dirs=1
> --num-l2caches=1 --num-l2caches=1 --l1d_size=16kB --l1i_size=16kB
> --l2_size=64kB --l3_size=128kB --l1d_assoc=4 --l1i_assoc=4 --l2_assoc=8
> --l3_assoc=16 --cpu-type=DerivO3CPU --mem-type=DDR3_2133_x64 -c
> tests/test-progs/hello/bin/arm/linux/hello
>
>
> but when I check the output of stats.txt and config.ini, there is no data
> about L3 caches which was driving me crazy as it was in the options. I
> checked the se.py too and didn't see anything specifying L3 caches (maybe
> I'm looking in the wrong place?) If I want to model an L3 cache, do I need
> to manually add it?
>
>
> Thanks
>
> Ayman
>
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Re: [gem5-users] gem5 segmentation fault with SPEC CPU2006 benchmarks

[Jason Lowe-Power]

Hi Muzamil,

Have you tried running gdb to find where the segfault is occurring. That's
where I would start. Using some debug flags would be helpful too after you
narrow down the problem.

Cheers,
Jason

On Wed, Feb 22, 2017 at 6:31 PM Muzamil Rafique 
wrote:

> Hi all,
>
> I was trying to run SPEC CPU2006 benchmarks with a simple configuration
> following the instructions given at:
>
> http://www.gem5.org/SPEC_CPU2006_benchmarks
>
> and modifying the given two codes accordingly. When I ran simulation with
> any benchmark:
>
> build/X86/gem5.opt configs/tutorial/cmp.py -b=bzip2
>
> I got the following error:
>
> Global frequency set at 1 ticks per second
> warn: DRAM device capacity (8192 Mbytes) does not match the address range
> assigned
> (512 Mbytes)
>
> ***gem5 has encountered a segmentation fault!***
>
>
> Any idea why this is happening or how to fix it?
>
> Thanks
> Muzamil
>
>
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Re: [gem5-users] Linux booting problem in ARM NOC

[Jason Lowe-Power]

Hi Sharjeel,

It's clear that Ruby+ARM currently doesn't work. It's going to take some
effort and some code changes in Ruby to get it to work correctly. It's good
that a single core boots. You should try something *very simple* with 2
cores. For instance, use MI_example and the Pt2Pt topology with the simple
network model. From here you'll be able to track down the problems easier.
Once you have that working, you can slowly introduce other code and solve
the problems that come with that.

Jason

On Mon, Feb 27, 2017 at 1:42 AM SHARJEEL KHILJI <
sharjeelsaeedkhi...@gmail.com> wrote:

> Hi,
>
> I can boot linux on following to a point indicated. I can boot the same
> kernel on single core CrossbarGarnet.
> There is some issue with multi core in ARM NOC in full system. Any
> suggestions please,
>
> ./build/ARM/gem5.fast  configs/example/fs.py
> --machine-type=VExpress_GEM5_V1 --kernel
> /home/khilji/gem5/m5/system/binaries/vmlinux-aarch32 --disk-image
> /home/khilji/gem5/m5/system/disks/arm-ubuntu-natty-headless.img
> --dtb-filename /home/khilji/gem5/m5/system/dtb/armv7_gem5_v1_2cpu.dtb
> --num-cpus=2 --cpu-type=timing --ruby --num-dirs=1 --garnet-network
> flexible --topology Torus --mesh-rows 2
>
> Booting Linux on physical CPU 0x0
> Initializing cgroup subsys cpuset
> Linux version 4.3.3 (bes...@jaguar.lirmm.fr) (gcc version 4.9.3
> (crosstool-NG crosstool-ng-1.22.0) ) #1 SMP PREEMPT Sat Jan 30 23:15:48 CET
> 2016
> CPU: ARMv7 Processor [410fc0f0] revision 0 (ARMv7), cr=10c5387d
> CPU: PIPT / VIPT nonaliasing data cache, PIPT instruction cache
> Machine model: V2P-CA15
> Ignoring memory range 0x1 - 0x48000
> cma: Reserved 16 MiB at 0x9f00
> Memory policy: Data cache writealloc
> On node 0 totalpages: 131072
> free_area_init_node: node 0, pgdat 806e4300, node_mem_map 9ebf2000
>   Normal zone: 1024 pages used for memmap
>   Normal zone: 0 pages reserved
>   Normal zone: 131072 pages, LIFO batch:31
> PERCPU: Embedded 12 pages/cpu @9ebd3000 s19392 r8192 d21568 u49152
> pcpu-alloc: s19392 r8192 d21568 u49152 alloc=12*4096
> pcpu-alloc: [0] 0 [0] 1
> Built 1 zonelists in Zone order, mobility grouping on.  Total pages: 130048
> Kernel command line: earlyprintk=pl011,0x1c09 console=ttyAMA0
> lpj=19988480 norandmaps rw loglevel=8 mem=512MB root=/dev/sda1
> PID hash table entries: 2048 (order: 1, 8192 bytes)
> Dentry cache hash table entries: 65536 (order: 6, 262144 bytes)
> Inode-cache hash table entries: 32768 (order: 5, 131072 bytes)
> Memory: 496044K/524288K available (5125K kernel code, 155K rwdata, 1476K
> rodata, 268K init, 136K bss, 11860K reserved, 16384K cma-reserved)
> Virtual kernel memory layout:
> vector  : 0x - 0x1000   (   4 kB)
> fixmap  : 0xffc0 - 0xfff0   (3072 kB)
> vmalloc : 0xa080 - 0xff00   (1512 MB)
> lowmem  : 0x8000 - 0xa000   ( 512 MB)
> modules : 0x7f00 - 0x8000   (  16 MB)
>   .text : 0x80008000 - 0x8067a8c8   (6603 kB)
>   .init : 0x8067b000 - 0x806be000   ( 268 kB)
>   .data : 0x806be000 - 0x806e4e40   ( 156 kB)
>.bss : 0x806e7000 - 0x807091fc   ( 137 kB)
> SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=2, Nodes=1
> Preemptible hierarchical RCU implementation.
> Build-time adjustment of leaf fanout to 32.
> RCU restricting CPUs from NR_CPUS=32 to nr_cpu_ids=2.
> RCU: Adjusting geometry for rcu_fanout_leaf=32, nr_cpu_ids=2
> NR_IRQS:16 nr_irqs:16 16
> L2C: failed to init: -19
> Architected cp15 timer(s) running at 25.16MHz (virt).
> clocksource: arch_sys_counter: mask: 0xff max_cycles:
> 0x5cdd39714, max_idle_ns: 440795202620 ns
> sched_clock: 56 bits at 25MHz, resolution 39ns, wraps every 4398046511084ns
> Switching to timer-based delay loop, resolution 39ns
> Console: colour dummy device 80x30
> Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS
> (lpj=19988480)
> pid_max: default: 32768 minimum: 301
> Mount-cache hash table entries: 1024 (order: 0, 4096 bytes)
> Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes)
> CPU: Testing write buffer coherency: ok
> /cpus/cpu@0 missing clock-frequency property
> /cpus/cpu@1 missing clock-frequency property
> CPU0: thread -1, cpu 0, socket 0, mpidr 8000
> Setting up static identity map for 0x80008280 - 0x800082d8
> CPU1: thread -1, cpu 1, socket 0, mpidr 8001
> Brought up 2 CPUs
> SMP: Total of 2 processors activated (7995.39 BogoMIPS).
> CPU: All CPU(s) started in SVC mode.
> devtmpfs: initialized
> VFP support v0.3: implementor 41 architecture 4 part 30 variant a rev 0
> clocksource: jiffies: mask: 0x max_cycles: 0x,
> max_idle_ns: 1911260446275 ns
> NET: Registered protocol family 16
> DMA: preallocated 256 KiB pool for atomic coherent allocations
> cpuidle: using governor ladder
> cpuidle: using governor menu
> hw-breakpoint: Debug register access (0xee113e93) caused undefined
> instruction on CPU 0
> hw-breakpoint: Debug register access (0xee013e90) caused