Hello,
I am relatively new in gem5 simulator, i have to design a multiprocessor
architecture with two levels of caches composed of:
- At level 1: the usual L1i and L1d caches
- At level 2 (shared by all processors): L2i and L2d caches, L2i
inclusive with L1i, and L2d non-inclusive with
Hello All,
I generate trace file using Commonitor and decoded the trace file by using
decode_packet_trace.py file in util folder. The output looks like this:
5,r,0,4,3328,0
5,r,32,4,3328,500
5,r,36,4,3328,1000
5,r,40,4,3328,1500
6,r,200,4,3146,1500
5,r,44,4,3328,2000
5,r,48,4,3328,2500
Hi, All,
I found that there is a kind of command in packet.hh file called writeClean,
and the comment for this command is writes dirty data below without evicting. I
am wondering what’s the meaning of this command, is that when we have a cache
hit and find that this cache block is dirty, we
Hello, and welcome to the gem5 mailing list :).
I suggest, at least as a first pass, using the classic caches, not Ruby.
You can check out the Learning gem5 book (learning.gem5.org) to see
examples of how to create different kinds of systems that don't necessarily
match what's in se.py. The
Hi all,
(Apologies if you receive multiple copies of this message :))
The gem5 community is hiring a software engineer to develop and improve
gem5's software infrastructure. gem5 is an open source computer
architecture simulator used extensively in both academia and industry. The
gem5 paper has
Thank you very much for your replies.
I will start using classic caches since i do not have to modify coherance
protocol for my work.
kind regards,
Armel
--
*JEATSA TOULEPI Armel*
Étudiant En Génie Informatique
Tel: +237 650771894 / 655296800
Le mer. 10 juil. 2019 à 18:11, Jason Lowe-Power a
