Re: [gem5-users] Micro-op Data Dependency

I don't know that off the top of my head---the ISAs I'm familiar with are either not microcoded, or use a micro-op assembler to generate all the micro-ops (i.e., x86). Have you looked at how ARM micro-ops are constructed? That's the one ISA that I believe is mostly not microcoded but still has so

Re: [gem5-users] Micro-op Data Dependency

Okay, thanks. How do I tell the ISA parser that the 'Rt' operand I've created refers to the extra architectural register? Or is there some function I can call inside the instruction's code that writes directly to an architectural register? All I can see from the code GEM5 generates is "setIntReg

Re: [gem5-users] Physmem in SE Mode (Jason Lowe-Power)

ints or show me the right way to do this? Thank you -- next part -- An HTML attachment was scrubbed... URL: <http://m5sim.org/cgi-bin/mailman/private/gem5-users/attachments/20160802/59cd9c14/attachment-0002.html> -- Messag

Re: [gem5-users] Making a C application work on multiple cores with gem5

Hi Jason for the cores not simultaneously. i read abouat what gem5 support so i will try for example 4 cores of x86 then 4 cores of ARM. And by the way do you have any idea about ARM SIMD instructions please? Thank you On Tue, Aug 2, 2016 at 3:28 PM, Jason Lowe-Power wrote: > Hello, > > If y

Re: [gem5-users] Physmem in SE Mode

Hi Monir, The AbstractMemory class (along with the System class) implements the physical memory of the system. When configuring gem5, if you instantiate a memory object (e.g., DRAMCtrl like DDR3_1600_x64) this object will register the physical memory with the System object. The with the DRAMCtrl,

Re: [gem5-users] Making a C application work on multiple cores with gem5

Hello, If you're using full system mode (FS mode), you can use pthreads or any other threading library just like on a real machine. If you're using syscall emulation (SE) mode, then you can use the m5threads library which is a pthreads-like library (http://repo.gem5.org/m5threads/). If I've misun

[gem5-users] Virtual to Physical Address in ARMv8 FS Classic Memory

Hi all I am currently running an application on 64 core ARMv8 FS with Classic Memory with individual L1 D and I Cache and unified L2 cache. On looking at the cache memory trace, two virtual addresses, one from Kernel space (e.g. 0xffc071a63400) and one from application space (e.g. 0x915400) a

[gem5-users] Making a C application work on multiple cores with gem5

hello I am new with gem5 simulator. I have a C application that i want to make it run faster. So the first thing I've done is to optimize it using several techniques like loop unrolling and SIMD. And the next step, i intend to make it work on *multiple cores* (*X86* and *ARM*) for that i must use