Re: [gem5-users] RISC-V ISA

Thanks for your help everyone! I'm actually pretty far into the implementation--I've mostly completed the 64-bit base ISA and the multiply, atomic, and single- and double-precision floating point extensions (RV64IMAFD) for use in SE mode with the atomic, timing, minor, and detailed CPU models. On

[gem5-users] arm_detailed error

Hi I wanted to work with the O3_ARM_v7a.py after i changed some cache parameters etc.. but when i type this command: * build/ARM/gem5.opt configs/example/se.py --cpu-type=arm_detailed -n 1 --cpu-clock=1GHz --caches --l2cache --mem-type=DDR3_1600_x64 -c /home/anoir/workspace/fft_ARM_unrolled8/ff