Thanks for your help everyone! I'm actually pretty far into the implementation--I've mostly completed the 64-bit base ISA and the multiply, atomic, and single- and double-precision floating point extensions (RV64IMAFD) for use in SE mode with the atomic, timing, minor, and detailed CPU models. Once I've fixed the formatting according to the style guide and tested it with the newest version of GEM5 in the next few days, I can submit the patch.
I did find the Austin Harris project when I was first getting started, but at that point it hadn't been updated in several months and it had no functionality implemented. Mostly I copied from MIPS because RISC-V and MIPS have a lot of similarities. Also, if anyone plans to use this, please cite "RISC5: Implementing the RISC-V ISA in GEM5," which we plan to submit soon. Thanks, Alec Roelke On Fri, Sep 9, 2016 at 10:07 AM, Jason Lowe-Power <ja...@lowepower.com> wrote: > Hi Alex, > > This is very exciting. I think I was just telling somebody a day or two > ago that RISC-V would be great to have in gem5! > > For the submission process see http://gem5.org/Submitting_Contributions. > Also, you should be sure to follow the coding style: > http://gem5.org/Coding_Style. > > In the same vein as what Andreas was saying, a good way to do this is to > post patches for some minimum working version on reviewboard. Once you get > those approved/submitted, then move onto more complicated things (e.g., > privileged instructions, floating point, etc.). It helps that RISC-V is > defined with a minimum set of instructions and then further optional > extensions. > > Looking forward to your patches! > > Cheers, > Jason > > > On Thu, Sep 8, 2016 at 8:20 AM Andreas Hansson <andreas.hans...@arm.com> > wrote: > >> Hi Alec, >> >> I think a good starting point would be to aim for enough functionality to >> have a few regressions working, using some simple test programs, and the >> atomic and timing CPU model. From there you can extend it to eventually >> include basic linux regressions and in-order/out-of-order regressions, >> multi-processor, etc. >> >> Andreas >> >> From: gem5-users <gem5-users-boun...@gem5.org> on behalf of Alec Roelke < >> ar...@virginia.edu> >> Reply-To: gem5 users mailing list <gem5-users@gem5.org> >> Date: Thursday, 8 September 2016 at 03:56 >> >> To: gem5 users mailing list <gem5-users@gem5.org> >> Subject: [gem5-users] RISC-V ISA >> >> Hello, >> >> I'm implementing the RISC-V ISA for GEM5, and I have a few questions: >> >> - How complete should it be before I try to submit it? What features >> should be supported? >> - Is there some kind of submission process? I know about the gem5-dev >> list and patch review board, but how do I submit there? >> >> Thanks, >> Alec Roelke >> IMPORTANT NOTICE: The contents of this email and any attachments are >> confidential and may also be privileged. If you are not the intended >> recipient, please notify the sender immediately and do not disclose the >> contents to any other person, use it for any purpose, or store or copy the >> information in any medium. Thank you. >> _______________________________________________ >> gem5-users mailing list >> gem5-users@gem5.org >> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > > > _______________________________________________ > gem5-users mailing list > gem5-users@gem5.org > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users >
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