Re: [gem5-users] Terminating multi-core simulation

2018-05-29 Thread Muhammad Avais
Dear Haeyoon,

  Many thanks for your help and guidance. I will try to apply
first scheme suggested by you in previous email.

Best Regards,
Avais

On Mon, May 28, 2018 at 1:18 PM, 조해윤  wrote:

> Dear Avais,
>
> I think it is reasonable to normalize with the numbers of executed
> instructions, but it still is a weakness that the running sections of
> benchmarks are not same totally.
> In my case, it was my best to exit the simulation by the total numbers of
> executed instructions.
> But if you can apply FIESTA methodology, it will be better.
>
> Best Regards,
> Haeyoon Cho.
>
> 2018-05-25 12:17 GMT+09:00 Muhammad Avais :
>
>> Dear Haeyoon Cho.,
>>
>> I am really thankful to you for this help. Actually, i am not very good
>> in modifying gem5 and this code will be very helpful for me.
>>
>> I have one more question, is it good idea to normalize the stats with
>> number of instructions simulated to calculate energy or other things? Does
>> people use this? Or some other metric to compare energy?
>>
>> Many thanks for your help,
>> Best Regards,
>> Avais
>>
>> On Thu, May 24, 2018 at 5:45 PM, 조해윤  wrote:
>>
>>> Dear Avais,
>>>
>>> I think running workloads fairly is very important in multi-core
>>> experiments, because the number of executed instructions of each core can
>>> be changed depend on each experimental configuration.
>>> There is a prior work how to experiment fairly on multi-core system; A.
>>> Hilton et al., "FIESTA: A Sample-Balanced Multi-Program Workload
>>> Methodology", MoBS, 2009.
>>> However, implementing this methodology in gem5 is another problem, and I
>>> couldn't do that.
>>>
>>> Alternatively, I modified the gem5 code to terminate by the number of
>>> total executed instructions of all cores.
>>> Existing gem5 code can only terminate by the maximum or minimum number
>>> of executed instructions per core.
>>> Since LocalSimLoopExitEvent() is called in CPU class in existing gem5
>>> code, I modified system class code to correct the number of executed
>>> instructions of all cores and to call LocalSimLoopExitEvent() by system
>>> class.
>>> As I think, the most important part is whether you can call
>>> LocalSimLoopExitEvent() when you want.
>>> I attach total_sim_exit.patch just for reference.
>>> I modified followed six files.
>>> /configs/commom/Simulation.py
>>> /src/sim/system.hh
>>> /src/sim/system.cc
>>> /src/sim/System.py
>>> /src/cpu/simple/base.hh
>>> /src/cpu/o3/cpu.cc
>>> This attached file may not compatible with current gem5 code, because I
>>> modified code base on stable version of gem5 code.
>>> Also, this modification is just for restrictive situation that one fast
>>> forward and one real simulation, and coding style is not good.
>>>
>>> If you can modify gem5 code better than me, please let me know.
>>>
>>> Best Regards,
>>> Haeyoon Cho.
>>>
>>>
>>> 2018-05-23 15:55 GMT+09:00 Muhammad Avais :
>>>
 Dear All,

  I want to measure dynamic energy of L2 cache for multi-core
 simulations. For this purpose, i measure stats from gem5 like # of hits,  #
 of misses and # of writebacks.
  As, multi-core simulation in gem5 terminates, as soon as, any
 workload reaches maximum count. Therefore, while comparing different
 schemes, each scheme terminates after different number of instructions, so
 stats like  # of hits,  # of misses and # of writebacks are not
 useful.
Is there any  other metric that can be used to compare energy in
 multicore systems like weighted speed up for performance. Or is it possible
 that simulation always runs for fixed number of instruction.

 Many Thanks,
 Best Regards,
 Avais

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[gem5-users] Memory models possibilities

2018-05-29 Thread Richard Brown
Hello everyone,

I have been reading several posts in this forum and the gem5 documentation,
I am new with gem5, I  have to work with memory subsystem and I have
already changed characteristics on main memory and cache memory as train.
However I have some questions that I have not answered reading the forum:

1. gem5 has two memory models, i.e. classic and ruby. I need to change the
read and write latencies, to be asymmetric for modeling an NVM memory. I
know it is super easy in the classic model, but I also need to change the
coherence protocol to avoid writes in some cache level, i.e the LLC is
supposed to be an NVM so I do not want to always write on it.

Is it possible to have asymmetric latencies with Ruby model? I tried it,
but I got an error when I simulate in full-system mode, I added asymmetric
latencies and stall the execution if the bank is busy, but many stalls
caused an error. In classic model I do not have problems but the cache
manage is fixed, I think it is a mess to change the cache manage to avoid
writes in one level.

2. I need to access cache line, I need to count the modified bits. Is it
possible to access cache line in both memory models?

3. I have read papers where people use NVMain with gem5, is possible to use
it as cache memory only for LLC? L1 and L2 will be SRAM.

4. I have read some posts where people talk about an unified memory model
for gem5, are there people working on it?

Thanks in advance for any help.

--
All the best
   Rich
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[gem5-users] x86 instructions with microops

2018-05-29 Thread Tariq Azmy
Hi,

How is a particular instruction being decoded, especially when it has
micro-ops? I looked at the stats in commit_impl.hh

if (!inst->isMicroop() || inst->isLastMicroop())
instsCommitted[tid]++;
opsCommitted[tid]++;

Does this means the micro ops is also stored as a Dynamic Inst, with
different PC address? Also where is the file(s) that shows list of
instruction that has microops?

Thanks
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Re: [gem5-users] Issues in handling compressed data for L3 cache

2018-05-29 Thread Jason Lowe-Power
Hi Srajan,

Could you post this on our code review site so the patch creator (Daniel)
can take a look? You can register on the site with a google account (e.g.,
your gmail). Then, you can post a reply on this page:
https://gem5-review.googlesource.com/c/public/gem5/+/9741.

One possible source of your problem is that you have to apply all of the
patches in the relation chain. In this case that would be:
Relation chain
mem-cache: Create Sector Cache

mem-cache: Return evictions along with victims

mem-cache: Use ReplaceableEntry in findBlockBySetAndWay

mem-cache: Make tag a pointer


Thanks,
Jason

On Tue, May 29, 2018 at 4:15 AM Srajan Khare  wrote:

> Hi Jason,
>
> As per your suggestion I included the recently committed patch (for
> creating sector cache) with my gem5 version. Then after, just to get an
> idea of Sector Cache performance, I ran simulation for *bzip2 *SPEC
> CPU2006 benchmark with 1B fast forward and then executing 500M instruction
> in DerivO3CPU mode.
>
> Only modification I did to simulate it, was to take 4 blocks per sector
> instead of default configuration in src/mem/cache/tags/tags.py.
>
> I got following assertion failed after sometime due to which simulation
> got aborted.
>
> ASSERTION FAILED!
>
> gem5.opt: build/X86/mem/cache/write_queue.cc:60: WriteQueueEntry*
> WriteQueue::allocate(Addr, unsigned int, PacketPtr, Tick, Counter):
> Assertion `!freeList.empty()' failed.
>
> -
>
> Could you please have some directions on this failed assertion so that I
> can go ahead with my actual compressed cache implementation?
>
> Thanks a lot in advance!
>
> ~Srajan Khare
>
>
> On Tue, May 29, 2018 at 3:12 PM, Srajan Khare  wrote:
>
>> Thank you Jason for your quick reply!
>>
>>
>> On Sat, May 19, 2018 at 12:50 PM, Srajan Khare  wrote:
>>
>>> Hi friends,
>>>
>>> I have been implementing Cache Compression algorithm in gem5.
>>> So in order to tap data for all the writes into L3 cache I have been
>>> using handleFill() function in cache.cc file. I have been using following
>>> command to transfer data in compressed format into L3 cache.
>>>
>>> ---*Code snippet*-
>>>
>>> //Only for L3 cache
>>> uint8_t *dataofCacheLine;
>>>
>>> memcpy(dataOfCacheLine, pkt->getConstPtr(), blkSize);
>>>
>>> compr_Info = compressionAlgo (dataOfCacheLine, .,
>>> .);
>>>
>>> //compr_Info contains compressed data and new size.
>>> //compressed data is then transferred into blk->data in the following way
>>>
>>> memcpy(blk->data, compr_info.comprData, compr_info.comprSize);
>>>
>>> 
>>>
>>> Doing this leads to SIGABRT signal which terminates the execution with a
>>> panic ("Tried to read unmapped address 0x1a8"). I debugged it with
>>> gdb and log files and got myself zero'd down to error in memcpy statement.
>>>
>>> Could any of you let me know why there is a crash due to second memcpy
>>> statement provided compressed data I am storing is consistent with the
>>> actual data referenced by the block?
>>> Does any addressing gets disturbed when I am doing it like this? If Yes,
>>> could you please give me some inputs on this??
>>>
>>> Thanks a lot in advance!
>>>
>>>
>>>
>>
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Re: [gem5-users] Error in running Moby(Asimbench) benchmark in gem5

2018-05-29 Thread 조해윤
Dear Mitali Sinha.

In my case, I run moby bench with RealView_PBX machine type.
I don't know if it is the cause, but give it a try.

Best Regard,
Haeyoon Cho.

2018-05-29 20:39 GMT+09:00 Mitali Sinha :

> I have followed the instructions provided in the gem5.org website to run
> the Moby benchmarks on gem5 as follows:
>
> 1.  Downloaded the Asimbench from https://bitbucket.org/
> yongbing_huang/asimbench/downloads/ which contains the following folders
> and files:
>  1.  asimbench_android_arm_kernel : vmlinux.smp.ics.arm.asimbench.
> 2.6.35
>  2.  asimbench_boot_scripts : contains the rcs scripts for
> different benchmarks
>  3.  asimbench_disk_image :  ARMv7a-ICS-Android.SMP.Asimbench-v3.img;
> sdcard-1g-mxplayer.img
>
> 2.  I have used the "armv7_gem5_v1_1cpu.dtb" and "boot_emm.arm" binaries
> downloaded from http://www.gem5.org/dist/current/arm/aarch-system-
> 20180409.tar.xz.
> 
>
> 3.  Made the following changes in the config/common/FSConfig.py :
>
> def makeArmSystem(..)
> .
> self.cf0 = CowIdeDisk(driveID='master')
> self.cf2 = CowIdeDisk(driveID='master')
> self.cf0.childImage(mdesc.disk())
> self.cf2.childImage(disk("sdcard-1g-mxplayer.img"))
> # Old platforms have a built-in IDE or CF controller. Default to
> # the IDE controller if both exist. New platforms expect the
> # storage controller to be added from the config script.
> if hasattr(self.realview, "ide"):
> #self.realview.ide.disks = [self.cf0]
> self.realview.ide.disks = [self.cf0, self.cf2]
> elif hasattr(self.realview, "cf_ctrl"):
> #self.realview.cf_ctrl.disks = [self.cf0]
> self.realview.cf_ctrl.disks = [self.cf0, self.cf2]
> else:
> self.pci_ide = IdeController(disks=[self.cf0])
> pci_devices.append(self.pci_ide)
> ...
>
> 4. Used the following command:
>
> build/ARM/gem5.opt configs/example/fs.py --os-type=android-ics
> --machine-type=VExpress_EMM --cpu-type=MinorCPU --caches
> --disk-image=/home/sujay/gem5/full_system_asimbench/disks/
> ARMv7a-ICS-Android.SMP.Asimbench-v3.img --kernel=/home/sujay/gem5/
> full_system_asimbench/binaries/vmlinux.smp.ics.arm.asimbench.2.6.35
> --dtb-filename=/home/sujay/gem5/full_system_asimbench/
> binaries/armv7_gem5_v1_1cpu.dtb --script=/home/sujay/gem5/
> full_system_asimbench/asimbench_boot_scripts/adobe.rcS
>
>
> 5. The above commands throw the following error:
>
>   ..
> Global frequency set at 1 ticks per second
> warn: DRAM device capacity (8192 Mbytes) does not match the address range
> assigned (512 Mbytes)
> info: kernel located at: /home/sujay/gem5/full_system_
> asimbench/binaries/vmlinux.smp.ics.arm.asimbench.2.6.35
> Listening for system connection on port 5900
> Listening for system connection on port 3456
> 0: system.remote_gdb: listening for remote gdb on port 7000
> info: Using bootloader at address 0x10
> info: Using kernel entry physical address at 0x80008000
> warn: DTB file specified, but no device tree support in kernel
>  REAL SIMULATION 
> warn: Existing EnergyCtrl, but no enabled DVFSHandler found.
> info: Entering event queue @ 0.  Starting simulation...
>
> *warn: Device system.membus.badaddr_responder accessed by read to address
> 0x10009018 size=4fatal: Received error response packet for inst:
> 0/13.7/35/140.143 pc: 0x8003aba0 (ldr)*
> Memory Usage: 823816 KBytes
>
>
> Looking for some suggestion regarding successfully running the asimbench
> on gem5. Any help is appreciated. Thanks in advance.
>
>
> --
> Mitali Sinha,
> PhD Scholar,
> IIIT Delhi
>
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[gem5-users] Error in running Moby(Asimbench) benchmark in gem5

2018-05-29 Thread Mitali Sinha
I have followed the instructions provided in the gem5.org website to run
the Moby benchmarks on gem5 as follows:

1.  Downloaded the Asimbench from
https://bitbucket.org/yongbing_huang/asimbench/downloads/ which contains
the following folders and files:
 1.  asimbench_android_arm_kernel :
vmlinux.smp.ics.arm.asimbench.2.6.35
 2.  asimbench_boot_scripts : contains the rcs scripts for
different benchmarks
 3.  asimbench_disk_image :
ARMv7a-ICS-Android.SMP.Asimbench-v3.img; sdcard-1g-mxplayer.img

2.  I have used the "armv7_gem5_v1_1cpu.dtb" and "boot_emm.arm" binaries
downloaded from http://www.gem5.org/dist/current/arm/
aarch-system-20180409.tar.xz.


3.  Made the following changes in the config/common/FSConfig.py :

def makeArmSystem(..)
.
self.cf0 = CowIdeDisk(driveID='master')
self.cf2 = CowIdeDisk(driveID='master')
self.cf0.childImage(mdesc.disk())
self.cf2.childImage(disk("sdcard-1g-mxplayer.img"))
# Old platforms have a built-in IDE or CF controller. Default to
# the IDE controller if both exist. New platforms expect the
# storage controller to be added from the config script.
if hasattr(self.realview, "ide"):
#self.realview.ide.disks = [self.cf0]
self.realview.ide.disks = [self.cf0, self.cf2]
elif hasattr(self.realview, "cf_ctrl"):
#self.realview.cf_ctrl.disks = [self.cf0]
self.realview.cf_ctrl.disks = [self.cf0, self.cf2]
else:
self.pci_ide = IdeController(disks=[self.cf0])
pci_devices.append(self.pci_ide)
...

4. Used the following command:

build/ARM/gem5.opt configs/example/fs.py --os-type=android-ics
--machine-type=VExpress_EMM --cpu-type=MinorCPU --caches
--disk-image=/home/sujay/gem5/full_system_asimbench/disks/ARMv7a-ICS-Android.SMP.Asimbench-v3.img
--kernel=/home/sujay/gem5/full_system_asimbench/binaries/vmlinux.smp.ics.arm.asimbench.2.6.35
--dtb-filename=/home/sujay/gem5/full_system_asimbench/binaries/armv7_gem5_v1_1cpu.dtb
--script=/home/sujay/gem5/full_system_asimbench/asimbench_boot_scripts/adobe.rcS


5. The above commands throw the following error:

  ..
Global frequency set at 1 ticks per second
warn: DRAM device capacity (8192 Mbytes) does not match the address range
assigned (512 Mbytes)
info: kernel located at:
/home/sujay/gem5/full_system_asimbench/binaries/vmlinux.smp.ics.arm.asimbench.2.6.35
Listening for system connection on port 5900
Listening for system connection on port 3456
0: system.remote_gdb: listening for remote gdb on port 7000
info: Using bootloader at address 0x10
info: Using kernel entry physical address at 0x80008000
warn: DTB file specified, but no device tree support in kernel
 REAL SIMULATION 
warn: Existing EnergyCtrl, but no enabled DVFSHandler found.
info: Entering event queue @ 0.  Starting simulation...

*warn: Device system.membus.badaddr_responder accessed by read to address
0x10009018 size=4fatal: Received error response packet for inst:
0/13.7/35/140.143 pc: 0x8003aba0 (ldr)*
Memory Usage: 823816 KBytes


Looking for some suggestion regarding successfully running the asimbench on
gem5. Any help is appreciated. Thanks in advance.


-- 
Mitali Sinha,
PhD Scholar,
IIIT Delhi
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Re: [gem5-users] Issues in handling compressed data for L3 cache

2018-05-29 Thread Srajan Khare
Hi Jason,

As per your suggestion I included the recently committed patch (for
creating sector cache) with my gem5 version. Then after, just to get an
idea of Sector Cache performance, I ran simulation for *bzip2 *SPEC CPU2006
benchmark with 1B fast forward and then executing 500M instruction in
DerivO3CPU mode.

Only modification I did to simulate it, was to take 4 blocks per sector
instead of default configuration in src/mem/cache/tags/tags.py.

I got following assertion failed after sometime due to which simulation got
aborted.

ASSERTION FAILED!

gem5.opt: build/X86/mem/cache/write_queue.cc:60: WriteQueueEntry*
WriteQueue::allocate(Addr, unsigned int, PacketPtr, Tick, Counter):
Assertion `!freeList.empty()' failed.

-

Could you please have some directions on this failed assertion so that I
can go ahead with my actual compressed cache implementation?

Thanks a lot in advance!

~Srajan Khare


On Tue, May 29, 2018 at 3:12 PM, Srajan Khare  wrote:

> Thank you Jason for your quick reply!
>
>
> On Sat, May 19, 2018 at 12:50 PM, Srajan Khare  wrote:
>
>> Hi friends,
>>
>> I have been implementing Cache Compression algorithm in gem5.
>> So in order to tap data for all the writes into L3 cache I have been
>> using handleFill() function in cache.cc file. I have been using following
>> command to transfer data in compressed format into L3 cache.
>>
>> ---*Code snippet*-
>>
>> //Only for L3 cache
>> uint8_t *dataofCacheLine;
>>
>> memcpy(dataOfCacheLine, pkt->getConstPtr(), blkSize);
>>
>> compr_Info = compressionAlgo (dataOfCacheLine, .,
>> .);
>>
>> //compr_Info contains compressed data and new size.
>> //compressed data is then transferred into blk->data in the following way
>>
>> memcpy(blk->data, compr_info.comprData, compr_info.comprSize);
>>
>> 
>>
>> Doing this leads to SIGABRT signal which terminates the execution with a
>> panic ("Tried to read unmapped address 0x1a8"). I debugged it with
>> gdb and log files and got myself zero'd down to error in memcpy statement.
>>
>> Could any of you let me know why there is a crash due to second memcpy
>> statement provided compressed data I am storing is consistent with the
>> actual data referenced by the block?
>> Does any addressing gets disturbed when I am doing it like this? If Yes,
>> could you please give me some inputs on this??
>>
>> Thanks a lot in advance!
>>
>>
>>
>
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Re: [gem5-users] Issues in handling compressed data for L3 cache

2018-05-29 Thread Srajan Khare
Thank you Jason for your quick reply!


On Sat, May 19, 2018 at 12:50 PM, Srajan Khare  wrote:

> Hi friends,
>
> I have been implementing Cache Compression algorithm in gem5.
> So in order to tap data for all the writes into L3 cache I have been using
> handleFill() function in cache.cc file. I have been using following command
> to transfer data in compressed format into L3 cache.
>
> ---*Code snippet*-
>
> //Only for L3 cache
> uint8_t *dataofCacheLine;
>
> memcpy(dataOfCacheLine, pkt->getConstPtr(), blkSize);
>
> compr_Info = compressionAlgo (dataOfCacheLine, .,
> .);
>
> //compr_Info contains compressed data and new size.
> //compressed data is then transferred into blk->data in the following way
>
> memcpy(blk->data, compr_info.comprData, compr_info.comprSize);
>
> 
>
> Doing this leads to SIGABRT signal which terminates the execution with a
> panic ("Tried to read unmapped address 0x1a8"). I debugged it with
> gdb and log files and got myself zero'd down to error in memcpy statement.
>
> Could any of you let me know why there is a crash due to second memcpy
> statement provided compressed data I am storing is consistent with the
> actual data referenced by the block?
> Does any addressing gets disturbed when I am doing it like this? If Yes,
> could you please give me some inputs on this??
>
> Thanks a lot in advance!
>
>
>
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