Re: [gem5-users] Integrating Orion Power Simulator with Garnet

[Krishna, Tushar]

Hi Faisal,
Orion is outdated. We used to have it as part of garnet long back but removed 
it.
gem5 now has DSENT (https://sites.google.com/site/mitdsent/) integrated.
It is in ext/dsent

The idea is to run dsent at the end of your simulation and it parses the 
config.ini and stats.txt files and reports network power and area.
The parser is here: util/on-chip-network-power-area.py

Last I had checked, the parser for it was broken. I had a patch to fix it but 
haven't pushed it into the main repo.

Here  they are:
dsent.diff
dsent_garnet_parser.diff

I just checked the parser patch and it doesn’t work with the latest version of 
gem5, but you can update the parser. I plan to do it at some point, but not in 
the next few weeks for sure.


Usage:
python ./util/on-chip-network-power-area.py   [ (optional)]

Example: python ./util/on-chip-network-power-area.py . m5out 
ext/dsent/configs/garnet_router.cfg ext/dsent/configs/garnet_link.cfg 32 500
This will model 500ps (2GHz) at 32nm

This will first build dsent, and then run it.
You need to update ext/dsent/CMakeLists.txt to point to the right gcc and g++ 
library as you can see in the dsent.diff patch.

Cheers,
Tushar

On Jul 4, 2018, 11:58 AM -0400, dipu.7...@gmail.com , 
wrote:
Dear All,

I would like to integrate the Orion 2.0 with the new garnet 2.0 simulator. As 
garnet 2.0 has some additional features, I would like exploit the additional 
features along with the Orion power analysis. Hence, it will be very much 
helpful to know the procedure to incorporate the Orion simulator with the 
garnet 2.0.

Thanks in advance.

Best regards,

F.A. Faisal
-
Doctoral Student, JAIST
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Re: [gem5-users] size variable in Packet class

[Google]

Hi Nikos,

Thanks for your help. 

I tried all possible flags, but I was not able to get the value of those 
variables. If you come across any different approach, then do suggest

Thanks again.

Riddhi  

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Re: [gem5-users] size variable in Packet class

[Nikos Nikoleris]

Riddhi,

You can get the values of these registers if you add some more Exec* flags. 
IIRC ExecResult might be useful as well. You can see the full list of debug 
flags with --debug-help.

Nikos


From: gem5-users  on behalf of Google 

Reply-To: gem5 users mailing list 
Date: Wednesday, 11 July 2018 at 10:52
To: "gem5-users@gem5.org" 
Subject: Re: [gem5-users] size variable in Packet class

Hi Nikos,

Thanks again. You actually did give an useful hint.
I used these flags, and I got following type of data:

system.cpu 0x3698a02f73: movDS:[r12 + 0x340], rsi
system.cpu 0x3698a02f73.0  :   MOV_M_R : st   rsi, DS:[r12 + 0x340] :
system.cpu 0x3698a02f7b: subrsi, DS:[r12]
system.cpu 0x3698a02f7b.0  :   SUB_R_M : ld   t1, DS:[r12] :
system.cpu 0x3698a02f7b.1  :   SUB_R_M : sub   rsi, rsi, t1 :
system.cpu 0x3698a02f7f: addDS:[r12 + 0x348], rsi
system.cpu 0x3698a02f7f.0  :   ADD_M_R : ldst   t1, DS:[r12 + 0x348] :
system.cpu 0x3698a02f7f.1  :   ADD_M_R : add   t1, t1, rsi :
system.cpu 0x3698a02f7f.2  :   ADD_M_R : st   t1, DS:[r12 + 0x348] :
system.cpu 0x3698a02f87: addDS:[r12 + 0x350], rsi
system.cpu 0x3698a02f87.0  :   ADD_M_R : ldst   t1, DS:[r12 + 0x350] :
system.cpu 0x3698a02f87.1  :   ADD_M_R : add   t1, t1, rsi :
system.cpu 0x3698a02f87.2  :   ADD_M_R : st   t1, DS:[r12 + 0x350] :
system.cpu 0x3698a02f92: addrcx, DS:[r12 + 0x10]
system.cpu 0x3698a02f92.0  :   ADD_R_M : ld   t1, DS:[r12 + 0x10] :
system.cpu 0x3698a02f92.1  :   ADD_R_M : add   rcx, rcx, t1 :
system.cpu 0x3698a02f97: movDS:[r12], rsi


From this I can make out that ADD instruction are taking place. Consider this: 
ADD_R_M: add rcx, rcx, t1: I want the value of these variable rcx, t1, etc. If 
you can think of someway to get this, then it would be great.

Thanks a lot for your help. It was really helpful.

Regards,
Riddhi

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Re: [gem5-users] size variable in Packet class

[Google]

Hi Nikos,

Thanks again. You actually did give an useful hint. 
I used these flags, and I got following type of data:

system.cpu 0x3698a02f73: movDS:[r12 + 0x340], rsi
system.cpu 0x3698a02f73.0  :   MOV_M_R : st   rsi, DS:[r12 + 0x340] :
system.cpu 0x3698a02f7b: subrsi, DS:[r12]
system.cpu 0x3698a02f7b.0  :   SUB_R_M : ld   t1, DS:[r12] :
system.cpu 0x3698a02f7b.1  :   SUB_R_M : sub   rsi, rsi, t1 :
system.cpu 0x3698a02f7f: addDS:[r12 + 0x348], rsi
system.cpu 0x3698a02f7f.0  :   ADD_M_R : ldst   t1, DS:[r12 + 0x348] :
system.cpu 0x3698a02f7f.1  :   ADD_M_R : add   t1, t1, rsi :
system.cpu 0x3698a02f7f.2  :   ADD_M_R : st   t1, DS:[r12 + 0x348] :
system.cpu 0x3698a02f87: addDS:[r12 + 0x350], rsi
system.cpu 0x3698a02f87.0  :   ADD_M_R : ldst   t1, DS:[r12 + 0x350] :
system.cpu 0x3698a02f87.1  :   ADD_M_R : add   t1, t1, rsi :
system.cpu 0x3698a02f87.2  :   ADD_M_R : st   t1, DS:[r12 + 0x350] :
system.cpu 0x3698a02f92: addrcx, DS:[r12 + 0x10]
system.cpu 0x3698a02f92.0  :   ADD_R_M : ld   t1, DS:[r12 + 0x10] :
system.cpu 0x3698a02f92.1  :   ADD_R_M : add   rcx, rcx, t1 :
system.cpu 0x3698a02f97: movDS:[r12], rsi


>From this I can make out that ADD instruction are taking place. Consider this: 
>ADD_R_M: add rcx, rcx, t1: I want the value of these variable rcx, t1, etc. If 
>you can think of someway to get this, then it would be great.

Thanks a lot for your help. It was really helpful.

Regards,
Riddhi

Sent from Mail for Windows 10

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Re: [gem5-users] size variable in Packet class

[Nikos Nikoleris]

Hi Riddhi,

I am not familiar with a way to trace the ALU operations and operands. You 
could trace the micro-ops and macro-ops and then post-process the trace to 
filter out the ALU operations. If you wish to do that then have a look at the 
Exec* debug flags. I believe the debug flags 
ExecEnable,ExecMicro,ExecMacro,ExecUser,ExecKernel will be useful.

Nikos

From: gem5-users  on behalf of Google 

Reply-To: gem5 users mailing list 
Date: Tuesday, 10 July 2018 at 12:13
To: "gem5-users@gem5.org" 
Subject: Re: [gem5-users] size variable in Packet class

Hi Nikos,

Thanks once again. I figured that out.

Can you help me in getting instruction trace for ALU ? I tried doing this for 
X86 system.
What I am trying to do us to get instruction traces for ALU.
What I did:
There is a file, regop.isa (src/arch/x86/isa/microops/). In this file, at line 
506, ADD function is defined. I tried to get the values of psrc1, op2 and 
DestReg, but I don’t think that these are instruction trace. I have attached a 
patch of results below:

2117728 8 2117736
27263459 0 27263459
2117736 8 2117744
29360611 0 29360611
2117744 8 2117752
31457763 0 31457763
2117752 8 2117760
33554915 0 33554915
2117760 8 2117768
35652067 0 35652067
2117768 8 2117776
37749219 0 37749219
2117776 8 2117784
39846371 0 39846371
2117784 8 2117792
2117792 8 2117800
2117800 8 2117808
2117808 8 2117816
2117816 8 2117824
2117824 8 2117832
2117832 8 2117840
2117840 8 2117848

The first column is for psrc1, second for op2 and third is for DestReg. If u 
notice every time the DestReg becomes psrc1 for next operation. And this kind 
of pattern is observed in complete traces. I don’t think this is the 
instruction trace for ALU. And I am not able to find where the ALU instructions 
are defined. I also tried getting traces from mediaop.isa (same folder), but 
sometimes traces are not at all generated. I don’t why.

Any suggestions would a great help to me.

Thanks in advance.

Regards,
Riddhi

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