Hi all,
To avoid sending the response to CPU in case of a prefetch request, while
giving the response in recvTimingResp(), it will check the target source, if it
is a prefetch it will delete the req and the packet. Now, if a prefetch
request from L1 is a miss in L1 and as well as a miss in L2.
Hi Theo,
Yes, it's quite fishy that you're seeing SC_Failed when running an x86
binary.
Looking at the code, and to stay with the fish metaphor, I think that it's
a red herring. See line 287 in Sequencer.cc. It just always prints
llscSuccess whether or not the instruction is an LLSC instruction!
Hi all,
I am trying to learn how to implement cache coherence protocols in gem5 using
SLICC.
I am currently working on an MSI protocol, similar to the one described in the
gem5 book.
The protocol passes the random tester for X86
(`configs/learning_gem5/part3/ruby_test.py`), even when faced with
Forwarding reply to mailing list.
-- Forwarded message -
From: Anuj Falcon
Date: Fri, Jul 3, 2020 at 8:05 AM
Subject: Re: [gem5-users] How to check ...
To: Ciro Santilli
Below is the link to the GEM5 model. (Public)
https://gitlab.com/shaktiproject/tools/core-models-gem5
On Fr
