[gem5-users] Handling a cache miss in gem5

2020-09-23 Thread Aritra Bagchi via gem5-users
Hi all, While experimenting with gem5 classic cache, I tried to find out how an access miss is handled and with what latency. Even if in *cache/tags/base_set_assoc.hh*, the access (here a miss) handling latency *"lat"* gets assigned to the *"lookupLatency"*, the actual latency that is used to han

[gem5-users] Re: Tracking read()/write() system calls in gem5

2020-09-23 Thread Ciro Santilli via gem5-users
Also have a look at --debug-flags SyscallBase,SyscallVerbose On Tue, Sep 22, 2020 at 8:26 PM ABD ALRHMAN ABO ALKHEEL via gem5-users wrote: > > Hi All, can I track the read()/write() system calls in GEM5 in SE mode? If > so, how I can do that? Any help would be appreciated. Thanks >

[gem5-users] Using perf_event with the ARM PMU inside gem5 on Linux

2020-09-23 Thread Pierre Ayoub via gem5-users
Hi gem5's users, TL;DR: -- I know that the ARM PMU is partially implemented, thanks to the gem5 source code and some publications. I have a binary which uses perf_event to access the PMU on a Linux-based OS, under an ARM processor, on real hardware. Could it use perf_event inside a gem5