[gem5-users] Any one bootup with fs.py in gem5 version 20.1 with dramsim3 or nvmain succuessfully

[Liyichao via gem5-users]

Hi All:
 I use gem5 20.1 ,and bootup with fs.py and dramsim3 model,but some 
error printed.

 As I know, gem5 20.1 new feature has departed the medium interface 
from memctrl, however, these modifications are only for the DRAM model inside 
gem5, I think external memory Dramsim3 and NVmain do not adapt to these changes.


my script:
./build/ARM/gem5.opt --debug-flags=DRAM -d ./m5out configs/example/fs.py 
--cpu-type=O3_ARM_v7a_3 --kernel=vmlinux -n 2 --machine-type=VExpress_GEM5_V1 
--disk-image=aarch64-ubuntu-trusty-headless.img --bootloader 
./system/arm/bootloader/arm64/boot.arm64 --caches --l2cache 
--checkpoint-dir=./m5out --mem-type=DRAMsim3 --mem-size=2GB

Error:
Traceback (most recent call last):
File "", line 1, in 
File "build/ARM/python/m5/main.py", line 457, in main
exec(filecode, scope)
File "configs/example/fs.py", line 339, in 
test_sys = build_test_system(np)
File "configs/example/fs.py", line 234, in build_test_system
MemConfig.config_mem(options, test_sys)
File "/home/l30005758/upstream/configs/common/MemConfig.py", line 237, in 
config_mem
mem_ctrl.dram = dram_intf
File "build/ARM/python/m5/SimObject.py", line 1337, in _setattr_
value = param.convert(value)
File "build/ARM/python/m5/params.py", line 215, in convert
return self.ptype(value)
TypeError: _init_() takes 1 positional argument but 2 were given
Error setting param MemCtrl.dram to 

李翼超（Charlie）

华为技术有限公司 Huawei Technologies Co., Ltd.
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[gem5-users] How to test the benchmarks' speedup using ARM SVE?

[有谁共鸣 via gem5-users]

Hi everyone:
I have ran a C language benchmark containing SVE intrinsics in gem5. When I 
adapt the different SVE vector bit width in se mode, I will get some 
performance improvement. However, the performance changed hardly in fs mode, 
even irregular. I wonder why ithappens?The following is the command I used in 
gem5 se mode:
$ ./build/ARM/gem5.opt -d sve_se/ configs/example/se.py -c ./benchmark/demo 
--cpu-type="O3_ARM_v7a" --caches --param 'system.cpu[:].isa[:].sve_vl_se = 2'


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[gem5-users] Re: Add FLUSH in MESI prtocol

[1154063264--- via gem5-users]

Hello Jason:
I defined the following transitions when flushing is executed in the I state, I 
did not use ruby_random_test.py to test at first, but created checkpoint in SE 
mode, and no error was reported, printed information shows flush_line I->I.
But when I execute the following command line, use ruby_random_test.py to test, 
and modify the script to test flush, when this transition(I, Flush_line) is 
executed, it stops.

Command:
--debug-flags=ProtocolTrace ./configs/example/ruby_random_test.py -n 4 --ruby

transition(I, Flush_line) {
flushRespsonse;
}

action(flushResponse) {
sequencer.writeCallbackScFail(address, cache_entry.DataBlk);
}
writeCallbackScFail is on the sequencer
void
Sequencer::writeCallbackScFail(Addr address, DataBlock& data)
{
llscClearMonitor(address);
writeCallback(address, data);
}
__
I don't know why this error reported in Ruby random tester, Is it because I 
can't use writeCallbackScFail as the flush response when block is in I? If so, 
how can the  flush be handled more appropriately?
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[gem5-users] Re: Some Question About Cache in Gem5

[522808087--- via gem5-users]

Thank's your reply,bobby.
I am confused at how I can know which level the cache is working.when debugging 
gem5,The packet was transmit from one port to another,but the port belong to 
which Cache,L1 or L2? (For example, after L1 MISS, look for data in L2 ).Best 
wish.
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[gem5-users] Re: A question regarding to VIPT/PIPT

[Leon Zhao via gem5-users]

Hi Ayaz,

I can't thank you enough for you reply. I'm aware of the fact that from 
software's perspective, VIPT and PIPT should be functioning equally but what 
piqued my interest is what it looks like from hardware's perspective.

Let's say both i-cache and d-cache are working under PIPT, do you have any idea 
about what I should do if I want to implement VIPT in gem5, hopefully with no 
aliasing problem? Any pointers would do.

Also, I scrutinized the page you mentioned above, but sadly there's no 
arch/arm/kernel/setup.c in my gem5 directory.

Thank you again and looking forward to your reply!
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[gem5-users] Re: A question regarding to VIPT/PIPT

[Ayaz Akram via gem5-users]

Hi Leon,

In gem5, the caches are PIPT technically. But, you can model the timing of
a VIPT cache by changing the latency of your cache. As far as the kernel
boot log is concerned, I am not fully sure if "CPU: PIPT / VIPT nonaliasing
data cache, PIPT instruction cache" refers to the actual hardware cache.
Even if it is, VIPT and PIPT should be treated in the same way from
software's perspective. Following link might be helpful to know what kernel
is exactly doing when this message is printed:

https://linux-arm-kernel.infradead.narkive.com/xBwIht4D/about-cachetype-on-armv7

-Ayaz

On Sat, Oct 17, 2020 at 12:21 AM Leon Zhao via gem5-users <
gem5-users@gem5.org> wrote:

> Hi everyone,
> I was running the following command in gem5 the other day:
>
> ..gem5.opt configs/example/fs.py --ruby --cpu-type=O3_ARM_N1
> --script=tests/test-progs/hello/bin/arm/linux/hello
> --kernel=/home/hippo/full_system_images/binaries/vmlinux.vexpress_gem5_v1.20170616
>
> and I noticed this appeared in the output:
>
> [0.00] CPU: ARMv7 Processor [410fc0f0] revision 0 (ARMv7),
> cr=14c5387d
> [0.00] CPU: PIPT / VIPT nonaliasing data cache, PIPT instruction
> cache
>
> So when it says "PIPT / VIPT nonaliasing data cache", does it mean that on
> the level of data cache, there are two different routes (a) PIPT and (b)
> VIPT with no aliasing, or are they basically the same thing just with a
> difference in names?
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[gem5-users] Re: Some Question About Cache in Gem5

[Bobby Bruce via gem5-users]

Hey,

I'm not sure I understand exactly what you're asking. I assume you're
learning from the "learning gem5" tutorial (here :
http://www.gem5.org/documentation/learning_gem5/introduction/)? If so,
could you point us towards the exact part that's confusing you?

Kind regards,
Bobby

--
Dr. Bobby R. Bruce
Room 2235,
Kemper Hall, UC Davis
Davis,
CA, 95616

web: https://www.bobbybruce.net


On Sun, Oct 18, 2020 at 6:27 AM 522808087--- via gem5-users <
gem5-users@gem5.org> wrote:

> hi,all.I am learning gem5,I know the Cache is heriarchy level,but  i can't
> distinguishhow the message was deliver between L1Cache and L2 Cache(eg.When
> L1 miss,find the blk in L2).Do you someone Know? Best wish.
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[gem5-users] Re: Configure multi-bank cache in ruby ​mode with MESI coherence protocol

[Jason Lowe-Power via gem5-users]

Hello,

It depends on how you want to model banking. If you just want to set and
limit the bandwidth to a cache, you can use the "resourceStalls = true"
option on the RubyCache object and set the tag and data array values. You
will also have to tag every transition in the cache controller (i.e.,
MESI_Two_Level-L2cache.sm) with the required resources (see MOESI_hammer
for an example).

If you want to model a distributed cache, then you can configure your "L2"
caches to have a slice of the address range and update the
"mapAddressToRange" function to map the addresses to the correct
distributed caches. This could be as simple as setting the
l2_select_num_bits parameter on the "L1" caches.

Cheers,
Jason

On Wed, Oct 14, 2020 at 7:15 PM 1154063264--- via gem5-users <
gem5-users@gem5.org> wrote:

> I want to implement multi-bank cache in ruby ​​mode， and I use the
> MESI_Three_Level protocol to maintain the consistency of the three-level
> cache. Which scripts should I modify to realize multi-bank cache ？
>
> （1) Do I need to modify all the .sm files in src/mem/ruby/protocol/,  such
> as,  MESI_Three_Level-L0cache.sm , L1cache.sm
> To Modify variables such as out_msg.Dest in the above script ?
>
> (2） Or the implementation of multi-bank cache is independent of the
> protocol and should not be modified in the above script ？
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[gem5-users] Re: Add FLUSH in MESI prtocol

[Jason Lowe-Power via gem5-users]

Hello,

It's difficult for me to say for certain without digging much deeper.
However, my gut says the latter is probably closer to correct. I doubt that
you can drop the line without first receiving an ack (somehow).

I'm not sure if this was said before, but you can use the Ruby random
tester in conjunction with the "test flushes" option to test what you're
working on. If you pass the tester with a few million loads, various sizes
of caches, etc. there is at least some confidence your implementation works
:).

Cheers,
Jason

On Fri, Oct 16, 2020 at 5:46 PM 1154063264--- via gem5-users <
gem5-users@gem5.org> wrote:

> Hello Jason:
> For  L0 cache in the MESI_Three_Level protocol, the cache block is
> initially in the M state, I considered two ways of state transition, which
> one do you think is more reasonable ？
> (1) In this case, the M state of L0 is directly changed to the I state,
> and the data is directly sent to L1;
>
>   transition(M, Flush_line, I) {
> forward_eviction_to_cpu;
> f_sendDataToL1;
> ff_deallocateCacheBlock;
> k_popMandatoryQueue;
> }
> -
> （2）In this case, the M state of L0 first becomes the MI_F intermediate
> state, and the PUTF request is sent to L1.  when L0 receiving the InvElse
> responded by L1, it is converted to the I state;
>
>   transition(M, Flush_line, MI_F) {
> i_allocateTBE;
> hh_flush_hit;
> gf_issuePUTF;
> forward_eviction_to_cpu;
> ff_deallocateCacheBlock;
> k_popMandatoryQueue;
>   }
>
>   transition({MI_F}, InvElse, I) {
> f_sendDataToL1;
> s_deallocateTBE;
> o_popIncomingResponseQueue;
> }
> --
> I don’t know which design above is more reasonable？ Looking forward to
> your reply.
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[gem5-users] Re: How to Set ROI In Benchmark

[Hoa Nguyen via gem5-users]

Hi Tracy,

The example of PARSEC benchmark mentioned in the documentation page
can be found here,

https://github.com/darchr/parsec-benchmark/commits/gem5-20-annotations

Regards,
Hoa Nguyen

On 10/13/20, Tracy Mac via gem5-users  wrote:
> Hi ALL!
>
> I try to run spec2006 in gem5 full system mode under the arm architecture
> .There are some regions of interest in the application.
> 1. I want to run them by gem5. I don't know where in gem5 can set the start
> and end points of these ROIs and the number of commands between them.
> 2. I found some samples in
> https://www.gem5.org/documentation/general_docs/checkpoints/, but only part
> of the code, I don't know where to find a more detailed script.
>
> I would appreciate it if you could help me !
>
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[gem5-users] Why fs_bigLITTLE.py always use /dev/vda1 as its storage disks device?

[Liyichao via gem5-users]

Hi All:

 How to modify the storage device driver,virtio_blk? As I know, the 
device name using fs.py is /dev/sda1.

 Because I have met a error using fs_bigLITTLE.py when I restore from 
checkpoint, the below print in system.terminal accured, and fs.py will never 
accur.(I have tried to use fs_bigLITTLE.py and fs.py with the same 
kernel/image/dtb)

[cid:image002.png@01D6A650.1C2464F0]


李翼超（Charlie）

华为技术有限公司 Huawei Technologies Co., Ltd.
[Company_logo]
部门：计算系统与组件开发部 [云与计算BG]
手　　机：15858232899
电子邮件：liyic...@huawei.com
地址：中国(China)-杭州(Hangzhou)-滨江区江淑路360号华为杭州研发中心Z4# [3-A06]

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