[gem5-users] Re: How to use the new libm5.a

2020-10-28 Thread Gabe Black via gem5-users 
Hi Wenqi. You do still need to call map_m5_mem(), but as you found, now
that there isn't one baked in call mechanism in the library you need to
call the version of the function that will use the invocation mechanism you
need. The header doesn't have declarations for them all, but if you declare
your own with the same signature and an _addr suffix, you can call that and
use the magic address based calling mechanism.

Gabe

On Wed, Oct 28, 2020 at 10:49 AM Wenqi Yin via gem5-users <
gem5-users@gem5.org> wrote:

> Hi Hoa, Gabe,
>
> Thanks for your help! But just want to confirm this: what I did in the
> past is calling map_m5_mem() in my code first and then call specific m5
> functions, and it seems to work. The guest in running on KvmCPU.
>
> When I am trying to do the same thing with the new libm5.a, it gave an
> exception (Illegal Instruction), however I haven’t looked into the error
> carefully yet, it may just because for some reason the lib is still trying
> to use the magic instruction interface. But before I proceed any further,
> just want to make sure I was using the correct approach to do this.
>
> Best,
> Wenqi
>
> On Oct 26, 2020, at 23:30, Gabe Black via gem5-users 
> wrote:
>
> Hi Wenqi. The updated libm5.a should be used in basically the same way as
> the old version. Just link against the library, include the header file,
> and call into the op you want using the normal function call syntax.
>
> Hoa, the documentation you've linked to is a little out of date. How can
> it be updated?
>
> Gabe
>
> On Sun, Oct 25, 2020 at 9:31 PM Hoa Nguyen via gem5-users <
> gem5-users@gem5.org> wrote:
>
>> Hi Wenqi,
>>
>> We have some documentation about the new m5 utility here:
>> https://www.gem5.org/documentation/general_docs/m5ops/
>>
>> The following link is an example of annotating PARSEC:
>> https://github.com/darchr/parsec-benchmark/commits/gem5-20-annotations
>>
>> Regards,
>> Hoa Nguyen
>>
>> On 10/25/20, wqyin--- via gem5-users  wrote:
>> > Hello all,
>> >
>> > I noticed the util/m5 has big changes since this
>> > commit:26454e8072e607d54ac67c42b33355d7c94d6d60 around Apr 27. I am
>> > wondering how should I use this new interface/implementation to call
>> > m5ops in my program? Shall I also instantiate a default CallType and
>> > then use it to obtain the dispatch table and finally pass it to
>> > Command::run? Also is there any examples which use the new
>> > implementation to annotate any benchmarks running inside gem5? Thanks
>> >
>> > Best,
>> >
>> > Wenqi
>> >
>> >
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[gem5-users] Re: Configure multi-bank cache in ruby ​mode with MESI coherence protocol

2020-10-28 Thread Jason Lowe-Power via gem5-users 
Hello,

For (1), yes. You can set this *in the python configuration file*. You
should not modify the SimObject description file to change a default
parameter.

For (2), yes, that's exactly where you should modify.

Cheers,
Jason

On Wed, Oct 28, 2020 at 9:47 AM zhen bang via gem5-users <
gem5-users@gem5.org> wrote:

> Hello Jason:
> I would use the resource stalls to model banking, I have read
> src/mem/ruby/structures/Rubycache.py and
> src/mem/ruby/structures/BankedArray.cc
> (1)  I have seen
> dataArrayBanks = Param.Int(1, "Number of banks for the data array")
> tagArrayBanks = Param.Int(1, "Number of banks for the tag array")
>
> If I want to configure multiple banks, can I directly modify these
> parameters?
>
> (2) To extend the BankedCache implementation to model arbitrary address
> interleaving, which files or functions should I modify?
> Should I modify the following function in
> src/mem/ruby/structures/BankedArray.cc?
> unsigned int
> BankedArray::mapIndexToBank(int64_t idx)
> {
> if (banks == 1) {
> return 0;
> }
> return idx % banks;
> }
>
> Looking forward to your reply.
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[gem5-users] Re: SE Mode and Std::thread

2020-10-28 Thread Daniel Gerzhoy via gem5-users 
Looks like this is related to this change:

https://gem5-review.googlesource.com/c/public/gem5/+/8184

I'm a bit behind develop because of custom changes and don't have this
patch merged yet.
Cherry picking this might work, but merging would probably be the best
solution, if time consuming.

Cheers,
Dan


On Tue, Oct 27, 2020 at 3:39 PM Daniel Gerzhoy 
wrote:

> Hey all,
>
> I'm running into a strange issue where threads are not spawning when
> launched with std::thread. It seems to work once, and then I try to launch
> again using a newly allocated thread pointer (after deleting the old one)
> and it hangs.
>
> Minimal example:
>
> void foo()
> {
>   printf("Foo alive from tid %lu\n", m5_cpu_id());
>   //m5_cpu_id is a pseudo_instruction I added to return tc->cpuId()
> }
>
> void main()
> {
>   printf("Launching foo 1"\n);
>   std::thread * mythread = new std::thread(foo,...);
>   printf("Done Launching foo 1"\n);
>
>   printf("Joining foo 1"\n);
>   myThread->join();
>   delete myThread;
>
>   printf("Launching foo 2"\n);
>   mythread = new std::thread(foo,...);
>   printf("Done Launching foo 2"\n);
>
>   printf("Joining foo 2"\n);
>   myThread->join(); //< IT HANGS HERE
>   printf("Done Everything!\n");
>   delete myThread;
> }
>
> __
>
> It works fine with TimingSimpleCPU, but then with DerivO3CPU I get the
> failure.
>
> Output for  DerivO3CPU:
>   Launch 1
>   Done Launch 1
>   I'm alive on tid 1
>   Launch 2
>   Done Launch 2
>
> And there it Hangs.
>
> FYI I am using apu_se.py, though with the above minimal example I've
> managed to reproduce the bug with no GPU code (nor even hipcc) involved.
>
> I went back to the original code I found that showed std::thread could be
> used here:
> https://www.gem5.org/documentation/learning_gem5/part3/running/
>
> [image: image.png]
>
> The comment there that -1 is required for SE mode, and then the subsequent
> comment about appeasing SE mode...
>
> What exactly do those comments mean?
>
> I'm going to keep debugging, but if anyone has any suggestions for debug
> flags that could be helpful it would be appreciated. (I'm using SyscallAll
> and going to investigate some of the syscalls SE mode ignores).
>
> I'm wondering if maybe it is calling join() multiple times that might be
> the problem? Though unsure why at this point.
>
> Thanks!
>
> Dan
>
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[gem5-users] Re: Implementing Cache Replacement Policies

2020-10-28 Thread Daniel Carvalho via gem5-users 
Hello,
A few years ago I have implemented a few PC-reliant RPs for fun, but did not 
merge them upstream because I did not have time to fully test them. One day 
they shall see the light of day, though :)

I don't remember what is required for the PC change in particular, but here are 
the changes that may be needed (I will add small sections of the commits for 
clarity). Remember that this implementation was created before Ruby started 
using the RPs too, so it may not work today:

=> Make RP:invalidate() not const (Usually these PC-reliant RPs use predictors, 
which must be updated on invalidations)

=> Use PacketPtr in *Tags::accessBlock()-    virtual CacheBlk* accessBlock(Addr 
addr, bool is_secure, Cycles ) = 0;
+    virtual CacheBlk* accessBlock(const PacketPtr pkt, Cycles ) = 0;
=> Make touch() and reset() use packets virtual void touch(const 
std::shared_ptr&
-    replacement_data) const = 0;
+    replacement_data, const PacketPtr pkt)
+    {
+    touch(replacement_data);
+    }
+    virtual void touch(const std::shared_ptr&
+    replacement_data) const = 0;
  virtual void reset(const std::shared_ptr&-   
 replacement_data) const = 0;
+    replacement_data, const PacketPtr pkt)
+    {
+    reset(replacement_data);
+    }
+    virtual void reset(const std::shared_ptr&
+    replacement_data) const = 0;

=> Create your RP that overrides the newly created touch() and reset() to use 
the packets' info

Regarding your questions:1) In src/mem/packet.hh
2) The Classic cache is inside src/mem/cache/
Regards,Daniel
   Em quarta-feira, 28 de outubro de 2020 17:30:49 GMT+1, Abhishek Singh via 
gem5-users  escreveu:  
 
 Hi,
I think you should check already implemented policies in 
src/mem/cache/replacement_policies and then design yours taking that as an 
template/example.
In order to get information which you mentioned, you might have to change/add 
arguments to accessBlock, findBlock, insertBlock, etc function in 
base_set_assoc.
The information you are looking can be found in pkt class.
For simplicity you can also use fa_lru as template and change things in it to 
implement replacement policies. 
On Wed, Oct 28, 2020 at 11:46 AM Chongzhi Zhao via gem5-users 
 wrote:

Hi,I'm trying to evaluate a cache replacement policy with classic memory in SE 
mode. A few questions:   
   - The policy requires PC, address, and access type (demand 
read/writeback/prefetch) to be made visible. However, I don't see these exposed 
to the replacement policies. Where may I find them?
   - The member functions are referenced in classes CacheMemory, SectorTags, 
and BaseSetAssoc. Which one of them would be relevant to classic memory?
Cheers,
Chongzhi Zhao___
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[gem5-users] Re: How to use the new libm5.a

2020-10-28 Thread Wenqi Yin via gem5-users 
Hi Hoa, Gabe, 

Thanks for your help! But just want to confirm this: what I did in the past is 
calling map_m5_mem() in my code first and then call specific m5 functions, and 
it seems to work. The guest in running on KvmCPU. 

When I am trying to do the same thing with the new libm5.a, it gave an 
exception (Illegal Instruction), however I haven’t looked into the error 
carefully yet, it may just because for some reason the lib is still trying to 
use the magic instruction interface. But before I proceed any further, just 
want to make sure I was using the correct approach to do this. 

Best, 
Wenqi

> On Oct 26, 2020, at 23:30, Gabe Black via gem5-users  
> wrote:
> 
> Hi Wenqi. The updated libm5.a should be used in basically the same way as the 
> old version. Just link against the library, include the header file, and call 
> into the op you want using the normal function call syntax.
> 
> Hoa, the documentation you've linked to is a little out of date. How can it 
> be updated?
> 
> Gabe
> 
> On Sun, Oct 25, 2020 at 9:31 PM Hoa Nguyen via gem5-users 
> mailto:gem5-users@gem5.org>> wrote:
> Hi Wenqi,
> 
> We have some documentation about the new m5 utility here:
> https://www.gem5.org/documentation/general_docs/m5ops/ 
> 
> 
> The following link is an example of annotating PARSEC:
> https://github.com/darchr/parsec-benchmark/commits/gem5-20-annotations 
> 
> 
> Regards,
> Hoa Nguyen
> 
> On 10/25/20, wqyin--- via gem5-users  > wrote:
> > Hello all,
> >
> > I noticed the util/m5 has big changes since this
> > commit:26454e8072e607d54ac67c42b33355d7c94d6d60 around Apr 27. I am
> > wondering how should I use this new interface/implementation to call
> > m5ops in my program? Shall I also instantiate a default CallType and
> > then use it to obtain the dispatch table and finally pass it to
> > Command::run? Also is there any examples which use the new
> > implementation to annotate any benchmarks running inside gem5? Thanks
> >
> > Best,
> >
> > Wenqi
> >
> >
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[gem5-users] Re: How to use the new libm5.a

2020-10-28 Thread Wenqi Yin via gem5-users 
Hi Ciro, 

I don’t think things changed and your method should still work. However, my use 
case is a bit different as I need to call m5 ops when my guest is running on 
KVM cpu. My understanding is in virtual environment the magic Inst won’t work 
(I tested and it gave me Illegal Instruction exception) and I need to use the 
memory map interface, not sure if I understood correctly. But thanks for the 
suggestion, your way is definitely easier when it’s not in kvm. 

Best, 
Wenqi

> On Oct 27, 2020, at 07:34, Ciro Santilli via gem5-users  
> wrote:
> 
> Hi Wenqi,
> 
> Have you tried: 
> https://stackoverflow.com/questions/62757008/how-to-use-m5-in-gem5-20/62759204#62759204
>  
> 
>  or has something changed since then too? Seems to work on develop just now.
> From: wqyin--- via gem5-users 
> Sent: Sunday, October 25, 2020 7:36 PM
> To: gem5-users@gem5.org 
> Cc: wq...@utexas.edu 
> Subject: [gem5-users] How to use the new libm5.a
>  
> Hello all, 
> I noticed the util/m5 has big changes since this commit: 
> 26454e8072e607d54ac67c42b33355d7c94d6d60 around Apr 27. I am wondering how 
> should I use this new interface/implementation to call m5ops in my program? 
> Shall I also instantiate a default CallType and then use it to obtain the 
> dispatch table and finally pass it to Command::run? Also is there any 
> examples which use the new implementation to annotate any benchmarks running 
> inside gem5? Thanks
> Best,
> Wenqi
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[gem5-users] Re: Configure multi-bank cache in ruby ​mode with MESI coherence protocol

2020-10-28 Thread zhen bang via gem5-users 
Hello Jason:
I would use the resource stalls to model banking, I have read 
src/mem/ruby/structures/Rubycache.py and src/mem/ruby/structures/BankedArray.cc
(1)  I have seen 
dataArrayBanks = Param.Int(1, "Number of banks for the data array")
tagArrayBanks = Param.Int(1, "Number of banks for the tag array")

If I want to configure multiple banks, can I directly modify these parameters?

(2) To extend the BankedCache implementation to model arbitrary address
interleaving, which files or functions should I modify?
Should I modify the following function in 
src/mem/ruby/structures/BankedArray.cc?
unsigned int
BankedArray::mapIndexToBank(int64_t idx)
{
if (banks == 1) {
return 0;
}
return idx % banks;
}

Looking forward to your reply.
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[gem5-users] Re: Implementing Cache Replacement Policies

2020-10-28 Thread Abhishek Singh via gem5-users 
Hi,

I think you should check already implemented policies in
src/mem/cache/replacement_policies and then design yours taking that as an
template/example.

In order to get information which you mentioned, you might have to
change/add arguments to accessBlock, findBlock, insertBlock, etc function
in base_set_assoc.

The information you are looking can be found in pkt class.

For simplicity you can also use fa_lru as template and change things in it
to implement replacement policies.

On Wed, Oct 28, 2020 at 11:46 AM Chongzhi Zhao via gem5-users <
gem5-users@gem5.org> wrote:

> Hi,
> I'm trying to evaluate a cache replacement policy with classic memory in
> SE mode. A few questions:
>
>1. The policy requires PC, address, and access type (demand
>read/writeback/prefetch) to be made visible. However, I don't see these
>exposed to the replacement policies. Where may I find them?
>2. The member functions are referenced in classes CacheMemory,
>SectorTags, and BaseSetAssoc. Which one of them would be relevant to
>classic memory?
>
> Cheers,
>
> *Chongzhi Zhao*
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-- 
Best Regards,
Abhishek
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[gem5-users] Implementing Cache Replacement Policies

2020-10-28 Thread Chongzhi Zhao via gem5-users 
Hi,
I'm trying to evaluate a cache replacement policy with classic memory in SE
mode. A few questions:

   1. The policy requires PC, address, and access type (demand
   read/writeback/prefetch) to be made visible. However, I don't see these
   exposed to the replacement policies. Where may I find them?
   2. The member functions are referenced in classes CacheMemory,
   SectorTags, and BaseSetAssoc. Which one of them would be relevant to
   classic memory?

Cheers,

*Chongzhi Zhao*
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[gem5-users] Re: Multi-level TLB is implemented in performance

2020-10-28 Thread Jason Lowe-Power via gem5-users 
Yes, this is possible, and I believe it's already implemented for Arm.

The best place to start is src/arch//tlb.cc

Cheers,
Jason

On Wed, Oct 28, 2020 at 1:27 AM Laney Laney via gem5-users <
gem5-users@gem5.org> wrote:

> Hi,all. I would like to know if it is possible to implement multi-level
> TLB on gem5 performance by modeling the latency of TLB. If so, which files
> or functions should I start with?
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[gem5-users] Multi-level TLB is implemented in performance

2020-10-28 Thread Laney Laney via gem5-users 
Hi,all. I would like to know if it is possible to implement multi-level TLB on 
gem5 performance by modeling the latency of TLB. If so, which files or 
functions should I start with?
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