[gem5-users] how gem5 loads binaries on SE mode?

Hello, everyone. I'm interested in memory encryption. I am interested in memory encryption, and I came across the problem of memory initialization. I would like to encrypt the binary in 128 bit units when it is loaded into the memory. Is there any document on how gem5 loads binaries on SE mode?

[gem5-users] Guest Binaries for X86

Hi, I noticed that the gem5 website only has guest binaries for ARM to run in full system mode, which are up to date and work well. I wonder if it is possible to have Full System guest Binaries for X86 and the other architectures. Best James ___

[gem5-users] ARM Microop vs Macroop

Hello Everyone, I hope you are all doing well! I am trying to implement a store instruction in ARM that has Post-index, Pre-index, and Signed-offset versions, and I'm using a normal store (i.e., STRX64) as a model to start, but I am running into some confusion with regard to which versions

[gem5-users] Re: Variable Meanings in ISA files

Thank you for the help, it's really appreciated! JZ ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s

[gem5-users] Re: Run Timed Simulation (Stop After Certain Time)

You can call cpu.scheduleInstStop(, , ) So, you can set an initial instruction limit which will exit from the simulate() call. Then, you can reset the stats and set a new instruction limit with scheduleInstStop. Then, call simulate() again. When this second simulate returns you can dump the

[gem5-users] Questions about simulating ARM SVE with gem5

Hi guys, I am new to the gem5 simulator. I have a few questions about simulating ARM SVE using gem5: 1. Which cpu model should I use? DerivO3CPU, MinorCPU, O3CPU, HPI? Or another cpu model? 2. How do I set the sve vector length? 3. Which simulation mode should I use if I want to run some large

[gem5-users] Re: Read Clean Request Packets

Hi Aritra, When a cache access misses, the cache in turns issues a request to next level cache or memory to request the line. Depending on whether the line needs to be read or written and other heuristics and policies, the cache will require from the line it gets back to have certain

[gem5-users] Read Clean Request Packets

Hi all, I am observing a lot of *ReadCleanReq* packets in the classic cache of gem5. Could anyone tell me what is the function/significance of these packets? Thanks and regards, Aritra Bagchi Research Scholar, Department of Computer Science and Engineering, Indian Institute of Technology Delhi,