[gem5-users] Re: riscv-ubuntu 20.04 FS mode

I use the following configuration: $GEM5/build/RISCV/gem5.fast -d $GEM5/node0 $GEM5/configs/example/gem5_library/riscv-ubuntu-run.py To be noticed that I have changed the riscv-ubuntu-run.py in order to use your new image as follows: ... image = CustomDiskImageResource( local_path =

[gem5-users] Re: riscv-ubuntu 20.04 FS mode

Dear Boddy, Thank you for the image and instructions! However, when I try to simulate the image through gem5, after 3 hours the gem5 simulation is automatically killed (after the following terminal output) . [ OK ] Started Unattended Upgrades Shutdown. [ OK ] Started LSB:

[gem5-users] Re: “fatal: Unable to find destination for [0x10020000 : 0x10020000] on system.iobus”, when adding new BasicPioDevice device.

That’s great! FYI, overriding the getAddrRanges is not strictly needed if the BasicPioDevice is correctly initialised. That basically means initialising pioAddr and pioSize member variables: https://github.com/gem5/gem5/blob/stable/src/dev/io_device.cc#L81 I am telling you this as while you

[gem5-users] Re: gem5 : X86 + GCN3 (gfx801) + test_fwd_lrn

Hi Matt P, When I tried the --reg-alloc-policy=dynamic a few runs did not improve and in fact got worse. For now, I will not use this option. Maybe the driver is not optimizing for this release. I did update my runs to use --gpu-to-dir-latency 100 (instead of 120) --TCC_latency 12 (instead of

[gem5-users] Re: “fatal: Unable to find destination for [0x10020000 : 0x10020000] on system.iobus”, when adding new BasicPioDevice device.

Hi Giacomo, Thanks again for the suggestion. I was able to solve the issue -- it turns out I forgot to implement getAddrRanges! For the record (and in case someone in the future runs into the same issue), I had to add the following in cus_device.hh under the class definition:

[gem5-users] Re: Running SPEChpc 2021 benchmarks with gem5

Hello Hoa, Thank you for your reply. It seems that I need to create an image file. I mistakenly assumed that the iso will work. Thus, I am looking into spec-2017 gem5-resources repo, and I’m trying to

[gem5-users] Re: “fatal: Unable to find destination for [0x10020000 : 0x10020000] on system.iobus”, when adding new BasicPioDevice device.

Yes apologies, I now realize your range was already covered in the existing _off_chip_ranges list I’d recommend you to debug with gdb what is returned by the CusDevice::getAddrRanges method. It gets called by the xbar and it effectively registers the device pio range in the interconnect map.

[gem5-users] Re: “fatal: Unable to find destination for [0x10020000 : 0x10020000] on system.iobus”, when adding new BasicPioDevice device.

Hi Giacomo, Thank you for the suggestion. I added the address range to the _off_chip_devices list as suggested, and confirmed the address range is present in the config.ini: [system.bridge] type=Bridge … ranges=201326592:268566527 268566528:268570624 268570625:536870912 788529152:2147483647

[gem5-users] Re: “fatal: Unable to find destination for [0x10020000 : 0x10020000] on system.iobus”, when adding new BasicPioDevice device.

Hi Joshua. You probably need to add the physical address range of your device to the _off_chip_ranges list [1]. This will be assigned to the membus->iobus bridge so that when the membus receives the cpu packet, it knows it must forward it to the io bridge Let me know if this works Kind

[gem5-users] “fatal: Unable to find destination for [0x10020000 : 0x10020000] on system.iobus”, when adding new BasicPioDevice device.

Hi all, I am trying to run an ARM full system simulation with a BasicPioDevice added onto the RealView Platform. I am interested in interfacing it via ioremap. The device is set up like so in src/dev/arm/RealView.py (with the necessary C++ header/implementation files): class

[gem5-users] Re: Read main memory directly in the timing model

Hi, I believe what you are trying to achieve is what is commonly called a "functional access". Though, I am not exactly sure about what is your intent when you say that you want to "bypass caches in order to maintain coherence" as it sounds contradictory to me. If you chose to mix regular and

[gem5-users] Re: Selecting and configuring a pre-fetcher

- Mail original - De: "Eliot Moss via gem5-users" À: "gem5 users mailing list" Cc: "Eliot Moss" Envoyé: Dimanche 20 Mars 2022 00:23:01 Objet: [gem5-users] Selecting and configuring a pre-fetcher Dear gem5-ers -- I've been running an x86 DerivO3CPU pretty much as it comes, and now

[gem5-users] Issue with strange virtual address access

Hi all, I used the following command to view the virtual address translation process. build/X86/gem5.opt --debug-flags=Exec,TLB --debug-file=/home/liyan/Desktop/gem5/m5out/debug.txt configs/example/se.py --cpu-type=TimingSimpleCPU --caches --l2cache --mem-type=DRAMsim3 --num-cpus=1 -c

[gem5-users] ARM model - load instruction reads non-zero data from an address which was not written out prior (as per traces)

Hi , I was going through the load and store instructions from the GEM5 traces and i could see that at some instances, the load instruction reads from an address which was not written with valid data before. How is it reading non-zero data from an address which was not written to? (From the GEM5