hoose only one of them. Additionally, the command
> line options for cache sizes may or may not work with Ruby depending on the
> coherence protocol.
>
> Cheers,
> Jason
>
> On Tue, Jan 24, 2017 at 5:01 AM SHARJEEL KHILJI <
> sharjeelsaeedkhi...@gmail.com> wrot
alled from to find what dir_cntrls
> is. IIRC, it's created in the protocol-specific python files.
>
> Cheers,
> Jason
>
> On Sat, Feb 4, 2017 at 6:06 AM SHARJEEL KHILJI <
> sharjeelsaeedkhi...@gmail.com> wrote:
>
>> Hi,
>> Thanks for your reply that helped
Sharjeel Khilji
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topologies (e.g., Pt2Pt or crossbar) and using only a single directory.
>
> This could also be a problem with the memory ranges. Ruby only supports a
> single range with no gaps. I don't know what the ARM systems use.
>
> Jason
>
> On Tue, Feb 21, 2017 at 3:54 AM SHARJEEL KHILJI <
Hi,
I have encountered following problem while I was booting linux on armv7 noc.
./build/ARM/gem5.fast configs/example/fs.py
--machine-type=VExpress_GEM5_V1 --kernel
/home/khilji/gem5/m5/system/binaries/vmlinux --disk-image
/home/khilji/gem5/m5/system/disks/linux-aarch32-ael.img --dtb-filename
> Hi Sharjeel,
>
> How do you do the compilation? I can get dtb files by typing "make" under
> $M5_ROOT/system/arm/dt
>
> -Mohammad
>
> On Fri, Feb 17, 2017 at 8:42 AM, SHARJEEL KHILJI <
> sharjeelsaeedkhi...@gmail.com> wrote:
>
>> Hi,
>> Anyone h
Hi,
When I run the following build command I get the simulation limit reached
exit().
./build/ARM/gem5.fast configs/example/fs.py
--machine-type=VExpress_GEM5_V1 --kernel
/home/khilji/gem5/m5/system/binaries/vmlinux --disk-image
/home/khilji/gem5/m5/system/disks/linux-aarch32-ael.img
Hi,
When I run the following build command I get the simulation limit reached
exit().
./build/ARM/gem5.fast configs/example/fs.py --machine-type=VExpress_GEM5_V1
--kernel /home/khilji/gem5/m5/system/binaries/vmlinux --disk-image
/home/khilji/gem5/m5/system/disks/linux-aarch32-ael.img
tionally, the command
> line options for cache sizes may or may not work with Ruby depending on the
> coherence protocol.
>
> Cheers,
> Jason
>
> On Tue, Jan 24, 2017 at 5:01 AM SHARJEEL KHILJI <
> sharjeelsaeedkhi...@gmail.com> wrote:
>
>>
>> Hi, i am try
Hi,
sorry it was 512MB the mem-size = 512 MB in build commands.
best regards,
Sharjeel
On 11 February 2017 at 15:33, SHARJEEL KHILJI <sharjeelsaeedkhi...@gmail.com
> wrote:
> HI,
> Thanks for your help, I have tried to figure out where is that
> uninitialized stat. Actuall
we can try to
> work out what stat isn't being initialized.
>
> Cheers,
> Jason
>
> On Sun, Feb 5, 2017 at 8:55 AM SHARJEEL KHILJI <
> sharjeelsaeedkhi...@gmail.com> wrote:
>
>> Hi,
>> Thanks for helping me with the directory and memory controller connect
at 15:48, SHARJEEL KHILJI <sharjeelsaeedkhi...@gmail.com
> wrote:
> Hi,
> sorry it was 512MB the mem-size = 512 MB in build commands.
>
> best regards,
>
> Sharjeel
>
>
> On 11 February 2017 at 15:33, SHARJEEL KHILJI <
> sharjeelsaeedkhi...@gmail.com>
anything in m5out/*terminal*? I would bet that something is going
> wrong early in the boot process and gem5 is not booting the OS correctly.
>
> Jason
>
> On Mon, Feb 13, 2017 at 10:51 AM SHARJEEL KHILJI <
> sharjeelsaeedkhi...@gmail.com> wrote:
>
>> Hi
>>
Hi,
here is the debug simulation
command line: ./build/ARM/gem5.debug --debug-flags=Exec,ExecTicks
configs/example/fs.py --maxinsts=10 --machine-type=VExpress_GEM5_V1
--kernel /home/khilji/gem5/m5/system/binaries/vmlinux-aarch32 --disk-image
/home/khilji/gem5/m5/system/disks/linux-aarch32-ael.img
Hi,
I want to compile the armv7.dts file in /system/arm/dt in to .dtb file.
I get Error: :33.1-9 syntax error
FATAL ERROR: Unable to parse input tree
when i compile with dtc -Odtb -Idts < armv7.dts > armv7.dtb
Any suggestions for this I want to compile armv7.dts file for the
VExpress_GEM5_V1
t;
> This could also be a problem with the memory ranges. Ruby only supports a
> single range with no gaps. I don't know what the ARM systems use.
>
> Jason
>
> On Tue, Feb 21, 2017 at 3:54 AM SHARJEEL KHILJI <
> sharjeelsaeedkhi...@gmail.com> wrote:
>
>> Hi,
>
ovided by on the gem5-arm-ruby gite.lirmm.fr
page. *https://gite.lirmm.fr/butko/gem5-arm-ruby/tree/ruby
<https://gite.lirmm.fr/butko/gem5-arm-ruby/tree/ruby> *
Kindly, if you can help me in this issue. I will be highly obliged.
best regards,
Muhammad Sha
scons: *** [build/ARM/dev/arm/generic_timer.fo] Error 1
scons: building terminated because of errors.
Kindly, if you can help me in the regard.
best regards,
Muhammad Sharjeel Khilji
On 14 December 2016 at 20:50, Andreas Sandberg <andreas.sandb...@arm.com>
wrote:
> Hi Pierre and Sharje
Hi,
While booting Linux on ARM NOC I get following error.
./build/ARM/gem5.debug configs/example/fs.py --cacheline_size=64
--machine-type=VExpress_GEM5_V1 --kernel
/home/khilji/gem5/m5/system/binaries/vmlinux-aarch32 --disk-image
/home/khilji/gem5/m5/system/disks/arm-ubuntu-natty-headless.img
Hi,
I want to simulate the a mesh ARM NOC in FS mode with four nodes (four
directories and four memory ranges each on one node). These memory ranges
registered with four abstract memory objects for four node are as follows
0x8000 - 0x8fff
0x9000 - 0x9fff
0xa000 - 0xafff
*very simple* with 2
> cores. For instance, use MI_example and the Pt2Pt topology with the simple
> network model. From here you'll be able to track down the problems easier.
> Once you have that working, you can slowly introduce other code and solve
> the problems that come w
Hi,
I am running ARM NoC garnet 2.0 Mesh. I want to know that during execution
of a program which link in the Mesh gets more busy? Is there any stat that
can report this. There is already a stat "m_total_int_link_utilization"
which reports the link utilization of all the internal links. Is there a
use fs/se.py. These
> scripts were originally meant as small examples, but have grown to be
> complicated, confusing, and very difficult to extend to non-standard
> applications.
>
> Jason
>
> On Tue, Jul 4, 2017 at 5:03 AM SHARJEEL KHILJI <
> sharjeelsaeedkhi...@gmail.com&
Hi,
I want to know how can I make Splash2 know about roi_begin_end() functions.
I have included m5op.h, m5ops.h any kernel prog e.g., FFT and have marked
roi annotations.
I want to know that I have to provide m5op_arm.S file to the compiler.
I want to know that how that can be done in the makefile
Hi,
I want to compile the Splash2 benchmark with pthread implementation of
PARMACS macros for ARM ISA. I have also use the m5_roi_begin/end
annotations in the splash2 kernels. Can any one highlight how this can be
achieved?
I mean how make file can be changed both in pthreads library and in
begin/end m5
> magic instructions. You then modify the Python config script to dump stats
> and restart simulation at the end of each ROI.
>
> Jason
>
> On Tue, Jun 6, 2017 at 3:15 AM SHARJEEL KHILJI <
> sharjeelsaeedkhi...@gmail.com> wrote:
>
>> Hi,
>>
Hi,
I want to make a system based upon ARM big little configuration and I want
to use fs_bigLITTLE.py configuration script. I want to know how can I
generate armv8_gem5_v1_big_little_2_2.dtb file ? Or will
armv7_gem5_v1_4cpu.dtb be enough for this since both Cortex A7 and Cortex
A15 use the armv7a
MESI_Two_Level protocol.
>
>
> Nikos
> --
> *From:* gem5-users <gem5-users-boun...@gem5.org> on behalf of SHARJEEL
> KHILJI <sharjeelsaeedkhi...@gmail.com>
> *Sent:* 12 June 2017 07:56:51
> *To:* gem5 users mailing list
> *Subject:* [gem5-users] Inva
e fields which
> are then used to route the response. It shouldn't be too hard to add
> something similar for the MESI_Two_Level protocol.
>
>
> Nikos
> --
> *From:* gem5-users <gem5-users-boun...@gem5.org> on behalf of SHARJEEL
> KHILJI <
MESI_Two_Level protocol.
>
>
> Nikos
> --
> *From:* gem5-users <gem5-users-boun...@gem5.org> on behalf of SHARJEEL
> KHILJI <sharjeelsaeedkhi...@gmail.com>
> *Sent:* 12 June 2017 07:56:51
> *To:* gem5 users mailing list
> *Subject:* [ge
Hi,
I am running following system.
./build/ARM/gem5.fast configs/example/fs.py --l1d_size=32kB
--l1i_size=32kB --num-l2caches 4 --l2_size=1MB --cacheline_size=64
--machine-type=VExpress_GEM5_V1 --kernel
/home/khilji/gem5/m5/system/binaries/vmlinux-aarch32 --disk-image
Hi,
I am running splash2 on ARM NoC and I get following timing information on
output while running radix kernel.
TIMING INFORMATION
Start time: 2180011630
Initialization finish time: 2180013105
Overall finish time :
Hi,
I want to dump stats at the end of every kernel that I run from the splash2
benchmark. How to dump stats from each kernel from splash2 at the end of
execution of that particular kernel program and then again dump stats for
the next program without exiting the simulation.
any suggestions ?
Hi,
I am running the following system,
scons build/ARM/gem5.debug PROTOCOL=MESI_Two_Level
./build/ARM/gem5.debug --debug-flags ProtocolTrace configs/example/fs.py
--l1d_size=32kB --l1i_size=32kB --num-l2caches 4 --l2_size=1MB
--cacheline_size=64 --machine-type=VExpress_GEM5_V1 --kernel
Hi,
I am getting following issue when I use ex5_big with ruby memory system.
warning : Address 0 is outside of physical memory, stopping fetch
which results in simulation limit reached. Can anyone tell me that does
ex5_big really works with ruby memory system.
best regards,
Sharjeel
Hi,
I am trying to make a heterogeneous NoC in ARM. I am using Ex5BigCluster
and Ex5LittleCluster from fs_bigLITTLE.py. When I connect the big and
little cluster cpus to LInux ARM System I get the following error.
AttributeError: object 'LinuxArmSystem' has no attribute 'numCpus'
(C++ object
t; --
> *From:* gem5-users <gem5-users-boun...@gem5.org> on behalf of SHARJEEL
> KHILJI <sharjeelsaeedkhi...@gmail.com>
> *Sent:* 24 August 2017 17:06:00
> *To:* gem5 users mailing list
> *Subject:* [gem5-users] ex5_big issues with ruby memory s
--
> *From:* gem5-users <gem5-users-boun...@gem5.org> on behalf of SHARJEEL
> KHILJI <sharjeelsaeedkhi...@gmail.com>
> *Sent:* 25 August 2017 13:41:32
> *To:* gem5 users mailing list
> *Subject:* Re: [gem5-users] ex5_big issues with ruby memory system
>
> Hi,
> I
Hello
yes if you are using ruby memory system you can select the type of protocol
(e.g., MESI Two level, MOESI CMP Directory etc).
regards,
Muhammad
On 11 October 2017 at 10:51, Muhammad Avais wrote:
> Hi,
> Does GEM5 follows any specific cache coherence protocol?
>
Hi,
I have simulated ARM NoC (4 and 8 cores) with 4 and 8GB with
VEXPRESS_GEM5_V1 platform. You can try with this platform.
regards,
Sharjeel
On 1 December 2017 at 23:55, David Kim wrote:
> Hello,
>
> I am going to simulate a system with large memory capacity.
>
> As
Hi,
I can not search the source on gem5 website. It replies with service not
available. Will this service be available again?
regards,
Sharjeel
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gem5-users@gem5.org
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Hi,
I am facing some issue while using DerivO3CPU with ARM ISA with ruby memory
system. It does not work and gives following error.
warn: Address 0 is outside of physical memory, stopping fetch
simulate() limit reached
I am using MESI Two Level protocol. DerivO3CPU works fine with classic
Hi,
I am facing some issue while using DerivO3CPU with ARM ISA with ruby memory
system. It does not work and gives following error.
warn: Address 0 is outside of physical memory, stopping fetch
simulate() limit reached
I am using MESI Two Level protocol. DerivO3CPU works fine with classic
memory in your configuration?
>
> Would you please briefly explain your system configuration?
>
>
> On Fri, Dec 1, 2017 at 1:34 PM, SHARJEEL KHILJI <
> sharjeelsaeedkhi...@gmail.com> wrote:
>
>> Hi,
>>
>> I have simulated ARM NoC (4 and 8 cores) wi
Hi,
I want to know that how can I get the information (that how many flits are
injected in to the network by a particular node) to the operating system. I
am running the following system,
./build/ARM/gem5.fast configs/example/fs.py --l1d_size=256kB
--l1i_size=256kB --num-l2caches 16
Dear all,
I am having following error while using the Garnet 2.0 network.
build/ARM/mem/ruby/network/MessageBuffer.cc:220: Tick
MessageBuffer::dequeue(Tick, bool): Assertion `isReady(current_time)'
failed.
and core dumped.
I am using following system
./build/ARM/gem5.fast
gt; seeing?
>
> Jason
>
> On Mon, Feb 12, 2018 at 12:33 PM SHARJEEL KHILJI <
> sharjeelsaeedkhi...@gmail.com> wrote:
>
>> Hi Jason,
>>
>> Your website Learning gem5 is not working. I need to use this for
>> debugging MESI Two Level protocol. Kindly, if y
Hi Jason,
Last email was incomplete sorry for that.
I am running following system,
./build/ARM/gem5.debug --debug-flags ProtocolTrace configs/example/fs.py
--l1d_size=32kB --l1i_size=32kB --num-l2caches 4 --l2_size=1MB
--cacheline_size=64 --machine-type=VExpress_GEM5_V1 --kernel
Hi Jason,
I am running following system,
./build/ARM/gem5.debug --debug-flags ProtocolTrace configs/example/fs.py
--l1d_size=32kB --l1i_size=32kB --num-l2caches 4 --l2_size=1MB
--cacheline_size=64 --machine-type=VExpress_GEM5_V1 --kernel
/home/khilji/gem5/m5/system/binaries/vmlinux-aarch32
Hi Jason,
Last email was incomplete sorry for that.
I am running following system,
./build/ARM/gem5.debug --debug-flags ProtocolTrace configs/example/fs.py
--l1d_size=32kB --l1i_size=32kB --num-l2caches 4 --l2_size=1MB
--cacheline_size=64 --machine-type=VExpress_GEM5_V1 --kernel
Dear all,
I am having following error while using the Garnet 2.0 network.
build/ARM/mem/ruby/network/MessageBuffer.cc:220: Tick
MessageBuffer::dequeue(Tick, bool): Assertion `isReady(current_time)'
failed.
and core dumped.
I am using following system
./build/ARM/gem5.fast
is deadlocking.
>
> Other than that, I can't help much.
>
> Good luck finding the problem!
>
> Jason
>
>
>
> On Tue, Feb 13, 2018 at 7:24 AM SHARJEEL KHILJI <
> sharjeelsaeedkhi...@gmail.com> wrote:
>
>>
>> Hi Jason,
>>
>> Last email
Hi,
I am facing some issue while using DerivO3CPU with ARM ISA with ruby memory
system. It does not work and gives following error.
warn: Address 0 is outside of physical memory, stopping fetch
simulate() limit reached
I am using MESI Two Level protocol but the same error appears with other
Hi
You can try it with MESI TWO LEVEL this protocol has no issues with ARM
Ruby
Cheers
Muhammad
On Mar 9, 2018 8:50 PM, "Sahana Prasad" wrote:
> Hello,
>
> I am trying to get the garnet system up on ARM in fs mode with the
> following :
>
> scons
Hello,
SIr, I want to run 16 core ARM big LITTLE NoC Mesh_XY with one ex5_big core
and 15 ex5_small cores. The build statement for the NoC is as follows.
./build/ARM/gem5.fast configs/example/fs_het.py --l1d_size=128kB
--l1i_size=128kB --num-l2caches 16 --num-bigl2caches 1
Hi,
I am using binaries that you have uploaded in the following system.
./build/ARM/gem5.fast configs/example/fs.py --l1d_size=64kB
--l1i_size=64kB --num-l2caches 16 --l2_size=64MB --cacheline_size=64
--machine-type=VExpress_GEM5_V1 --kernel
Hi to all in this discussion,
I wanted to add some points to the discussion above regarding ARM+ RUBY. I
have been working with ARM +RUBY and I have simulated 2x2/ 4x4 Mesh_XY NoC
with MESI_Two_Level protocol. This protocol works fine with ARM in full
system mode. But originally MESI_Two_Level
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