[gem5-users] Re: Expose C++ enum in SLICC

Hi Gabriel, Thanks for the detailed information. My enum is small, so I think this will work just fine. Regards, Sampad On Mon, Nov 8, 2021 at 6:43 AM Gabriel Busnot via gem5-users < gem5-users@gem5.org> wrote: > Hi Sampad, > > I don't think that you can import C++ enums in SLICC in a general

[gem5-users] Expose C++ enum in SLICC

Hi All, Is there a way to expose an enum defined outside SLICC to be used within SLICC ? An example of my use case: *some_src.hh:* *-* enum MyEnum { A, B, C}; class MyClass{ void someFunc( MyEnum) {} } ... *some_slicc.sm :* *---*

[gem5-users] Duplicate MessageBuffer creation in GPU_VIPER.py

Hi All, The dir_cntrl.requestToMemory is initialized twice in GPU_VIPER.py. Could this potentially lead to two MessageBuffers being added or the previous one will just be overwritten ? Is this correct functionality?

[gem5-users] Re: MOESI_AMD_Base-CorePair.sm and MOESI_AMD_Base-dir.sm Correctness Check

t; I am not sure I understand completely what you're getting at, but it >>> appears the allocation of the TBE entry does store the data: >>> https://gem5.googlesource.com/public/gem5/+/refs/heads/develop/src/mem/ruby/protocol/MOESI_AMD_Base-dir.sm#878 >>> >>> Matt &

[gem5-users] MOESI_AMD_Base-CorePair.sm and MOESI_AMD_Base-dir.sm Correctness Check

Hello All, I was looking at the MOESI_AMD_Base-CorePair.sm and MOESI_AMD_Base-dir.sm and am not quite sure if the following sequence of events are correct or not. Can you please verify? / At CorePair -> invokes action "vd_victim", which sends a data block with outgoing

[gem5-users] Re: Pseudo Instruction - m5_reset_stats() - Body Modification

t;> >>> There are a large number of steps between when the guest code calls >>> m5_reset_stats and when the above function executes, but this should help >>> you start hacking :). >>> >>> Cheers, >>> Jason >>> >>> On Sat, O

[gem5-users] Re: Pseudo Instruction - m5_reset_stats() - Body Modification

_inst.cc#303 > > There are a large number of steps between when the guest code calls > m5_reset_stats and when the above function executes, but this should help > you start hacking :). > > Cheers, > Jason > > On Sat, Oct 2, 2021 at 4:05 AM Sampad Mohapatra via gem5-users <

[gem5-users] Re: GCN3 - Polybench GPU - SPEC 17 - Errors

gem5-resources ( > resources.gem5.org/) to allow others to also use them! > > Thanks, > Matt > > On Sat, Oct 9, 2021 at 9:47 AM Sampad Mohapatra via gem5-users < > gem5-users@gem5.org> wrote: > >> Hi All, >> >> I am running gem5 v21.0.0.0, rocm v1.6

[gem5-users] GCN3 - Polybench GPU - SPEC 17 - Errors

Hi All, I am running gem5 v21.0.0.0, rocm v1.6.x (built from source). The simulations run one host CPU (its pair runs a tiny binary and ends exec quickly) to launch GPU benchmark (hipified Polybench GPU) and one CPU of a separate core-pair(its 2nd core runs a lightweight binary and ends exec

[gem5-users] Pseudo Instruction - m5_reset_stats() - Body Modification

Hi All, I need to set a bool variable in src/cpu/simple/base.(hh|cc) to be true when m5_reset_stats() is *explicitly *called from some binary executing on gem5. Using this bool and instruction count, I want to exit the simulation. How can I modify the body (hack) of m5_reset_stats() to call

[gem5-users] Re: Out of Memory while running GPU Benchmark

e the size of the memory. > > Best, > Muhammet > > Sampad Mohapatra via gem5-users , 14 Eyl 2020 Pzt, > 21:49 tarihinde şunu yazdı: > >> Hi All, >> >> I am running 2DConvolution (polybench-gpu) and leela (SPEC 17) using the >> AMD GCN3 model on a res

[gem5-users] Out of Memory while running GPU Benchmark

Hi All, I am running 2DConvolution (polybench-gpu) and leela (SPEC 17) using the AMD GCN3 model on a research cluster with around 4 TB of memory. But the simulation ended with the following message: fatal: Out of memory, please increase size of physical memory. Memory Usage: 30305260 KBytes I

[gem5-users] Re: AMD GCN3 - X86KvmCPU usage - Segfault encountered

-2DD7-40BB-A1B8-4E2AA1F9FDF2> On Mon, Sep 7, 2020 at 1:05 PM Matt Sinclair wrote: > Matt P (CC'd) will likely know better than me, but I don't believe > KVM/fast-forwarding works with GCN3 yet. > > Matt > > On Mon, Sep 7, 2020 at 9:36 AM Sampad Mohapatra via gem5-users <

[gem5-users] AMD GCN3 - X86KvmCPU usage - Segfault encountered

Hi All, I am using the staging branch GCN3. While using the KvmCPU to fast forward execution till my GPU kernel launches using m5_switch_cpu(), I am encountering a segfault at the following location: src/cpu/kvm/vm.cc:562 : long KvmVM::allocVCPUID() { return nextVCPUID++; } For some reason the

[gem5-users] Garnet - Query regarding Faux-Filesystem

Hi All, Why was the following piece of code added to Mesh_XY.py and not to Cluster.py ? # Register nodes with filesystem def registerTopology(self, options): for i in xrange(options.num_cpus): FileSystemConfig.register_node([i],

[gem5-users] Re: SLICC - Help modify MemoryMsg

To clarify, I have added a bool and setter and getter functions to message.hh|cc. And I was able to solve the problem by declaring the following in SLICC. structure(Message, external="yes") { void setFlag(bool); bool getFlag(); }

[gem5-users] SLICC - Help modify MemoryMsg

Hi All, I am trying to add a bool variable to MemoryMsg and set() and get() it in SLICC. But when I try to build gem5, I get the following errors. AttributeError: 'NoneType' object has no attribute 'methods': File "/i3c/hpcl/sum94/local/ROCM_SRC/gem5/SConstruct", line 1257:

[gem5-users] Re: AMD GCN3 - Virtual network type correctness in MOESI_AMD_Base-dir.sm

experts with Garnet can review and validate. > > Thanks, > Matt > > On Sun, Aug 30, 2020 at 10:37 PM Sampad Mohapatra via gem5-users < > gem5-users@gem5.org> wrote: > >> Hi Srikant, >> >> It is used to send both data and acks. >> For now I am c

[gem5-users] Re: AMD GCN3 - Virtual network type correctness in MOESI_AMD_Base-dir.sm

> > Thanks, > Matt > > On Sun, Aug 30, 2020 at 10:37 PM Sampad Mohapatra via gem5-users < > gem5-users@gem5.org> wrote: > >> Hi Srikant, >> >> It is used to send both data and acks. >> For now I am changing it to response type till a counter argu

[gem5-users] Re: AMD GCN3 - Virtual network type correctness in MOESI_AMD_Base-dir.sm

type they should be marked as a 'response' type. > > Thanks, > Srikant > > On Sun, Aug 30, 2020 at 6:49 PM Sampad Mohapatra via gem5-users < > gem5-users@gem5.org> wrote: > >> Hi All, >> >> The *vnet_type* of the MessageBuffer *responseToDMA* is

[gem5-users] AMD GCN3 - Virtual network type correctness in MOESI_AMD_Base-dir.sm

Hi All, The *vnet_type* of the MessageBuffer *responseToDMA* is set as *request* and the virtual network number is set as 3. MessageBuffer * responseToDMA, network="To", virtual_network="3", vnet_type="request"; But in other slicc files such as *GPU_VIPER_TCC.sm* the vnet_type of vn number 3 is

[gem5-users] AMD GCN3 - More virtual networks initialized than required

Hi All, I am using the staging branch. The Viper protocol sets the number of VN to be 11. In GPU_VIPER.py: ruby_system.network.number_of_virtual_networks = 11 But the actual number of VN used is 5. SQC, TCC (has an unused VN #5), TCP, Corepair, Dir all use 0,1,2,3 and 4. The generated stats

[gem5-users] Re: GCN3 - SLICC - GPU_VIPER-TCC.sm and GPU_TCP-TCP.sm Correctness

don't pass the data along to simplify things (i.e., > we don't send the data, but we do account for it). > > However, Alex and Brad (CC'd) know a lot more about the state of the > backing store than I do, so they should comment to confirm. > > Matt > > On Tue, Aug 25, 202

[gem5-users] GCN3 - SLICC - GPU_VIPER-TCC.sm and GPU_TCP-TCP.sm Correctness

Hello, In GPU_VIPER-TCC.sm and GPU_TCP-TCP.sm, in action *at_atomicThrough* present in both files, the out message Type is *CoherenceRequestType:Atomic* and the message size is *MessageSizeType:Data*, but there is *no data* being sent. Is this correct behaviour ? Either data is not being sent or

[gem5-users] How are SLICC in_port and out_port connected ?

Hello, I am not clear as to how an out_port (let's say from cache) and an in_port (to directory) are connected. For example in learning gem5 book: MSI-Cache.sm: MessageBuffer * requestToDir, network="To", virtual_network="0", vnet_type="request"; out_port(request_out, RequestMsg,

[gem5-users] Re: Missing L1 and L2 Hit stats/actions in MOESI AMD Base - CorePair.sm

isn't used, then why is it a part of the >>>>> Viper protocol ? >>>>> Does the L3 Cache not maintain any coherency ? >>>>> Is this the intended behaviour of the default configuration ? >>>>> >>>>> Thanks and Regards,

[gem5-users] Re: Missing L1 and L2 Hit stats/actions in MOESI AMD Base - CorePair.sm

gt; wrote: >>> >>>> Hi Sampad, >>>> >>>> I'm not aware of a patch for this. There was recently a patch to add >>>> similar support for the VIPER protocol: >>>> https://gem5-review.googlesource.com/c/public/gem5/+/30174. If t

[gem5-users] Re: Missing L1 and L2 Hit stats/actions in MOESI AMD Base - CorePair.sm

> Thanks, > Matt > > On Tue, Aug 4, 2020 at 4:53 PM Sampad Mohapatra via gem5-users < > gem5-users@gem5.org> wrote: > >> Hello All, >> >> MOESI AMD Base - CorePair state machine is missing the actions for L1 and >> L2 hit statistics. >> The st

[gem5-users] Re: AMD GCN3 - Can't use single CPU - fatal no spare thread context

n merged into develop or the >>> AMD staging branch yet (although like some of the other ROCm patches, it >>> would actually need to be placed elsewhere like gem5-resources, not >>> directly in the gem5 repo, since it doesn't affect gem5 code). >>>

[gem5-users] Re: AMD GCN3 - Can't use single CPU - fatal no spare thread context

other ROCm patches, it would actually need to be > placed elsewhere like gem5-resources, not directly in the gem5 repo, since > it doesn't affect gem5 code). > > Alternatively, you can just run with -n 2, as you've found already. It > should have very minimal impact on running the ap

[gem5-users] AMD GCN3 - Can't use single CPU - fatal no spare thread context

Hi All, Why does the GCN3 model require at least 2 CPUs ? Every time I use a single CPU, gem5 crashes with the following error: *fatal: clone: no spare thread context in system* In contrast, I was able to run the HSAIL model with a single CPU. Thank You, Sampad Mohapatra

[gem5-users] Missing L1 and L2 Hit stats/actions in MOESI AMD Base - CorePair.sm

Hello All, MOESI AMD Base - CorePair state machine is missing the actions for L1 and L2 hit statistics. The stats are present, but since no "action" is created nor used (actions to update misses are present for both L1 and L2), the stats stay at 0. I am not clear as to which state transitions

[gem5-users] AMD GCN3 - HSA Memory Mapping

Hi All, I have two queries related to apu_se.py. (1) In both AMD staging and public/develop, apu_se.py has two unused variables: hsapp_gpu_map_vaddr = 0x2 hsapp_gpu_map_size = 0x1000 Are they unnecessary or should they actually be used somewhere ? (2) The following is passed as

[gem5-users] Re: AMD GCN3 - HIP Compile m5_exit() issue

;> Sorry, using hipcc* to link them together. >>> >>> On Sat, Aug 1, 2020 at 2:15 PM Daniel Gerzhoy >>> wrote: >>> >>>> I would suggest compiling M5op with gcc or g++ with a -c flag and then >>>> using M5op to link them together. >>&g

[gem5-users] Re: AMD GCN3 - HIP Compile m5_exit() issue

PM Daniel Gerzhoy > wrote: > >> I would suggest compiling M5op with gcc or g++ with a -c flag and then >> using M5op to link them together. >> >> On Sat, Aug 1, 2020 at 2:13 PM Sampad Mohapatra via gem5-users < >> gem5-users@gem5.org> wrote: >> >&g

[gem5-users] AMD GCN3 - HIP Compile m5_exit() issue

Hello, While trying to compile polybench benchmarks with m5_exit(0) using the HIP compiler () I am getting a lot of errors (m5ops.h was included). Please give me some advice. *Compile Command:* /opt/rocm/hip/bin/hipcc --amdgpu-target=gfx801 -g -O2 2DConvolution.cpp -I/sam/gem5/include

[gem5-users] Re: AMD GCN3 - Garnet Support

k topology specified for garnet in gem5. > > Thanks, > Srikant > > On Tue, Jul 28, 2020 at 7:47 PM Sampad Mohapatra via gem5-users < > gem5-users@gem5.org> wrote: > >> Hi All, >> >> Does the GCN3 APU model support garnet network and topologies ?

[gem5-users] AMD GCN3 - Garnet Support

Hi All, Does the GCN3 APU model support garnet network and topologies ? Also, what is the hsaTopology ? Are garnet topologies and hsaTopology related in some way ? Thank you, Sampad Mohapatra ___ gem5-users mailing list -- gem5-users@gem5.org To