Re: [gem5-users] SPEC2017 on gem5 SE mode
Hmm, interesting. Can you please keep posting the info about your progress? On Fri, Dec 15, 2017 at 10:05 PM, Mohammad Khasawneh < mkhas...@binghamton.edu> wrote: > I’m running only 1 thread and 1 copy of each program. I'm going over them > individually and testing different compilation flags. As of now, just > reducing the optimization level from O3 to O2 seems to have worked on a > couple of them. > > > > Thank you, > > Mohammad > > > > > > *From: *Jasmin Jahic <jasmin.ja...@gmail.com> > *Sent: *Friday, December 15, 2017 4:00 PM > *To: *gem5 users mailing list <gem5-users@gem5.org> > *Subject: *Re: [gem5-users] SPEC2017 on gem5 SE mode > > > > Hello, > > > > do you run SPEC with 1 or more threads? > > > > Best regards, > > Jasmin > > > > On Fri, Dec 15, 2017 at 4:57 PM, Mohammad Khasawneh < > mkhas...@binghamton.edu> wrote: > > Hello, > > > > I’m trying to get SPEC2017 to run in SE mode (X86) as SPEC2006 did, so far > the only benchmark that ran to completion is 505.mcf_r with no > modifications to the basic config file. Here is what I did: > > > >1. Compiled benchmarks statically (although it seems this is no longer >a requirement on newer gem5 versions). >2. Made sure binaries execute natively on host. >3. Ran them through gem5 pretty much like I used to run SPEC2006. > > > > What I get: > > On many of them a common error I get is this: > > > > panic: Unrecognized/invalid instruction executed: > > > > { > > leg = 0x10, > > rex = 0, > > vex/xop = 0x5, > > op = { > > type = three byte 0f3a, > > op = 0x18, > > }, > > modRM = 0, > > sib = 0, > > immediate = 0, > > displacement = 0 > > dispSize = 0 > > } > > > > I’m assuming a change in the config file would force the compiler to > produce more sensible binaries, any ideas on where I should start digging > would be appreciated. > > > > Thank you, > > Mohammad > > > ___ > gem5-users mailing list > gem5-users@gem5.org > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > > > > > > ___ > gem5-users mailing list > gem5-users@gem5.org > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] SPEC2017 on gem5 SE mode
I’m running only 1 thread and 1 copy of each program. I'm going over them individually and testing different compilation flags. As of now, just reducing the optimization level from O3 to O2 seems to have worked on a couple of them. Thank you, Mohammad From: Jasmin Jahic Sent: Friday, December 15, 2017 4:00 PM To: gem5 users mailing list Subject: Re: [gem5-users] SPEC2017 on gem5 SE mode Hello, do you run SPEC with 1 or more threads? Best regards, Jasmin On Fri, Dec 15, 2017 at 4:57 PM, Mohammad Khasawneh <mkhas...@binghamton.edu> wrote: Hello, I’m trying to get SPEC2017 to run in SE mode (X86) as SPEC2006 did, so far the only benchmark that ran to completion is 505.mcf_r with no modifications to the basic config file. Here is what I did: 1. Compiled benchmarks statically (although it seems this is no longer a requirement on newer gem5 versions). 2. Made sure binaries execute natively on host. 3. Ran them through gem5 pretty much like I used to run SPEC2006. What I get: On many of them a common error I get is this: panic: Unrecognized/invalid instruction executed: { leg = 0x10, rex = 0, vex/xop = 0x5, op = { type = three byte 0f3a, op = 0x18, }, modRM = 0, sib = 0, immediate = 0, displacement = 0 dispSize = 0 } I’m assuming a change in the config file would force the compiler to produce more sensible binaries, any ideas on where I should start digging would be appreciated. Thank you, Mohammad ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] SPEC2017 on gem5 SE mode
Hello, do you run SPEC with 1 or more threads? Best regards, Jasmin On Fri, Dec 15, 2017 at 4:57 PM, Mohammad Khasawnehwrote: > Hello, > > > > I’m trying to get SPEC2017 to run in SE mode (X86) as SPEC2006 did, so far > the only benchmark that ran to completion is 505.mcf_r with no > modifications to the basic config file. Here is what I did: > > > >1. Compiled benchmarks statically (although it seems this is no longer >a requirement on newer gem5 versions). >2. Made sure binaries execute natively on host. >3. Ran them through gem5 pretty much like I used to run SPEC2006. > > > > What I get: > > On many of them a common error I get is this: > > > > panic: Unrecognized/invalid instruction executed: > > > > { > > leg = 0x10, > > rex = 0, > > vex/xop = 0x5, > > op = { > > type = three byte 0f3a, > > op = 0x18, > > }, > > modRM = 0, > > sib = 0, > > immediate = 0, > > displacement = 0 > > dispSize = 0 > > } > > > > I’m assuming a change in the config file would force the compiler to > produce more sensible binaries, any ideas on where I should start digging > would be appreciated. > > > > Thank you, > > Mohammad > > ___ > gem5-users mailing list > gem5-users@gem5.org > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users