[gem5-users] (no subject)

[DURAIRAJ J]

Hello everyone 
Is there any way to make a router to drop a packet while routing? 
___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

[gem5-users] (no subject)

[Hafizul Islam Reyad]

Hi,

I am new to gem5 and I was trying to run multiple benchmarks on gem5 to get
some results for my research. I face a issue that whenever I run multiple
gem5 simulations on one disk image, some of the gem5 process exits without
giving any results or errors.

For example, I have about 20 microbenchmarks and 3 gem5 configurations
(e.g. different cachesize/ memory size etc.). So when I start a benchmark
run, I use one disk image and one kernel to run all these simulations (20
microbenchmarks * 3 gem configs = 60 simulations). Out of these 60
simulations, some of gem process (about 10) stops without giving any error
or exit message. When I run the incomplete benchmarks again (using the same
command), they finish successfully.

My question is that if I share the same disk image and kernel across a lot
of simultaneous gem5 simulation, does this cause any issue? If not, what
might be the possible reason for this?

I ran my simulations in a bare-metal AWS server that had 72 threads and 512
GB memory, so I don't think resource was an issue.

Example gem5 script:

build/X86_MESI_Two_Level/gem5.opt --outdir=x configs/example/fs.py
--kernel=binaries/x86_64-vmlinux-3.4.112.smp
--disk-image=disks/x86_benchmark.img --script=test.rcS
--cpu-type=AtomicSimpleCPU --num-cpus=4 --caches --l1d_size=64kB
--l1i_size=64kB --l1d_assoc=2 --l1i_assoc=2 --l2cache --l2_size=16MB
--num-l2caches=4 --l2_assoc=8 --mem-channels=2 --mem-ranks=2 --mem-size=2GB
--ruby --num-dirs=2 --smt --network=garnet2.0 --topology=Mesh_XY
--mesh-rows=2


Thank you
With regards,
Reyad
___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

[gem5-users] (no subject)

[Eleanor]

Hi,

 I'm trying to run multiworkload smt. I an the hello world program from
tests, and I see that one of the outputs is displayed after m5exit. What is
the reason for this?

./build/X86/gem5.opt ./configs/example/se.py --smt --cpu-type=DerivO3CPU
--caches -c
tests/test-progs/hello/bin/x86/linux/hello;tests/test-progs/hello/bin/x86/linux/hello

gem5 Simulator System.  http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.

gem5 compiled Oct 10 2019 16:33:12
gem5 started Oct 17 2019 20:49:36
command line: ./build/X86/gem5.opt ./configs/example/se.py --smt
--cpu-type=DerivO3CPU --caches -c tests/test-progs/hello/bin/x86/linux/hello

Global frequency set at 1 ticks per second
warn: DRAM device capacity (8192 Mbytes) does not match the address range
assigned (512 Mbytes)
0: system.remote_gdb: listening for remote gdb on port 7000
 REAL SIMULATION 
info: Entering event queue @ 0.  Starting simulation...
Hello world!
Exiting @ tick 16684000 because exiting with last active thread context
Hello world!

I assume its because m5exit occurs as soon as one thread is complete, and
doesn't wait for the other one. Is there any workaround for this?

Also, I 'm trying simulate multiworkload smt with spec benchmark, but I get
Segmentation fault:

./build/X86/gem5.opt ./configs/example/se.py --smt --cpu-type=DerivO3CPU
--caches -c
"/home/benchmarks/benchspec/CPU2006/462.libquantum/exe/libquantum_base.gcc41-64bit;/home/benchmarks/benchspec/CPU2006/462.libquantum/exe/libquantum_base.gcc41-64bit"
-o "33 5;33 5"
gem5 Simulator System.  http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.

gem5 compiled Oct 10 2019 16:33:12
gem5 started Oct 17 2019 20:38:32
command line: ./build/X86/gem5.opt ./configs/example/se.py --smt
--cpu-type=DerivO3CPU --caches -c
'/home/benchmarks/benchspec/CPU2006/462.libquantum/exe/libquantum_base.gcc41-64bit;/home/benchmarks/benchspec/CPU2006/462.libquantum/exe/libquantum_base.gcc41-64bit'
-o '33 5;33 5'

Global frequency set at 1 ticks per second
warn: DRAM device capacity (8192 Mbytes) does not match the address range
assigned (512 Mbytes)
0: system.remote_gdb: listening for remote gdb on port 7000
0: system.remote_gdb: listening for remote gdb on port 7009
panic: Pio port of system.cpu.interrupts1 not connected to anything!
Memory Usage: 667812 KBytes
Program aborted at tick 0
--- BEGIN LIBC BACKTRACE ---
./build/X86/gem5.opt(_Z15print_backtracev+0x2c)[0x558ef9c26bcc]
./build/X86/gem5.opt(_Z12abortHandleri+0x4a)[0x558ef9c38e0a]
/lib/x86_64-linux-gnu/libpthread.so.0(+0x12890)[0x7fa9e6197890]
/lib/x86_64-linux-gnu/libc.so.6(gsignal+0xc7)[0x7fa9e4dfee97]
/lib/x86_64-linux-gnu/libc.so.6(abort+0x141)[0x7fa9e4e00801]
./build/X86/gem5.opt(+0x501b7f)[0x558ef9afcb7f]
./build/X86/gem5.opt(_ZN9PioDevice4initEv+0x188)[0x558efa7b4f48]
./build/X86/gem5.opt(_ZN6X86ISA10Interrupts4initEv+0x20)[0x558ef9d25940]
./build/X86/gem5.opt(+0xef67f6)[0x558efa4f17f6]
./build/X86/gem5.opt(+0x69fdd4)[0x558ef9c9add4]
/usr/lib/x86_64-linux-gnu/libpython2.7.so.1.0(PyEval_EvalFrameEx+0x7a70)[0x7fa9e6452f00]
/usr/lib/x86_64-linux-gnu/libpython2.7.so.1.0(PyEval_EvalCodeEx+0x7d8)[0x7fa9e6583708]
/usr/lib/x86_64-linux-gnu/libpython2.7.so.1.0(PyEval_EvalFrameEx+0x6364)[0x7fa9e64517f4]
/usr/lib/x86_64-linux-gnu/libpython2.7.so.1.0(PyEval_EvalCodeEx+0x7d8)[0x7fa9e6583708]
/usr/lib/x86_64-linux-gnu/libpython2.7.so.1.0(PyEval_EvalFrameEx+0x6364)[0x7fa9e64517f4]
/usr/lib/x86_64-linux-gnu/libpython2.7.so.1.0(PyEval_EvalCodeEx+0x7d8)[0x7fa9e6583708]
/usr/lib/x86_64-linux-gnu/libpython2.7.so.1.0(PyEval_EvalCode+0x19)[0x7fa9e644b2f9]
/usr/lib/x86_64-linux-gnu/libpython2.7.so.1.0(PyEval_EvalFrameEx+0x68a5)[0x7fa9e6451d35]
/usr/lib/x86_64-linux-gnu/libpython2.7.so.1.0(PyEval_EvalCodeEx+0x7d8)[0x7fa9e6583708]
/usr/lib/x86_64-linux-gnu/libpython2.7.so.1.0(PyEval_EvalFrameEx+0x6364)[0x7fa9e64517f4]
/usr/lib/x86_64-linux-gnu/libpython2.7.so.1.0(PyEval_EvalCodeEx+0x7d8)[0x7fa9e6583708]
/usr/lib/x86_64-linux-gnu/libpython2.7.so.1.0(PyEval_EvalCode+0x19)[0x7fa9e644b2f9]
/usr/lib/x86_64-linux-gnu/libpython2.7.so.1.0(PyRun_StringFlags+0x76)[0x7fa9e64fb426]
./build/X86/gem5.opt(_Z6m5MainiPPc+0x63)[0x558ef9c37843]
./build/X86/gem5.opt(main+0x38)[0x558ef9ac5048]
/lib/x86_64-linux-gnu/libc.so.6(__libc_start_main+0xe7)[0x7fa9e4de1b97]
./build/X86/gem5.opt(_start+0x2a)[0x558ef9aef36a]
--- END LIBC BACKTRACE ---
[1]5063 abort (core dumped)  ./build/X86/gem5.opt
./configs/example/se.py --smt --cpu-type=DerivO3CPU  -c

I also ran the same thing with 2 cores (not smt) in se mode, and although
it runs for a while, it gets stuck at "warn: MOVNTDQ: Ignoring non-temporal
hint, modeling as cacheable!":
last few lines:
info: Increasing stack size by one page.
info: Increasing stack size by one page.
N = 33, 31 qubits required
Random seed: 5
N = 33, 31 qubits required
Random seed: 5
warn: MOVNTDQ: Ignoring non-temporal hint, modeling as cacheable!

So I think that the proble

Re: [gem5-users] (no subject)

[Nazish Shabbir]

Thank you so much. I'll try this.

On Sun, May 12, 2019 at 10:22 PM Abhishek Singh <
abhishek.singh199...@gmail.com> wrote:

> Hello Nazish,
>
> If you are using classic memory, edit src/mem/cache/base.cc file’s
> recvTimingReq function.
> You can access the old data through blk->data and the new data by
> pkt->getdata(this you need to search in src/mem/packet.hh, I may have made
> mistake in writing correct name of the function).
>
> On Sun, May 12, 2019 at 2:52 AM Nazish Shabbir 
> wrote:
>
>>  Hello! I am relatively new to gem5 and trying to implement an encoding
>> scheme in it but not exactly sure what the best approach to implementing
>> this would be.
>>
>> The way i would like this to work is when there is a write access to the
>> last level cache, we need to read the old data in the last level cache.
>> Then we compare the new cache line with the old cache line to calculate the
>> HTs and STs.
>>
>> Where would you recommend i look to start implementing this? Which place
>> i need to start modifying?
>>
>> Thanks!
>> ___
>> gem5-users mailing list
>> gem5-users@gem5.org
>> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
>
> ___
> gem5-users mailing list
> gem5-users@gem5.org
> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] (no subject)

[Abhishek Singh]

Your logic sounds correct to me for single core.

For multi core, the last level cache is shared, and you can get block from
other core’s L1 dcache.
So you need to think through about what behavior you are expecting from
your design and make changes or keep things same.

On Mon, May 13, 2019 at 12:02 AM Muhammad Avais 
wrote:

> Dear Abhishek,
>
>  Many thanks for your reply. I will set the flag in response packet
> for L2 hit. This flag will be default reset, therefore, I think I will not
> need main memory flag in this case.
>  Please, let me know if you feel a problem in this logic.
>  For multicore simulation, what should be the difference?
>
> Many thanks for your response,
> Best regards,
> Avais
>
> On Sat, May 11, 2019 at 8:15 AM Abhishek Singh <
> abhishek.singh199...@gmail.com> wrote:
>
>> What you do, is create flags in src/mem/packet.hh for various cache
>> levels.
>> Whenever you hit in L2, you can set the L2flag in response pkt.
>> And if it is misses in L2, set main memory flag in response pkt, as you
>> are sure you will get data from main memory.
>> Here we are assuming it’s a single core simulation.
>>
>> On Fri, May 10, 2019 at 5:42 AM Muhammad Avais 
>> wrote:
>>
>>> Dear All,
>>>
>>> 1- For blocks loaded in the L1 cache, how can I distinguish that it was
>>> loaded into the L1 cache from the L2 cache (L2 hit) or main memory (L1
>>> cache)?
>>>
>>> Many thanks,
>>> Best Regards,
>>> Avais
>>> ___
>>> gem5-users mailing list
>>> gem5-users@gem5.org
>>> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
>>
>> ___
>> gem5-users mailing list
>> gem5-users@gem5.org
>> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
>
> ___
> gem5-users mailing list
> gem5-users@gem5.org
> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] (no subject)

[Muhammad Avais]

Dear Abhishek,

 Many thanks for your reply. I will set the flag in response packet for
L2 hit. This flag will be default reset, therefore, I think I will not need
main memory flag in this case.
 Please, let me know if you feel a problem in this logic.
 For multicore simulation, what should be the difference?

Many thanks for your response,
Best regards,
Avais

On Sat, May 11, 2019 at 8:15 AM Abhishek Singh <
abhishek.singh199...@gmail.com> wrote:

> What you do, is create flags in src/mem/packet.hh for various cache levels.
> Whenever you hit in L2, you can set the L2flag in response pkt.
> And if it is misses in L2, set main memory flag in response pkt, as you
> are sure you will get data from main memory.
> Here we are assuming it’s a single core simulation.
>
> On Fri, May 10, 2019 at 5:42 AM Muhammad Avais 
> wrote:
>
>> Dear All,
>>
>> 1- For blocks loaded in the L1 cache, how can I distinguish that it was
>> loaded into the L1 cache from the L2 cache (L2 hit) or main memory (L1
>> cache)?
>>
>> Many thanks,
>> Best Regards,
>> Avais
>> ___
>> gem5-users mailing list
>> gem5-users@gem5.org
>> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
>
> ___
> gem5-users mailing list
> gem5-users@gem5.org
> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] (no subject)

[Abhishek Singh]

Hello Nazish,

If you are using classic memory, edit src/mem/cache/base.cc file’s
recvTimingReq function.
You can access the old data through blk->data and the new data by
pkt->getdata(this you need to search in src/mem/packet.hh, I may have made
mistake in writing correct name of the function).

On Sun, May 12, 2019 at 2:52 AM Nazish Shabbir 
wrote:

>  Hello! I am relatively new to gem5 and trying to implement an encoding
> scheme in it but not exactly sure what the best approach to implementing
> this would be.
>
> The way i would like this to work is when there is a write access to the
> last level cache, we need to read the old data in the last level cache.
> Then we compare the new cache line with the old cache line to calculate the
> HTs and STs.
>
> Where would you recommend i look to start implementing this? Which place
> i need to start modifying?
>
> Thanks!
> ___
> gem5-users mailing list
> gem5-users@gem5.org
> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

[gem5-users] (no subject)

[Nazish Shabbir]

 Hello! I am relatively new to gem5 and trying to implement an encoding
scheme in it but not exactly sure what the best approach to implementing
this would be.

The way i would like this to work is when there is a write access to the
last level cache, we need to read the old data in the last level cache.
Then we compare the new cache line with the old cache line to calculate the
HTs and STs.

Where would you recommend i look to start implementing this? Which place  i
need to start modifying?

Thanks!
___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] (no subject)

[Abhishek Singh]

What you do, is create flags in src/mem/packet.hh for various cache levels.
Whenever you hit in L2, you can set the L2flag in response pkt.
And if it is misses in L2, set main memory flag in response pkt, as you are
sure you will get data from main memory.
Here we are assuming it’s a single core simulation.

On Fri, May 10, 2019 at 5:42 AM Muhammad Avais 
wrote:

> Dear All,
>
> 1- For blocks loaded in the L1 cache, how can I distinguish that it was
> loaded into the L1 cache from the L2 cache (L2 hit) or main memory (L1
> cache)?
>
> Many thanks,
> Best Regards,
> Avais
> ___
> gem5-users mailing list
> gem5-users@gem5.org
> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] (no subject)

[Abhishek Singh]

Hi Muhammad,

One way is to use the function "name()" in src/mem/cache/base.cc and
src/mem/cache/cache.cc file to implement cache specific function.
For e.g.,
for implementing things specifically  for dcache u can just write if
(name() == "system.cpu.dcache"){ }


Best regards,

Abhishek


On Fri, May 10, 2019 at 5:23 AM Muhammad Avais 
wrote:

>Dear All,
>
>   I have one question. For blocks loaded in the L1 cache, how can I
> distinguish that it was loaded into the L1 cache from L2 cache or main
> memory?
>
> Many thanks,
> Best regards,
> Avais
>
>
> On Wed, May 8, 2019 at 5:21 AM Abhishek Singh <
> abhishek.singh199...@gmail.com> wrote:
>
>> Hi Muhammad,
>>
>>
>> If you want on L2 hit, the block is invalidated from L2 cache and filled
>> in Dcache and the rest behavior same as you explained in the diagram, you
>> can use gem5's "most_excl" option in "gem5/src/mem/cache/Cache.py" file.
>> You may need to take care of "clean victim" from dcache which is not a
>> difficult modification.
>>
>> Best regards,
>>
>> Abhishek
>>
>>
>> On Tue, May 7, 2019 at 1:48 AM Muhammad Avais 
>> wrote:
>>
>>> Dear All,
>>>   Is 'mostly exclusive cache' supported in GEM5 classic model
>>> strictly non-exclusive cache? If it is not non-exclusive cache, how can I
>>> make it non-exclusive cache?
>>>
>>>   The non-exclusive cache is shown in Fig. below.
>>> [image: image.png]
>>>  Can anyone guide me?
>>>
>>> Many thanks,
>>> best regards,
>>> Avais
>>>
>>> ___
>>> gem5-users mailing list
>>> gem5-users@gem5.org
>>> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
>>
>> ___
>> gem5-users mailing list
>> gem5-users@gem5.org
>> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
>
> ___
> gem5-users mailing list
> gem5-users@gem5.org
> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

[gem5-users] (no subject)

[Muhammad Avais]

Dear All,

1- For blocks loaded in the L1 cache, how can I distinguish that it was
loaded into the L1 cache from the L2 cache (L2 hit) or main memory (L1
cache)?

Many thanks,
Best Regards,
Avais
___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] (no subject)

[Muhammad Avais]

   Dear All,

  I have one question. For blocks loaded in the L1 cache, how can I
distinguish that it was loaded into the L1 cache from L2 cache or main
memory?

Many thanks,
Best regards,
Avais


On Wed, May 8, 2019 at 5:21 AM Abhishek Singh <
abhishek.singh199...@gmail.com> wrote:

> Hi Muhammad,
>
>
> If you want on L2 hit, the block is invalidated from L2 cache and filled
> in Dcache and the rest behavior same as you explained in the diagram, you
> can use gem5's "most_excl" option in "gem5/src/mem/cache/Cache.py" file.
> You may need to take care of "clean victim" from dcache which is not a
> difficult modification.
>
> Best regards,
>
> Abhishek
>
>
> On Tue, May 7, 2019 at 1:48 AM Muhammad Avais 
> wrote:
>
>> Dear All,
>>   Is 'mostly exclusive cache' supported in GEM5 classic model
>> strictly non-exclusive cache? If it is not non-exclusive cache, how can I
>> make it non-exclusive cache?
>>
>>   The non-exclusive cache is shown in Fig. below.
>> [image: image.png]
>>  Can anyone guide me?
>>
>> Many thanks,
>> best regards,
>> Avais
>>
>> ___
>> gem5-users mailing list
>> gem5-users@gem5.org
>> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
>
> ___
> gem5-users mailing list
> gem5-users@gem5.org
> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] (no subject)

[Muhammad Avais]

Dear Abhishek,

  Many thanks for the useful response, I will try to modify clean
victim eviction from "dcache".

Many thanks,
Best regards,
Avais

On Wed, May 8, 2019 at 5:21 AM Abhishek Singh <
abhishek.singh199...@gmail.com> wrote:

> Hi Muhammad,
>
>
> If you want on L2 hit, the block is invalidated from L2 cache and filled
> in Dcache and the rest behavior same as you explained in the diagram, you
> can use gem5's "most_excl" option in "gem5/src/mem/cache/Cache.py" file.
> You may need to take care of "clean victim" from dcache which is not a
> difficult modification.
>
> Best regards,
>
> Abhishek
>
>
> On Tue, May 7, 2019 at 1:48 AM Muhammad Avais 
> wrote:
>
>> Dear All,
>>   Is 'mostly exclusive cache' supported in GEM5 classic model
>> strictly non-exclusive cache? If it is not non-exclusive cache, how can I
>> make it non-exclusive cache?
>>
>>   The non-exclusive cache is shown in Fig. below.
>> [image: image.png]
>>  Can anyone guide me?
>>
>> Many thanks,
>> best regards,
>> Avais
>>
>> ___
>> gem5-users mailing list
>> gem5-users@gem5.org
>> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
>
> ___
> gem5-users mailing list
> gem5-users@gem5.org
> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] (no subject)

[Abhishek Singh]

Hi Muhammad,


If you want on L2 hit, the block is invalidated from L2 cache and filled in
Dcache and the rest behavior same as you explained in the diagram, you can
use gem5's "most_excl" option in "gem5/src/mem/cache/Cache.py" file.
You may need to take care of "clean victim" from dcache which is not a
difficult modification.

Best regards,

Abhishek


On Tue, May 7, 2019 at 1:48 AM Muhammad Avais 
wrote:

> Dear All,
>   Is 'mostly exclusive cache' supported in GEM5 classic model strictly
> non-exclusive cache? If it is not non-exclusive cache, how can I make it
> non-exclusive cache?
>
>   The non-exclusive cache is shown in Fig. below.
> [image: image.png]
>  Can anyone guide me?
>
> Many thanks,
> best regards,
> Avais
>
> ___
> gem5-users mailing list
> gem5-users@gem5.org
> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

[gem5-users] (no subject)

[Muhammad Avais]

Dear All,
  Is 'mostly exclusive cache' supported in GEM5 classic model strictly
non-exclusive cache? If it is not non-exclusive cache, how can I make it
non-exclusive cache?

  The non-exclusive cache is shown in Fig. below.
[image: image.png]
 Can anyone guide me?

Many thanks,
best regards,
Avais
___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

[gem5-users] (no subject)

[Abbas Fairouz]

Hi there,

I trying to run a binary file on GEM5, but I'm getting a weird error and it
is stuck on it. When I run the same binary file on my actual machine, it
runs perfect.

The error is highlighted in yellow bellow:


**
GEM5 terminal output:
***

*gem5ht64*~> ./build/X86/gem5.opt -d m5out/test ./configs/example/fs.py
--cpu-clock=1GHz --caches --l2cache --l1d_size=128kB
--checkpoint-dir=m5out/cpt_general -r 1 --script=myscripts/swhash_test
--mem-type=ddr3_1600_x64 --cpu-type=detailed

gem5 Simulator System.  http://gem5.org

gem5 is copyrighted software; use the --copyright option for details.


gem5 compiled Aug 15 2018 13:11:54

gem5 started Aug 15 2018 17:58:36

gem5 executing on ecesvj10101.ece.tamu.edu

command line: ./build/X86/gem5.opt -d m5out/test ./configs/example/fs.py
--cpu-clock=1GHz --caches --l2cache --l1d_size=128kB
--checkpoint-dir=m5out/cpt_general -r 1 --script=myscripts/swhash_test
--mem-type=ddr3_1600_x64 --cpu-type=detailed

Global frequency set at 1 ticks per second

info: kernel located at:
/home/grads/a/afairouz/201_hash_GEM5/gem5/system/binaries/x86_64-vmlinux-2.6.28.4-smp

  0: rtc: Real-time clock set to Sun Jan  1 00:00:00 2012

Listening for com_1 connection on port 3456

warn: Reading current count from inactive timer.

0: system.remote_gdb.listener: listening for remote gdb #0 on port 7000

Switch at curTick count:1

info: Entering event queue @ 4982563282000.  Starting simulation...

Switched CPUS @ tick 4982563292000

switching cpus

 REAL SIMULATION 

info: Entering event queue @ 4982563292000.  Starting simulation...

warn: Don't know what interrupt to clear for console.

warn: x86 cpuid: unimplemented function 7

warn: Tried to clear PCI interrupt 14


*
GEM5 terminal of port 3456 output:
**

*gem5ht64*~> ./m5term localhost 3456

 m5 slave terminal: Terminal 0 

Loading new script...

runscript[946]: segfault at 814840 ip 0041ce03 sp 7fffba11cb98
error 6 in runscript[40+bd000]

Clocksource tsc unstable (delta = -49916 ns)





Does anyone ran into this issue before?



Best regards,
Abbas Fairouz
___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

[gem5-users] (no subject)

[Nikhitha Josh]

What does m_vc member of flit.hh in garnet2.0 store? Why is it used?
___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] (no subject)

[Krishna, Tushar]

http://www.gem5.org/Garnet2.0

It is woken up by both the coherence protocol buffers and the router to NI 
links connected to it.

Cheers,
Tushar

On Jun 26, 2018, 2:48 AM -0400, Nikhitha Josh , wrote:
Hi,
Which class calls the Network Interface wakeup() function?

Regards,
Nikhitha

___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

[gem5-users] (no subject)

[Nikhitha Josh]

Hi,
Which class calls the Network Interface wakeup() function?

Regards,
Nikhitha
___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

[gem5-users] (no subject)

[Nikhitha Josh]

Hi,
Where in gem5 are new objects of Message being created?

Thanks,
Nikhitha
___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

[gem5-users] (no subject)

[Nikhitha Josh]

 Hi,
I'm a beginner in gem5 and I'm  trying  to create my own packet and send it
from a certain source to a certain destination. I'm finding some trouble
with the net_dest component of RouteInfo structure.
I cant understand the actual concept of the NetDest class.
Please help me in this regard.

Thanks,
Nikhitha
___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

[gem5-users] (no subject)

[Muhammad Avais]

Dear All,
  Has anyone made some list of read intensive or data intensive
SPEC2006 benchmarks or some other benchmarks

Many Thanks
Best Regards
Avais
___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] (no subject)

[SHARJEEL KHILJI]

Hello
yes if you are using ruby memory system you can select the type of protocol
(e.g., MESI Two level, MOESI CMP Directory etc).

regards,
Muhammad

On 11 October 2017 at 10:51, Muhammad Avais  wrote:

> Hi,
> Does GEM5 follows any specific cache coherence protocol?
>  If yes? then which one?
> Thanks
>
> ___
> gem5-users mailing list
> gem5-users@gem5.org
> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
>
___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

[gem5-users] (no subject)

[Muhammad Avais]

Hi,
Does GEM5 follows any specific cache coherence protocol?
 If yes? then which one?
Thanks
___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

[gem5-users] (no subject)

[Muhammad Avais]

Hi,

  I have question regarding 'ResponseLatency' of Cache. Is it
technology dependent or has fixed value?

 How to choose its value?

Thanks
___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

[gem5-users] (no subject)

[‪mostafa habib‬ ‪]

Hi
I am a new user of gem5 I want to realize a simulation of 4 benchmarks of the 
mibench suite, my goal is to study the shared  l2 cache and private L2 cache. I 
compile jpeg for ARM architecture and when I executed it with the following 
command I could not find the miss rate and hit rate for each core, the majority 
of the values are null in stats file. I am using MESI protocol and ruby  How 
can I get asimple architecture with a private L1 for each Core and a shared L2? 
And how to get the number of miss or miss rate?How can I specify num bank of 
the cache 
Can I sent a command for all benchmark on one time
 The command is:./build/ARM/gem5.opt configs/example/se.py -n 16 --ruby -c 
/home/mostafa/gem5/mibench/consumer/jpeg/jpeg-6a/cjpeg '--option=-dct int 
-progressive -opt -outfile 
/home/mostafa/gem5/mibench/consumer/jpeg/output_large_encode.jpeg  
/home/mostafa/gem5/mibench/consumer/jpeg/input_large.ppm' --caches 
--l1d_size=32kB --l1i_size=32kB --l1d_assoc=4 --l1i_assoc=4 --l2cache  
--l2_size=1MB --num-l2caches=16 --l2_assoc=8 --cacheline_size=64  
--cpu-type=arm_detailedI would be very grateful for a help thank you  ___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

[gem5-users] (no subject)

[azarakhsh1986_2020]

hii ran gem5  with 9 core and ruby memory, is it true that cpu0 and cpu1 and 
cpu2 send most request and the others haven't any request (in smilarge 
benchmark)?___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

[gem5-users] (no subject)

[张月明]

help

___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

[gem5-users] (no subject)

[Zahra Azad]

___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

[gem5-users] (no subject)

[Alec Roelke]

Hello,

I’m trying to simulate a SPARC processor with SMT enabled in SE mode.  When I 
enable the SMT switch (using --smt --cpu-type=detailed --caches) with a single 
core, it works fine if there’s only one workload.  If I add a second workload, 
though, I get an assertion error that “params->numPhysIntRegs >= numThreads * 
SparcISA::NumIntRegs” has failed.  For reference, the command I’m using to run 
GEM5 is this:

build/SPARC/gem5.opt configs/example/se.py -c 
'tests/test-progs/hello/bin/sparc/linux/hello;tests/test-progs/hello/bin/sparc/linux/hello'
 --smt --caches --cpu-type=detailed

The full error I receive is this:

gem5.opt: build/SPARC/cpu/o3/cpu.cc:270: 
FullO3CPU::FullO3CPU(DerivO3CPUParams*) [with Impl = O3CPUImpl]: 
Assertion `params->numPhysIntRegs >= numThreads * SparcISA::NumIntRegs' failed.

I looked into the error and it appears that SPARC has 169 integer registers.  
When multiplied by a numThreads value of 2 from having two workloads, that 
exceeds the number of physical integer registers available.  My understanding 
was that SPARC had 32 integer registers per hardware thread, but when I change 
it I get the following error:

gem5.opt: build/SPARC/cpu/o3/free_list.hh:68: PhysRegIndex 
SimpleFreeList::getReg(): Assertion `!freeRegs.empty()' failed.

Has anyone gotten SMT to work with SPARC in SE mode?  Is there some 
configuration I’m missing that will make it work?

Thanks in advance for your help.
___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

[gem5-users] (no subject)

[Khaled Attia]

-- 
*Khaled M. Attia*
*T.A. @ Computers & Systems Engineering*
*Mansoura University, Egypt*
Mob. : +201000736160
email: khaled.3ttia[at]gmail.com
___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

[gem5-users] (no subject)

[Minu Cherian]

Hello everyone,

I want the benchmark of alpha to evaluate the performance of the
system.Please help me.

Thanks & regards

Minu
___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

[gem5-users] (no subject)

[gopayya]

Hi,
 i have my own algorithm to  shared last level cache L2 that is LRR ,
 I have implemented LRRPolicy.cc file same as like LRUPolicy and i am
using two extra bits for replacing line L2, depends on the information
available in L1 cache.

here is the problem is how to run two separate replacement policies one
at L1 cache and other one at L2 cache with sigle core and multiple cores,


and finally what are files i need to gothrough for more better work


thanks and regards,
gopi,
india

___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

[gem5-users] (no subject)

[Tanvir Mustofa]

Hello,

I am new to gem5. I have seen some earlier posts discussing generation of
ruby.stat. I am using X86_MESI_Two_Level binary with config script fs.py
with ruby enabled. But I don't see any such file (ruby.stat). can anyone
help me with this.

Regards
Dhruvo
___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

[gem5-users] (no subject)

[babak aghaei via gem5-users]

Hi What we would do when we modified a file in gem5 repo for seeing the result 
of this modification!?  
---Babak Aghaei 
Ph.D candidate
___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

[gem5-users] (no subject)

[babak aghaei via gem5-users]

Hi
this is possible, befor you must establish the garnet network and then run any 
benchmark on it.
best

---
Babak Aghaei 
Ph.D candidate
___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] (no subject)

[Matheus Alcântara Souza via gem5-users]

I've compiled Parsec v.2.1 for M5 following the instructions on
http://www.cs.utexas.edu/~cart/parsec_m5/. The code changes I needed were a
few, so I did not have much efforts.

You should aim this using the same instructions, reading the Tech Report
http://www.cs.utexas.edu/~parsec_m5/TR-09-32.pdf.

The crosscompiler is available in http://www.m5sim.org/Download. Pay
attention to the Kernel Version used to compile.

Best Regards.
Matheus

2014-09-28 11:51 GMT-03:00 babak aghaei via gem5-users 
:

> Hi
> Is anybody has run Parsec 3.0 on ALPHA ISA?
>  plz help!
> ---
>
> *Babak Aghaei **Ph.D candidate* in *Computer*
> *Engineering (Hardware),Science and Research University*
> *Tehran, IRAN *
> *E-Mail: * *B  *
> .agh...@iaut.ac.ir
> *E-Mail: **babak_agha...@yahoo.com* 
> *E-Mail: **babak.agha...@gmail.com* 
>
> ___
> gem5-users mailing list
> gem5-users@gem5.org
> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
>



-- 

Atenciosamente,
Matheus Alcântara Souza
___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

[gem5-users] (no subject)

[babak aghaei via gem5-users]

Hi
Is anybody has run Parsec 3.0 on ALPHA ISA?

 plz help!

---
Babak Aghaei 
Ph.D candidate in Computer Engineering (Hardware),
Science and Research University
Tehran, IRAN 
E-Mail: b.agh...@iaut.ac.ir
E-Mail: babak_agha...@yahoo.com 
E-Mail: babak.agha...@gmail.com ___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

[gem5-users] (no subject)

[Yingying Tian via gem5-users]

Hi,

I am using the latest stable version for x86+ruby+FS. I encountered the
same assertion failure as the following email (posted in May) when I
increased the memory size to 8GB. Could you please give me any suggestions?

Thanks,
Yingying


HI everybody:

I am also facing the assertaion error which is described by

Panagiotis Grivas.? Also, I want to increase the mem-size to 8GB in the
(ruby+FS+ALPHA+) what is required to do that. I tried by using
(ruby+FS+X86) to increase the memory size to 8GB (using the gem5
development version) unfortunately there was assertaion error at the kernel
booting in the file?src/mem/ruby/system/DirectoryMemory.cc

AbstractEntry*
DirectoryMemory::lookup(PhysAddress address)
{
??? assert(isPresent(address));
??? DPRINTF(RubyCache, "Looking up address: %s\n", address);

??? if (m_use_map) {
??? return m_sparseMemory->lookup(address);
??? }
else
{
??? uint64_t idx = mapAddressToLocalIdx(address);
??? assert(idx < m_num_entries); ==
=>Here the error
??? return m_entries[idx];
??? }
}



I use the follwing command line:

./build/X86/gem5.opt blackscholes? configs/example/ruby_fs.py -n 16
--num-dirs=16 --topology=Mesh --mesh-rows=4 --caches --l2cache
--num-l2caches=16 --l1d_size=32kB --l1i_size=32kB --l2_size=256kB
--l1d_assoc=4 --l1i_assoc=4 --l2_assoc=8 --cpu-clock=3GHz --mem-size=8GB
--disk-image=x86root-parsec.img --kernel=x86_64-vmlinux-2.6.28.4-smp
--script=small_sim/runscript_blackscholes.rcs? -s 51000


Thank you in advanced
Tareq
___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

[gem5-users] (no subject)

[babak aghaei via gem5-users]

Hi All

I have run the parsec all benchmarks in standalone, but in gem5, when I 
create the disk image for ALPHA ISA by contain parsec 3.0 and run 
simulation I face with the bash script problem like this:

/parsec-3.0/bin/parsecmgmt:line 1288: ${BASH_VERSINFO[0]}: bad substitution
/parsec-3.0/bin/parsecmgmt: line 794: date: command not found
..
I think this errors becoz bash old version, and I try update the disk 
bash file but I can't. can you guid me what I must be do for running 
parsec 3.0 on ALPHA ISA gem5.
BEST  
 
 
---
Babak Aghaei 
Ph.D candidate in Computer Engineering (Hardware),
Science and Research University
Tehran, IRAN 
E-Mail: b.agh...@iaut.ac.ir
E-Mail: babak_agha...@yahoo.com 
E-Mail: babak.agha...@gmail.com ___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

[gem5-users] (no subject)

[Vishaal Mohan via gem5-users]

Hello,
I have been trying to run Asimbench(renamed as Moby) on gem5. I made the
changes to FSConfig.py as mentioned in the wiki page to boot the sdcard
along with the android image. When I looked at the screenshots that are
dumped into m5out, I realized that the benchmarks aren't running. For
example, when I try to run the mxplayer benchmark, there is an error
message in the screenshot that says that the video can't be played and in
the PDF reader, it says that the document could not be found.
I checked the /mnt/sdcard/ folder within the android image and it seems to
be empty. Is there anything I am missing?
Thank you.

Cheers
--Vishaal Mohan
___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

[gem5-users] (no subject)

[Ashish Venkat]

—
Sent via Carrier Pigeon___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] (no subject)

[Mitch Hayenga]

Amin/Tony, there is a very big reason for why gem5 does this.  It's about
modeling what real processors do.

Modern out of orders are very deeply pipelined and instructions take
multiple cycles to execute from the time they are scheduled.  To enable
back-to-back execution of dependent instructions, the scheduler
speculatively schedules instructions multiple cycles ahead of time based on
the assumed execution cycle of the producer instructions.  If all
instructions take the expected latencies, dependent instructions catch
their operands via the bypass paths.  Loads throw a wrench into this
because they can have variable latencies (miss in the L1 cache, be blocked,
etc).  In a real pipeline, if a load misses or is blocked the speculative
schedule of instructions gets messed up.  The hard part is that some
portion of the scheduled instructions may have been independent of the
load, whereas other instructions fall in the load-dependent program slice.
 The amount of control logic to precisely determine mischeduled dependent
instructions is prohibitive, so squashing/replaying instructions is a
common technique.  There are various levels of preciseness that can be done
for replaying instructions.  If I remember right o3's was very
conservative/pessimistic.

Here is a good paper that discusses replay schemes and their impact.

Understanding Scheduling Replay Schemes
Ilhyun Kim and Mikko H. Lipasti
http://pharm.ece.wisc.edu/papers/hpca2004ikim.pdf

Whoever coded the o3 model decided that since stores do not produce
register operands, the replay is unnecessary there.



On Thu, Sep 26, 2013 at 6:35 PM, Amin Farmahini  wrote:

> Tony,
>
> I noticed the same thing as well and as you mentioned the perf penalty
> could be really high.
> http://www.mail-archive.com/gem5-users@gem5.org/msg05894.html
> I don't know what the reason could be, but I was able to fix this. If I
> remember right, to prevent squashing, you need to mark those loads with a
> flag or something and try to add them to instruction queue again.
>
> Thanks,
> Amin
>
>
> On Thu, Sep 26, 2013 at 6:21 PM, Tony Nowatzki  wrote:
>
>> Hi All,
>>
>> Apologies in advance if this is a silly question, or a repeat.
>>
>> I recently noticed that the OoO core squashes itself and all younger
>> instructions when a load is issued to the memory system, but the cache is
>> blocked (say the MSHRs are full, or there are no targets left). Contrarily,
>> when a write is issued to the memory system, the store will simply retry
>> until the cache can handle the request.
>>
>> There is potentially some performance penalty in squashing these loads,
>> and a large energy penalty as well (can be up to 2x for the core in some
>> contrived cases, according to mcpat).  Given that these squashes can occur
>> frequently in memory-bound programs, is there a reason this was chosen as
>> the implementation?  Is there a reason why loads can't be stalled and
>> retried on a cache block?
>>
>> Thanks!
>> Tony
>> __**_
>> gem5-users mailing list
>> gem5-users@gem5.org
>> http://m5sim.org/cgi-bin/**mailman/listinfo/gem5-users
>>
>
>
> ___
> gem5-users mailing list
> gem5-users@gem5.org
> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
>
___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] (no subject)

[Amin Farmahini]

Tony,

I noticed the same thing as well and as you mentioned the perf penalty
could be really high.
http://www.mail-archive.com/gem5-users@gem5.org/msg05894.html
I don't know what the reason could be, but I was able to fix this. If I
remember right, to prevent squashing, you need to mark those loads with a
flag or something and try to add them to instruction queue again.

Thanks,
Amin


On Thu, Sep 26, 2013 at 6:21 PM, Tony Nowatzki  wrote:

> Hi All,
>
> Apologies in advance if this is a silly question, or a repeat.
>
> I recently noticed that the OoO core squashes itself and all younger
> instructions when a load is issued to the memory system, but the cache is
> blocked (say the MSHRs are full, or there are no targets left). Contrarily,
> when a write is issued to the memory system, the store will simply retry
> until the cache can handle the request.
>
> There is potentially some performance penalty in squashing these loads,
> and a large energy penalty as well (can be up to 2x for the core in some
> contrived cases, according to mcpat).  Given that these squashes can occur
> frequently in memory-bound programs, is there a reason this was chosen as
> the implementation?  Is there a reason why loads can't be stalled and
> retried on a cache block?
>
> Thanks!
> Tony
> __**_
> gem5-users mailing list
> gem5-users@gem5.org
> http://m5sim.org/cgi-bin/**mailman/listinfo/gem5-users
>
___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

[gem5-users] (no subject)

[Tony Nowatzki]

Hi All,

Apologies in advance if this is a silly question, or a repeat.

I recently noticed that the OoO core squashes itself and all younger 
instructions when a load is issued to the memory system, but the cache 
is blocked (say the MSHRs are full, or there are no targets left). 
Contrarily, when a write is issued to the memory system, the store 
will simply retry until the cache can handle the request.


There is potentially some performance penalty in squashing these 
loads, and a large energy penalty as well (can be up to 2x for the 
core in some contrived cases, according to mcpat).  Given that these 
squashes can occur frequently in memory-bound programs, is there a 
reason this was chosen as the implementation?  Is there a reason why 
loads can't be stalled and retried on a cache block?


Thanks!
Tony
___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] (no subject)

[Mahshid Sedghi]

Thanks a lot Amin. Now it's working. I actually had to insert the line in
Simulation.py rather than fs.py, since I switch cpus after restoring from
checkpoint and therefore, I had to assign the robsize to "switch_cpus"
rather than "system.cpu".

Appreciate your help,
Mahshid


On Wed, Jul 17, 2013 at 2:32 AM, Amin Farmahini  wrote:

> You should not add it there. O3CPU.py defines the variables (processor
> parameters in this case) with their default values.
> You should add it to your se.py or fe.py. After you instantiate your
> processor, you can set this up. Something like:
> system.cpu[?].numROBEntries = option.robsize
>
> (Actually this is not the recommended way if you want to keep your code
> clean, but it is the easier way. The better way is to make a separate
> python file to take care of such things like what is done in CacheConfig.py)
>
> Amin
>
>
> On Wed, Jul 17, 2013 at 12:12 AM, Mahshid Sedghi  > wrote:
>
>> Thanks Tao and Amin. I am able to add options, but I am not able to
>> assign it to numROBEntries. I mean when I use this in O3CPU.py:
>>
>> numROBEntries = options.robsize
>>
>> it doesn't work, since options module is not defined here. I tried
>> importing options, but still didn't work. Can you elaborate on how to do
>> this?
>>
>> Thanks.
>>
>>
>> On Tue, Jul 16, 2013 at 9:32 PM, Zheng Wu  wrote:
>>
>>> Hi,
>>>
>>> I am also curious about how to create new options as well. The
>>> numRobEntries in O3CPU.py you mentioned has the following:
>>>
>>> "numROBEntries = Param.Unsigned(192, "Number of reorder buffer entries")"
>>>
>>> How is this related to options.robsize as mentioned?
>>>
>>>
>>> In addition, what if I were to add another data member to a class and
>>> want to use python options to set the value, what additional steps or
>>> procedure do i need to perform? Do I need to do anything with SWIG or
>>> something?
>>>
>>> Thanks,
>>> Zheng Wu
>>>
>>>
>>> On 2013-07-16, at 8:23 PM, Amin Farmahini  wrote:
>>>
>>> The last thing that Tao forgot to mention is to use options.robsize to
>>> set the value of numROBEntries (numROBEntries is defined in
>>> src/cpu/o3/O3CPU.py).
>>>
>>> Amin
>>>
>>>
>>> On Tue, Jul 16, 2013 at 5:06 PM, Tao Zhang wrote:
>>>
>>>> Hi Mahshid,
>>>>
>>>> ** **
>>>>
>>>> You can use the “add_option” to add any desired options in the command
>>>> line. To do this, you just add the line below (or something like it) at the
>>>> beginning of your fs.py. 
>>>>
>>>> ** **
>>>>
>>>> parser.add_option("-rob", "--robsize", type="int", default=128,
>>>> help=”specify the rob size”);
>>>>
>>>> ** **
>>>>
>>>> Then, after all options (including the default options and personalized
>>>> options) have been parsed (in other words, the variable ‘options’ is
>>>> initialized), you can simply leverage the option below.
>>>>
>>>> ** **
>>>>
>>>> options.robsize
>>>>
>>>> ** **
>>>>
>>>> After this, you can use the option in the command line, like
>>>>
>>>> ** **
>>>>
>>>> gem5.opt configs/example/se.py --robsize=64 ……
>>>>
>>>> ** **
>>>>
>>>> Note that if your option includes dash “-”, it will be converted into
>>>> underscore “_”. For example, “--rob-size” produces representative
>>>> “options.rob_size”. 
>>>>
>>>> ** **
>>>>
>>>> Also, it is pretty helpful if you look at the Options.py to see how the
>>>> default options are added into the system. The file is in configs/common/.
>>>> 
>>>>
>>>> ** **
>>>>
>>>> -Tao
>>>>
>>>> ** **
>>>>
>>>> ** **
>>>>
>>>> *From:* gem5-users-boun...@gem5.org [mailto:gem5-users-boun...@gem5.org]
>>>> *On Behalf Of *Mahshid Sedghi
>>>> *Sent:* Tuesday, July 16, 2013 4:35 PM
>>>> *To:* gem5 users mailing list
>>>> *Subject:* [gem5-users] (no subject)
>>>>
>>>> ** **
>>>>
>>>> Hello,
>>>>
>>>>

Re: [gem5-users] (no subject)

[Amin Farmahini]

You should not add it there. O3CPU.py defines the variables (processor
parameters in this case) with their default values.
You should add it to your se.py or fe.py. After you instantiate your
processor, you can set this up. Something like:
system.cpu[?].numROBEntries = option.robsize

(Actually this is not the recommended way if you want to keep your code
clean, but it is the easier way. The better way is to make a separate
python file to take care of such things like what is done in CacheConfig.py)

Amin


On Wed, Jul 17, 2013 at 12:12 AM, Mahshid Sedghi
wrote:

> Thanks Tao and Amin. I am able to add options, but I am not able to assign
> it to numROBEntries. I mean when I use this in O3CPU.py:
>
> numROBEntries = options.robsize
>
> it doesn't work, since options module is not defined here. I tried
> importing options, but still didn't work. Can you elaborate on how to do
> this?
>
> Thanks.
>
>
> On Tue, Jul 16, 2013 at 9:32 PM, Zheng Wu  wrote:
>
>> Hi,
>>
>> I am also curious about how to create new options as well. The
>> numRobEntries in O3CPU.py you mentioned has the following:
>>
>> "numROBEntries = Param.Unsigned(192, "Number of reorder buffer entries")"
>>
>> How is this related to options.robsize as mentioned?
>>
>>
>> In addition, what if I were to add another data member to a class and
>> want to use python options to set the value, what additional steps or
>> procedure do i need to perform? Do I need to do anything with SWIG or
>> something?
>>
>> Thanks,
>> Zheng Wu
>>
>>
>> On 2013-07-16, at 8:23 PM, Amin Farmahini  wrote:
>>
>> The last thing that Tao forgot to mention is to use options.robsize to
>> set the value of numROBEntries (numROBEntries is defined in
>> src/cpu/o3/O3CPU.py).
>>
>> Amin
>>
>>
>> On Tue, Jul 16, 2013 at 5:06 PM, Tao Zhang wrote:
>>
>>> Hi Mahshid,
>>>
>>> ** **
>>>
>>> You can use the “add_option” to add any desired options in the command
>>> line. To do this, you just add the line below (or something like it) at the
>>> beginning of your fs.py. 
>>>
>>> ** **
>>>
>>> parser.add_option("-rob", "--robsize", type="int", default=128,
>>> help=”specify the rob size”);
>>>
>>> ** **
>>>
>>> Then, after all options (including the default options and personalized
>>> options) have been parsed (in other words, the variable ‘options’ is
>>> initialized), you can simply leverage the option below.
>>>
>>> ** **
>>>
>>> options.robsize
>>>
>>> ** **
>>>
>>> After this, you can use the option in the command line, like
>>>
>>> ** **
>>>
>>> gem5.opt configs/example/se.py --robsize=64 ……
>>>
>>> ** **
>>>
>>> Note that if your option includes dash “-”, it will be converted into
>>> underscore “_”. For example, “--rob-size” produces representative
>>> “options.rob_size”. 
>>>
>>> ** **
>>>
>>> Also, it is pretty helpful if you look at the Options.py to see how the
>>> default options are added into the system. The file is in configs/common/.
>>> 
>>>
>>> ** **
>>>
>>> -Tao
>>>
>>> ** **
>>>
>>> ** **
>>>
>>> *From:* gem5-users-boun...@gem5.org [mailto:gem5-users-boun...@gem5.org]
>>> *On Behalf Of *Mahshid Sedghi
>>> *Sent:* Tuesday, July 16, 2013 4:35 PM
>>> *To:* gem5 users mailing list
>>> *Subject:* [gem5-users] (no subject)
>>>
>>> ** **
>>>
>>> Hello,
>>>
>>> ** **
>>>
>>> I want to introduce a new option to the simulation script to define the
>>> ROB size, since I am doing experiments with different ROB sizes and would
>>> like to skip the procedure of rebuilding the gem5 again and again for
>>> different ROB sizes. Basically, I need to do a similar thing as the thread
>>> below:
>>>
>>> ** **
>>>
>>> http://www.mail-archive.com/gem5-users@gem5.org/msg00480.html
>>>
>>> ** **
>>>
>>> I am not still sure how to relate the option with the cpu parameters.
>>> I'd appreciate it if someone can give me some hints.
>>>
>>> ** **
>>>
>>> Thanks,
>>>
>>> Mahshid
>>>
>>> ___
>>> gem5-users mailing list
>>> gem5-users@gem5.org
>>> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
>>>
>>
>> ___
>> gem5-users mailing list
>> gem5-users@gem5.org
>> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
>>
>>
>>
>> ___
>> gem5-users mailing list
>> gem5-users@gem5.org
>> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
>>
>
>
> ___
> gem5-users mailing list
> gem5-users@gem5.org
> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
>
___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] (no subject)

[Mahshid Sedghi]

Thanks Tao and Amin. I am able to add options, but I am not able to assign
it to numROBEntries. I mean when I use this in O3CPU.py:

numROBEntries = options.robsize

it doesn't work, since options module is not defined here. I tried
importing options, but still didn't work. Can you elaborate on how to do
this?

Thanks.


On Tue, Jul 16, 2013 at 9:32 PM, Zheng Wu  wrote:

> Hi,
>
> I am also curious about how to create new options as well. The
> numRobEntries in O3CPU.py you mentioned has the following:
>
> "numROBEntries = Param.Unsigned(192, "Number of reorder buffer entries")"
>
> How is this related to options.robsize as mentioned?
>
>
> In addition, what if I were to add another data member to a class and want
> to use python options to set the value, what additional steps or procedure
> do i need to perform? Do I need to do anything with SWIG or something?
>
> Thanks,
> Zheng Wu
>
>
> On 2013-07-16, at 8:23 PM, Amin Farmahini  wrote:
>
> The last thing that Tao forgot to mention is to use options.robsize to set
> the value of numROBEntries (numROBEntries is defined in
> src/cpu/o3/O3CPU.py).
>
> Amin
>
>
> On Tue, Jul 16, 2013 at 5:06 PM, Tao Zhang wrote:
>
>> Hi Mahshid,
>>
>> ** **
>>
>> You can use the “add_option” to add any desired options in the command
>> line. To do this, you just add the line below (or something like it) at the
>> beginning of your fs.py. 
>>
>> ** **
>>
>> parser.add_option("-rob", "--robsize", type="int", default=128,
>> help=”specify the rob size”);
>>
>> ** **
>>
>> Then, after all options (including the default options and personalized
>> options) have been parsed (in other words, the variable ‘options’ is
>> initialized), you can simply leverage the option below.
>>
>> ** **
>>
>> options.robsize
>>
>> ** **
>>
>> After this, you can use the option in the command line, like
>>
>> ** **
>>
>> gem5.opt configs/example/se.py --robsize=64 ……
>>
>> ** **
>>
>> Note that if your option includes dash “-”, it will be converted into
>> underscore “_”. For example, “--rob-size” produces representative
>> “options.rob_size”. 
>>
>> ** **
>>
>> Also, it is pretty helpful if you look at the Options.py to see how the
>> default options are added into the system. The file is in configs/common/.
>> 
>>
>> ** **
>>
>> -Tao
>>
>> ** **
>>
>> ** **
>>
>> *From:* gem5-users-boun...@gem5.org [mailto:gem5-users-boun...@gem5.org]
>> *On Behalf Of *Mahshid Sedghi
>> *Sent:* Tuesday, July 16, 2013 4:35 PM
>> *To:* gem5 users mailing list
>> *Subject:* [gem5-users] (no subject)
>>
>> ** **
>>
>> Hello,
>>
>> ** **
>>
>> I want to introduce a new option to the simulation script to define the
>> ROB size, since I am doing experiments with different ROB sizes and would
>> like to skip the procedure of rebuilding the gem5 again and again for
>> different ROB sizes. Basically, I need to do a similar thing as the thread
>> below:
>>
>> ** **
>>
>> http://www.mail-archive.com/gem5-users@gem5.org/msg00480.html
>>
>> ** **
>>
>> I am not still sure how to relate the option with the cpu parameters. I'd
>> appreciate it if someone can give me some hints.
>>
>> ** **
>>
>> Thanks,
>>
>> Mahshid
>>
>> ___
>> gem5-users mailing list
>> gem5-users@gem5.org
>> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
>>
>
> ___
> gem5-users mailing list
> gem5-users@gem5.org
> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
>
>
>
> ___
> gem5-users mailing list
> gem5-users@gem5.org
> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
>
___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] (no subject)

[Zheng Wu]

Hi,

I am also curious about how to create new options as well. The numRobEntries in 
O3CPU.py you mentioned has the following:

"numROBEntries = Param.Unsigned(192, "Number of reorder buffer entries")"

How is this related to options.robsize as mentioned?


In addition, what if I were to add another data member to a class and want to 
use python options to set the value, what additional steps or procedure do i 
need to perform? Do I need to do anything with SWIG or something?

Thanks,
Zheng Wu


On 2013-07-16, at 8:23 PM, Amin Farmahini  wrote:

> The last thing that Tao forgot to mention is to use options.robsize to set 
> the value of numROBEntries (numROBEntries is defined in src/cpu/o3/O3CPU.py).
> 
> Amin
> 
> 
> On Tue, Jul 16, 2013 at 5:06 PM, Tao Zhang  wrote:
> Hi Mahshid,
> 
>  
> 
> You can use the “add_option” to add any desired options in the command line. 
> To do this, you just add the line below (or something like it) at the 
> beginning of your fs.py.
> 
>  
> 
> parser.add_option("-rob", "--robsize", type="int", default=128, help=”specify 
> the rob size”);
> 
>  
> 
> Then, after all options (including the default options and personalized 
> options) have been parsed (in other words, the variable ‘options’ is 
> initialized), you can simply leverage the option below.
> 
>  
> 
> options.robsize
> 
>  
> 
> After this, you can use the option in the command line, like
> 
>  
> 
> gem5.opt configs/example/se.py --robsize=64 ……
> 
>  
> 
> Note that if your option includes dash “-”, it will be converted into 
> underscore “_”. For example, “--rob-size” produces representative 
> “options.rob_size”.
> 
>  
> 
> Also, it is pretty helpful if you look at the Options.py to see how the 
> default options are added into the system. The file is in configs/common/.
> 
>  
> 
> -Tao
> 
>  
> 
>  
> 
> From: gem5-users-boun...@gem5.org [mailto:gem5-users-boun...@gem5.org] On 
> Behalf Of Mahshid Sedghi
> Sent: Tuesday, July 16, 2013 4:35 PM
> To: gem5 users mailing list
> Subject: [gem5-users] (no subject)
> 
>  
> 
> Hello,
> 
>  
> 
> I want to introduce a new option to the simulation script to define the ROB 
> size, since I am doing experiments with different ROB sizes and would like to 
> skip the procedure of rebuilding the gem5 again and again for different ROB 
> sizes. Basically, I need to do a similar thing as the thread below:
> 
>  
> 
> http://www.mail-archive.com/gem5-users@gem5.org/msg00480.html
> 
>  
> 
> I am not still sure how to relate the option with the cpu parameters. I'd 
> appreciate it if someone can give me some hints.
> 
>  
> 
> Thanks,
> 
> Mahshid
> 
> 
> ___
> gem5-users mailing list
> gem5-users@gem5.org
> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
> 
> ___
> gem5-users mailing list
> gem5-users@gem5.org
> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] (no subject)

[Amin Farmahini]

The last thing that Tao forgot to mention is to use options.robsize to set
the value of numROBEntries (numROBEntries is defined in
src/cpu/o3/O3CPU.py).

Amin


On Tue, Jul 16, 2013 at 5:06 PM, Tao Zhang  wrote:

> Hi Mahshid,
>
> ** **
>
> You can use the “add_option” to add any desired options in the command
> line. To do this, you just add the line below (or something like it) at the
> beginning of your fs.py. 
>
> ** **
>
> parser.add_option("-rob", "--robsize", type="int", default=128,
> help=”specify the rob size”);
>
> ** **
>
> Then, after all options (including the default options and personalized
> options) have been parsed (in other words, the variable ‘options’ is
> initialized), you can simply leverage the option below.
>
> ** **
>
> options.robsize
>
> ** **
>
> After this, you can use the option in the command line, like
>
> ** **
>
> gem5.opt configs/example/se.py --robsize=64 ……
>
> ** **
>
> Note that if your option includes dash “-”, it will be converted into
> underscore “_”. For example, “--rob-size” produces representative
> “options.rob_size”. 
>
> ** **
>
> Also, it is pretty helpful if you look at the Options.py to see how the
> default options are added into the system. The file is in configs/common/.
> 
>
> ** **
>
> -Tao
>
> ** **
>
> ** **
>
> *From:* gem5-users-boun...@gem5.org [mailto:gem5-users-boun...@gem5.org] *On
> Behalf Of *Mahshid Sedghi
> *Sent:* Tuesday, July 16, 2013 4:35 PM
> *To:* gem5 users mailing list
> *Subject:* [gem5-users] (no subject)
>
> ** **
>
> Hello,
>
> ** **
>
> I want to introduce a new option to the simulation script to define the
> ROB size, since I am doing experiments with different ROB sizes and would
> like to skip the procedure of rebuilding the gem5 again and again for
> different ROB sizes. Basically, I need to do a similar thing as the thread
> below:
>
> ** **
>
> http://www.mail-archive.com/gem5-users@gem5.org/msg00480.html
>
> ** **
>
> I am not still sure how to relate the option with the cpu parameters. I'd
> appreciate it if someone can give me some hints.
>
> ** **
>
> Thanks,
>
> Mahshid
>
> ___
> gem5-users mailing list
> gem5-users@gem5.org
> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
>
___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] (no subject)

[Tao Zhang]

Hi Mahshid,

 

You can use the "add_option" to add any desired options in the command line.
To do this, you just add the line below (or something like it) at the
beginning of your fs.py. 

 

parser.add_option("-rob", "--robsize", type="int", default=128,
help="specify the rob size");

 

Then, after all options (including the default options and personalized
options) have been parsed (in other words, the variable 'options' is
initialized), you can simply leverage the option below.

 

options.robsize

 

After this, you can use the option in the command line, like

 

gem5.opt configs/example/se.py --robsize=64 ..

 

Note that if your option includes dash "-", it will be converted into
underscore "_". For example, "--rob-size" produces representative
"options.rob_size". 

 

Also, it is pretty helpful if you look at the Options.py to see how the
default options are added into the system. The file is in configs/common/.

 

-Tao

 

 

From: gem5-users-boun...@gem5.org [mailto:gem5-users-boun...@gem5.org] On
Behalf Of Mahshid Sedghi
Sent: Tuesday, July 16, 2013 4:35 PM
To: gem5 users mailing list
Subject: [gem5-users] (no subject)

 

Hello,

 

I want to introduce a new option to the simulation script to define the ROB
size, since I am doing experiments with different ROB sizes and would like
to skip the procedure of rebuilding the gem5 again and again for different
ROB sizes. Basically, I need to do a similar thing as the thread below:

 

http://www.mail-archive.com/gem5-users@gem5.org/msg00480.html

 

I am not still sure how to relate the option with the cpu parameters. I'd
appreciate it if someone can give me some hints.

 

Thanks,

Mahshid

___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

[gem5-users] (no subject)

[Mahshid Sedghi]

Hello,

I want to introduce a new option to the simulation script to define the ROB
size, since I am doing experiments with different ROB sizes and would like
to skip the procedure of rebuilding the gem5 again and again for different
ROB sizes. Basically, I need to do a similar thing as the thread below:

http://www.mail-archive.com/gem5-users@gem5.org/msg00480.html

I am not still sure how to relate the option with the cpu parameters. I'd
appreciate it if someone can give me some hints.

Thanks,
Mahshid
___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

[gem5-users] (no subject)

[Yanqi Zhou]

Hi everyone,
Some of the PARSEC benchmarks end with error:
build/ALPHA/sim/eventq.cc:63: virtual Event::~Event(): Assertion `!scheduled()' 
failed.
181 Program aborted at cycle 242845445
182 /var/spool/PBS/mom_priv/jobs/1185438.della-pbs.SC: line 10: 10507 Aborted

I followed the instruction from UT-Austin, used a pre-compiled ALPHA disk 
image, kernel file, and the automatic generated .rcS script.

Can anyone tell me what is happening here?

Thanks,

___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

[gem5-users] (no subject)

[Anthony Gutierrez]

This comment in src/arch/arm/linux/system.cc:

// Task file is read by cache occupancy plotting script or
// Streamline conversion script.

Suggests that there are some scripts available for plotting the data in
this file, or converting it to a Streamline compatible format; are these
scripts available anywhere?

Thanks
Anthony Gutierrez
http://web.eecs.umich.edu/~atgutier
___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

[gem5-users] (no subject)

[megha gupta]

Is it possible to have multiple banks in shared L2 cache with variable
size(at-least 2 size)please guide me in identifying which part
of the code needs to be modified.
___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

[gem5-users] (no subject)

[megha gupta]

which part of the codei should modify to implement global
LRU instead of
LRU for a set
___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

[gem5-users] (no subject)

[megha gupta]

which part of the code collects all memory reference 
___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

[gem5-users] (no subject)

[mehmet basaran]

Hi all,

I would like to know the relationship between an application binary and
gem5 in FS mode. Is the binary directly fed to kernel? While running the
binary file, can I still access information about threads through gem5? Or
once run in fs mode gem5 can only provide trace of CPUs (about interaction
between hardware) rather than application specific info?

Any insight, pointers, links about this are welcome as always (Questions
too).

Regards
Mehmet
___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

[gem5-users] (no subject)

[Liulin Zhong]

Hi All,

I met a problem.
I need some extra memory accesses, so I allocate the missbuffer in the
timingAccess(), but this is done without any change in the time. So the
memory is handling the requests very slow, so the mshr which buffers the
resquests soon gets full.
I think a way to solve this is by blocking the requests, if the mshr queue
is full, I will keep the time moving until the mshr queue is full. But
since the time model here is an discrete event queue, is there an easy way
to do this?


Thanks a lot!
Sarah
___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

[gem5-users] (no subject)

[SHARAN MORA (RIT Student)]

Hi,
I am using ALPHA build_opt.

Am I using MI_example protocol or MOESI snooping protocol (as I am using
Classic memory system, evident from "makeLinuxAlphaSystem" in FSConfig.py)
Thanks,
___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

[gem5-users] (no subject)

[SHARAN MORA (RIT Student)]

Hi,
I am not able to build gem5 with python 2.4.3 and swig 2.0.7, even though
dependencies show
python :  version 2.4 - 2.7
swig : version 1.3.34 or newer

I was able to successfully able to build it on my laptop with python
version 2.7.3, swig  2.0.4. I want to run on my lab system with centos 5. I
am getting python scope error.

scons: Reading SConscript files ...
Warning: Protocol buffer compiler (protoc) not found.
 Please install protobuf-compiler for tracing support.
Checking for leading underscore in global variables...(cached) no
Checking for C header file Python.h... (cached) yes
Checking for C library pthread... (cached) yes
Checking for C library dl... (cached) yes
Checking for C library util... (cached) yes
Checking for C library m... (cached) yes
Checking for C library python2.4... (cached) yes
Checking for accept(0,0,0) in C++ library None... (cached) yes
Checking for zlibVersion() in C++ library z... (cached) yes
Checking for clock_nanosleep(0,0,NULL,NULL) in C library None... (cached) no
Checking for clock_nanosleep(0,0,NULL,NULL) in C library rt... (cached) yes
Checking for C library tcmalloc_minimal... (cached) no
You can get a 12% performance improvement by installing tcmalloc
(libgoogle-perftools-dev package on Ubuntu or RedHat).
Checking for C header file fenv.h... (cached) yes
Reading SConsopts
Building in /research-storage/users/sxm5916/gem5/build/ALPHA
Using saved variables file
/research-storage/users/sxm5916/gem5/build/variables/ALPHA
scons: done reading SConscript files.
scons: Building targets ...
 [ CXX] ALPHA/sim/main.cc -> .o
 [ CXX] ALPHA/python/swig/pyevent.cc -> .o
 [ CXX] ALPHA/python/swig/pyobject.cc -> .o
 [ CXX] ALPHA/python/swig/core_wrap.cc -> .o
build/ALPHA/python/swig/core_wrap.cc:917: warning: 'long int
PyNumber_AsSsize_t(PyObject*, void*)' defined but not used
 [ CXX] ALPHA/python/swig/debug_wrap.cc -> .o
build/ALPHA/python/swig/debug_wrap.cc:917: warning: 'long int
PyNumber_AsSsize_t(PyObject*, void*)' defined but not used
 [ CXX] ALPHA/python/swig/drain_wrap.cc -> .o
build/ALPHA/python/swig/drain_wrap.cc: In function 'PyObject*
SWIG_From_unsigned_SS_int(unsigned int)':
build/ALPHA/python/swig/drain_wrap.cc:3068: error: 'PyInt_FromSize_t' was
not declared in this scope
build/ALPHA/python/swig/drain_wrap.cc: At global scope:
build/ALPHA/python/swig/drain_wrap.cc:917: warning: 'long int
PyNumber_AsSsize_t(PyObject*, void*)' defined but not used
scons: *** [build/ALPHA/python/swig/drain_wrap.o] Error 1
scons: building terminated because of errors.
___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] (no subject)

[Andreas Hansson]

If you do the export in a shell it will only apply to that process. If you 
want, you can also have a "gem5_env" or similar that you source every time you 
do gem5 work. Lastly, you can add the CXX=g++44 and CC=gcc44 on the command 
line.

Hope that helps.

Andreas

From: "SHARAN MORA (RIT Student)" mailto:sxm5...@rit.edu>>
Reply-To: gem5 users mailing list 
mailto:gem5-users@gem5.org>>
Date: Sunday, 27 January 2013 14:46
To: gem5 users mailing list mailto:gem5-users@gem5.org>>
Subject: Re: [gem5-users] (no subject)

I want to specify gem5 which g++ compiler to use (in this case g++44), not 
change default compiler of bash. In which file can I set the compiler path
Thanks


On Sat, Jan 26, 2013 at 9:50 PM, Fangfei Liu 
mailto:fangf...@princeton.edu>> wrote:

Hi, you can add an environment variable CXX. For example, if you use bash, you 
can add a line in your .bashrc file:



export CXX=g++44



Hope it helps.


From: gem5-users-boun...@gem5.org<mailto:gem5-users-boun...@gem5.org> 
[gem5-users-boun...@gem5.org<mailto:gem5-users-boun...@gem5.org>] on behalf of 
SHARAN MORA (RIT Student) [sxm5...@rit.edu<mailto:sxm5...@rit.edu>]
Sent: Saturday, January 26, 2013 9:43 PM
To: gem5-users@gem5.org<mailto:gem5-users@gem5.org>
Subject: [gem5-users] (no subject)

Hi Everyone,
How do I set gem5 to use g++44 compiler instead of g++ compiler. I cannot 
directly upgrade my gcc version 4.1.2 as I use Centos 5.
Thanks,

___
gem5-users mailing list
gem5-users@gem5.org<mailto:gem5-users@gem5.org>
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users


-- IMPORTANT NOTICE: The contents of this email and any attachments are 
confidential and may also be privileged. If you are not the intended recipient, 
please notify the sender immediately and do not disclose the contents to any 
other person, use it for any purpose, or store or copy the information in any 
medium. Thank you.___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] (no subject)

[SHARAN MORA (RIT Student)]

I want to specify gem5 which g++ compiler to use (in this case g++44), not
change default compiler of bash. In which file can I set the compiler path
Thanks


On Sat, Jan 26, 2013 at 9:50 PM, Fangfei Liu  wrote:

>  Hi, you can add an environment variable CXX. For example, if you use
> bash, you can add a line in your .bashrc file:
>
>
>
> export CXX=g++44
>
>
>
> Hope it helps.
>  --
> *From:* gem5-users-boun...@gem5.org [gem5-users-boun...@gem5.org] on
> behalf of SHARAN MORA (RIT Student) [sxm5...@rit.edu]
> *Sent:* Saturday, January 26, 2013 9:43 PM
> *To:* gem5-users@gem5.org
> *Subject:* [gem5-users] (no subject)
>
>Hi Everyone,
>  How do I set gem5 to use g++44 compiler instead of g++ compiler. I cannot
> directly upgrade my gcc version 4.1.2 as I use Centos 5.
>  Thanks,
>
> ___
> gem5-users mailing list
> gem5-users@gem5.org
> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
>
___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] (no subject)

[Fangfei Liu]

Hi, you can add an environment variable CXX. For example, if you use bash, you 
can add a line in your .bashrc file:



export CXX=g++44



Hope it helps.


From: gem5-users-boun...@gem5.org [gem5-users-boun...@gem5.org] on behalf of 
SHARAN MORA (RIT Student) [sxm5...@rit.edu]
Sent: Saturday, January 26, 2013 9:43 PM
To: gem5-users@gem5.org
Subject: [gem5-users] (no subject)

Hi Everyone,
How do I set gem5 to use g++44 compiler instead of g++ compiler. I cannot 
directly upgrade my gcc version 4.1.2 as I use Centos 5.
Thanks,
___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

[gem5-users] (no subject)

[SHARAN MORA (RIT Student)]

Hi Everyone,
How do I set gem5 to use g++44 compiler instead of g++ compiler. I cannot
directly upgrade my gcc version 4.1.2 as I use Centos 5.
Thanks,
___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] (no subject)

[Tao Zhang]

this is correct. However, there should be more tag bits for the purpose 
of cache conherence and replacement (e.g., valid, dirty, LRU...)


-Tao

On 11/24/2012 01:23 AM, Nitin Chaturvedi wrote:

Dear sir
srry for wrong interpretation..please check again and correct 
me if i am wrong...


my understanding.
If..physical address space 1GB.size of 
physical address 30-bits...

Now,
1. if size of on chip L2 cache is 4MB
2. block size.64byte
3. 16 banks and 16 way set associative

then physical address interpretation will be as follows

-12bits for Tag8bits for 
index---4bits to select 
bank--6 bits for block offset



sir, please correct me if i am wrong..
 thanks

On Sat, Nov 24, 2012 at 11:28 AM, megha gupta > wrote:


my understanding...physical address space
.means on chip L2 cache
1. if size of on chip L2 cache is 4MB
2. block size.64byte
3. 16 banks and 16 way set associative

then physical address is of 50 bits and its interpretation will be
as follows

-32bits for Tag8bits for
index---4bits to select
bank--6 bits for block offset


sir, please correct me if i am wrong..




--
Nitin Chaturvedi
Lecturer, EEE/IU
BITS, Pilani (Raj)


___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] (no subject)

[Muhammad abid Mughal]

absolutely right. Another way is:
-12bits for Tag---4bits to select 
bank--8bits for index--6 bits for block offset


your way maps contiguous blocks across different banks of a cache, so this is 
really helpful if processor is reading contiguous data from memory pages.
Mine approach first put all contiguous blocks in one bank then next one and so 
onso may not provide good performance if data is contiguous.






 From: Nitin Chaturvedi 
To: gem5 users mailing list  
Sent: Saturday, 24 November 2012, 11:23
Subject: Re: [gem5-users] (no subject)
 

Dear sir

srry for wrong interpretation..please check again and correct me if i 
am wrong...

my understanding.
If..physical address space 1GB.size of physical 
address 30-bits...
Now,
1. if size of on chip L2 cache is 4MB
2. block size.64byte
3. 16 banks and 16 way set associative 

then physical address interpretation will be as follows

-12bits for Tag8bits for 
index---4bits to select bank--6 bits 
for block offset


sir, please correct me if i am wrong.. thanks


On Sat, Nov 24, 2012 at 11:28 AM, megha gupta  wrote:

my understanding...physical address space .means on 
chip L2 cache
>1. if size of on chip L2 cache is 4MB
>2. block size.64byte
>3. 16 banks and 16 way set associative 
>
>then physical address is of 50 bits and its interpretation will be as follows
>
>-32bits for Tag8bits for 
>index---4bits to select bank--6 bits 
>for block offset
>
>
>sir, please correct me if i am wrong..


-- 
Nitin Chaturvedi
Lecturer, EEE/IU
BITS, Pilani (Raj)

___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] (no subject)

[Nitin Chaturvedi]

Dear sir
srry for wrong interpretation..please check again and correct me if
i am wrong...

my understanding.
If..physical address space 1GB.size of physical
address 30-bits...
Now,
1. if size of on chip L2 cache is 4MB
2. block size.64byte
3. 16 banks and 16 way set associative

then physical address interpretation will be as follows

-12bits for Tag8bits for
index---4bits to select bank--6
bits for block offset


sir, please correct me if i am wrong..
 thanks

On Sat, Nov 24, 2012 at 11:28 AM, megha gupta  wrote:

> my understanding...physical address space .means
> on chip L2 cache
> 1. if size of on chip L2 cache is 4MB
> 2. block size.64byte
> 3. 16 banks and 16 way set associative
>
> then physical address is of 50 bits and its interpretation will be as
> follows
>
> -32bits for Tag8bits for
> index---4bits to select bank--6
> bits for block offset
>
>
> sir, please correct me if i am wrong..
>



-- 
Nitin Chaturvedi
Lecturer, EEE/IU
BITS, Pilani (Raj)
___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

[gem5-users] (no subject)

[Fernando Endo]

Hello all,

I'm in doubt with three parameters inside the file
"mcpat-template.xml" got from https://www.cl.cam.ac.uk/~acr31/sicsa/.
It's Inside the component above:


  
  ...
  
  
  


I found that the first two values need to have "::total" appended, like this:


  
  ...
  
  
  


Then, I thought maybe the l2 cache information is wrong here. I wonder
if I should do like this:


  
  ...
  
  
  


I mean, get the information from physmem. In my stats file, I couldn't
find the num_write one.

Thanks in advance,

-- 
Fernando A. Endo, PhD student and researcher

CEA Lab
and
Université de Grenoble, UJF
France
___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] (no subject)

[Mahesh Jethanandani]

Sunitha,

Have you installed the first software in this list?

http://www.gem5.org/Dependencies#External_tools_and_required_versions

On Jul 9, 2012, at 4:23 AM, sunitha p wrote:

> hi all..
> 
> I am trying to install gem5
>  am facing this error..have installed scons,swig,python..
> 
> kindly help me out
> 
> 
> scons: Reading SConscript files ...
> Error Don't know what compiler options to use for your compiler.
>compiler: None
>version: COMMAND NOT FOUND!
>If you're trying to use a compiler other than GCC, ICC, SunCC,
>or clang, there appears to be something wrong with your
>environment.
>
>If you are trying to use a compiler other than those listed
>above you will need to ease fix SConstruct and 
>src/SConscript to support that compiler.
> 
> -- 
> Thanks & Regards
> 
> Sunitha.P
> 8970314569
> 
> ___
> gem5-users mailing list
> gem5-users@gem5.org
> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Mahesh Jethanandani
mjethanand...@gmail.com



___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

[gem5-users] (no subject)

[sunitha p]

hi all..

I am trying to install gem5
 am facing this error..have installed scons,swig,python..

kindly help me out


scons: Reading SConscript files ...
Error Don't know what compiler options to use for your compiler.
   compiler: None
   version: COMMAND NOT FOUND!
   If you're trying to use a compiler other than GCC, ICC, SunCC,
   or clang, there appears to be something wrong with your
   environment.

   If you are trying to use a compiler other than those listed
   above you will need to ease fix SConstruct and
   src/SConscript to support that compiler.

-- 
Thanks & Regards

Sunitha.P
8970314569
___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] (no subject)

[Meeran Mohideeen]

I checked all the .py files within the src/mem/ruby folder... But i dont
see any flaw in them (upto my knowledege)... I will try checking the cc
files also...

[Thank you for mentioning my mistake... i actually forgot and will see to
it the subject is included always]

On Sat, Feb 18, 2012 at 3:30 AM, Gabriel Michael Black <
gbl...@eecs.umich.edu> wrote:

> You should really put a subject on this so people who would be interested
> will see it when scanning through their mail.
>
> This sounds like a bug in one of the simulation scripts. I vaguely
> remember a recent change where there was a redundant copy of the system
> parameter being used with one of the CPUs (maybe?) and that was taken out
> of the C++. It could be that it was left in some of the python scripts, and
> the now redundant system parameter is colliding with the real one.
>
> Gabe
>
>
> Quoting Meeran Mohideeen :
>
>  Hi...
>>
>> I am trying to run an ALPHA CMP simulation with two cores with ruby memory
>> component When i try to run the simulation using
>> "./build/ALPHA_FS/gem5.opt configs/example/ruby_fs.py -n 2 --l1i_size=16kB
>> --l1d_size=16kB --l2_size=2MB --num-l2caches=1 --topology=Mesh --timing
>> --script=runcsript.rcS"
>>
>> i am getting the following warning.
>>
>> warning: overwriting port .tsunami.ide.dma value
>> .dma_cntrl0.dma_sequencer.port[0] with > LinuxAlphaSystem>.dma_cntrl0.dma_sequencer.port[1]
>> warning: overwriting port .tsunami.ethernet.dma
>> value .dma_cntrl1.dma_sequencer.port[0] with
>> .dma_cntrl1.dma_sequencer.port[1]
>>
>> Also... the simulation is halted with
>>
>> [ srm_env: version 0.0.6 loaded successfully ] (i.e: knfsd
>> installation
>> doesnt begins) > (from m5out/system.term)
>>
>> But when i run the same simulation without ruby component (i.e:
>> ./build/ALPHA/fs.py) the simulation runs fine. Whats wrong with
>> ruby Please help me..
>>
>>
>
> ___
> gem5-users mailing list
> gem5-users@gem5.org
> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
>
___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] (no subject)

[Gabriel Michael Black]

You should really put a subject on this so people who would be  
interested will see it when scanning through their mail.


This sounds like a bug in one of the simulation scripts. I vaguely  
remember a recent change where there was a redundant copy of the  
system parameter being used with one of the CPUs (maybe?) and that was  
taken out of the C++. It could be that it was left in some of the  
python scripts, and the now redundant system parameter is colliding  
with the real one.


Gabe

Quoting Meeran Mohideeen :


Hi...

I am trying to run an ALPHA CMP simulation with two cores with ruby memory
component When i try to run the simulation using
"./build/ALPHA_FS/gem5.opt configs/example/ruby_fs.py -n 2 --l1i_size=16kB
--l1d_size=16kB --l2_size=2MB --num-l2caches=1 --topology=Mesh --timing
--script=runcsript.rcS"

i am getting the following warning.

warning: overwriting port .tsunami.ide.dma value
.dma_cntrl0.dma_sequencer.port[0] with .dma_cntrl0.dma_sequencer.port[1]
warning: overwriting port .tsunami.ethernet.dma
value .dma_cntrl1.dma_sequencer.port[0] with
.dma_cntrl1.dma_sequencer.port[1]

Also... the simulation is halted with

[ srm_env: version 0.0.6 loaded successfully ] (i.e: knfsd installation
doesnt begins) > (from m5out/system.term)

But when i run the same simulation without ruby component (i.e:
./build/ALPHA/fs.py) the simulation runs fine. Whats wrong with
ruby Please help me..




___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

[gem5-users] (no subject)

[Meeran Mohideeen]

Hi...

I am trying to run an ALPHA CMP simulation with two cores with ruby memory
component When i try to run the simulation using
"./build/ALPHA_FS/gem5.opt configs/example/ruby_fs.py -n 2 --l1i_size=16kB
--l1d_size=16kB --l2_size=2MB --num-l2caches=1 --topology=Mesh --timing
--script=runcsript.rcS"

i am getting the following warning.

warning: overwriting port .tsunami.ide.dma value
.dma_cntrl0.dma_sequencer.port[0] with .dma_cntrl0.dma_sequencer.port[1]
warning: overwriting port .tsunami.ethernet.dma
value .dma_cntrl1.dma_sequencer.port[0] with
.dma_cntrl1.dma_sequencer.port[1]

Also... the simulation is halted with

[ srm_env: version 0.0.6 loaded successfully ] (i.e: knfsd installation
doesnt begins) > (from m5out/system.term)

But when i run the same simulation without ruby component (i.e:
./build/ALPHA/fs.py) the simulation runs fine. Whats wrong with
ruby Please help me..
___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

[gem5-users] (no subject)

[jianming yu]

i've come up with some problem when runing gem5.
after the compilation :
it shows scons finished building target
but when i enter the command
it returns such an error:
Traceback(most recent call last):
 File"",line1 , in 
AttributeError:'module'object has no attribute 'main'

i did not manage to locate the error, i hope someone could help me with
that, thanks in advance
___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] (no subject)

[Nilay Vaish]

You may want to take a look at our article in May 2011 issue of ACM 
SIGARCH Computer Architecture News. Here is the link --


http://dx.doi.org/10.1145/2024716.2024718

--
Nilay

On Mon, 12 Dec 2011, sudhanshu jha wrote:


Hello,


Thanks for the response. ?I am looking for some detailed document like a 
full-fledged manual describing the whole simulation model (with block 
diagrams, etc). I hope you understand what i am trying to say. Please let 
me know if there is any document of this kind.


regards,
Sudhanshu.



 From: Nilay Vaish 
To: sudhanshu jha ; gem5 users mailing list  
Sent: Monday, December 12, 2011 12:46 PM

Subject: Re: [gem5-users] (no subject)

Sudhanshu, documentation on gem5 is available on our website www.gem5.org.

--
Nilay


On Mon, 12 Dec 2011, sudhanshu jha wrote:


Hello,


My name is Sudhanshu. I am using gem5 for simulations.?Can you please let me 
know if there is a document that specifies the architecture of gem5, in terms 
of module and its working model (document of detailed software architecture of 
gem5 and its work flow)? I need to understand the work-flow of gem5 to make 
changes to the model to support heterogeneous architectural parameters like 
frequency, cache size, etc instead of SMP model.

Can you please send me a copy of this document at your earliest?

Thanks in advance.

regards,
Sudhanshu.___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] (no subject)

[sudhanshu jha]

Hello,

Thanks for the response.  I am looking for some detailed document like a 
full-fledged manual describing the whole simulation model (with block diagrams, 
etc). I hope you understand what i am trying to say. Please let me know if 
there is any document of this kind.

regards,
Sudhanshu.



 From: Nilay Vaish 
To: sudhanshu jha ; gem5 users mailing list 
 
Sent: Monday, December 12, 2011 12:46 PM
Subject: Re: [gem5-users] (no subject)
 
Sudhanshu, documentation on gem5 is available on our website www.gem5.org.

--
Nilay


On Mon, 12 Dec 2011, sudhanshu jha wrote:

> Hello,

My name is Sudhanshu. I am using gem5 for simulations. Can you please let me 
know if there is a document that specifies the architecture of gem5, in terms 
of module and its working model (document of detailed software architecture of 
gem5 and its work flow)? I need to understand the work-flow of gem5 to make 
changes to the model to support heterogeneous architectural parameters like 
frequency, cache size, etc instead of SMP model.

Can you please send me a copy of this document at your earliest?

Thanks in advance.

regards,
Sudhanshu.___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] (no subject)

[Nilay Vaish]

Sudhanshu, documentation on gem5 is available on our website www.gem5.org.

--
Nilay


On Mon, 12 Dec 2011, sudhanshu jha wrote:


Hello,


My name is Sudhanshu. I am using gem5 for simulations.?Can you please let 
me know if there is a document that specifies the architecture of gem5, in 
terms of module and its working model (document of detailed software 
architecture of gem5 and its work flow)? I need to understand the 
work-flow of gem5 to make changes to the model to support heterogeneous 
architectural parameters like frequency, cache size, etc instead of SMP 
model.


Can you please send me a copy of this document at your earliest?

Thanks in advance.

regards,
Sudhanshu.___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

[gem5-users] (no subject)

[sudhanshu jha]

Hello,

My name is Sudhanshu. I am using gem5 for simulations. Can you please let me 
know if there is a document that specifies the architecture of gem5, in terms 
of module and its working model (document of detailed software architecture of 
gem5 and its work flow)? I need to understand the work-flow of gem5 to make 
changes to the model to support heterogeneous architectural parameters like 
frequency, cache size, etc instead of SMP model.

Can you please send me a copy of this document at your earliest?

Thanks in advance.

regards,
Sudhanshu.___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

[gem5-users] (no subject)

[Dibakar Gope]

Hi, I have a general question in running multiple threads in multicore
environment. In M5 simulation, if a core is assigned with multiple
threads, does that core executes the threads one after another or the
core uses some kind of round-robin policy/time-multiplexed way?
Thanks,
Dibakar Gope

Texas A&M University

___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users