Hi Gabe,
Any thoughts on the below?
Thanks,
Shyam
> On Apr 13, 2019, at 10:21 PM, Shyam Murthy wrote:
>
> Hi Gabe,
>
> One additional question, regarding another instruction I was trying to
> implement (FCMOVNBE).
> I thought of emulating a sequence similar what we have for CMOVNBE.
> def
Hi Gabe,
One additional question, regarding another instruction I was trying to
implement (FCMOVNBE).
I thought of emulating a sequence similar what we have for CMOVNBE.
def macroop CMOVNBE_R_R
{
mov reg, reg, reg, flags=(CCvZF,)
Hi Gabe,
Thanks for the help with the FRNDINT instruction.
I was trying to implement another instruction, namely *FISTP. *This was my
initial implementation
def macroop FISTP {
cvtf_d2i t1, st(0)
movfp *st(0)*, t1
pop87
};
But I think the instruction writes to a destination, I was
Hi Gabe,
I wrote this implementation for the frndint macroop:
*def macroop FRNDINT {cvtf_d2i st(0), st(0)};*
However, when I run the application using this instruction on gem5, I seem
to get this error:* gem5.opt: build/X86/cpu/simple_thread.hh:251: RegVal
SimpleThread::readIntReg(int):
Thanks a lot for the clarification Gabe.
Thanks,
Shyam
On Sun, Mar 31, 2019 at 6:29 AM Gabe Black wrote:
> Hi Shyam. There are float to integer and integer to float conversion
> microops in src/arch/x86/isa/microops/fpop.isa which start with cvt_* which
> is short for convert. You can
Apologize for the wrong title in my previous email. Correcting.
Thanks,
Shyam
On Fri, Mar 29, 2019 at 6:16 PM Shyam Murthy
wrote:
> Hi Gabe,
>
> As I am trying to run SPEC 2017 on gem5 in SE mode, I ran into some
> unimplemented instructions namely *frndint*, *fsqrt* and *fistp* to name
> a
