Re: [gem5-users] Implementing tag-less cache architecture only for the last level cache
Hi jason, Apologies for a naive understanding of your tutorial, I just thought the cache that you designed can be the design of tag-less caches, since there were no tags used in your implementation. Apparently, I'm understanding is completely wrong. I need a tagless architecture for the cache to facilitate my project. The problem that I'm facing is that, I could not comprehend the existing source code of the cache to design a new cache architecture. Can you possibly, guide me to a particular aspect of the existing design that I may need to change, to start with?? Anything that could help me understand the caches in gem5?? Thank you Varun. ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] Implementing tag-less cache architecture only for the last level cache
Hi Varun, The SimpleCache is just a starting point. It isn't at all a realistic model! It's an example to show you how to use gem5 ports. It will not be able to handle most realistic situations (e.g., being used as anything other than a single core L1 cache). You can take this code as a starting point to understand how gem5 works. You will have to develop your own C++ model from scratch to model new kinds of architectural widgets. Jason On Wed, Dec 13, 2017 at 10:41 PM Saivarun R wrote: > Hi Jason, > > I went through the tutorial and understood quite a bit of it. What I > understood is that, there is no usage of tags in the implementation, just > an unordered map. So I thought with some changes in the latencies, I can > create a tagless blocking cache. Is this a correct starting point in > implementing tagless cache? or is there some thing more to it?? > > In order to try the idea out, I just changed the vector ports of the > SimpleCache and tried to plug it as a second-level cache. The simulation > stopped because of this reason, Exiting @ tick 18446744073709551615 because > simulate() limit reached. > > To check out the I also used the simple cache, as it is, as a second-level > cache in http://learning.gem5.org/book/part1/cache_config.html. And when > I ran the simulation, this is what I encountered, > info: Entering event queue @ 0. Starting simulation... > panic: Unknown packet type! > @ tick 934 > [accessFunctional:build/X86/learning_gem5/simple_cache.cc, line 358] > Memory Usage: 655584 KBytes > Program aborted at tick 934 > > Kindly help me in this regard. Sorry for this long mail. > > Thank you > Varun > ___ > gem5-users mailing list > gem5-users@gem5.org > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] Implementing tag-less cache architecture only for the last level cache
Hi Jason, I went through the tutorial and understood quite a bit of it. What I understood is that, there is no usage of tags in the implementation, just an unordered map. So I thought with some changes in the latencies, I can create a tagless blocking cache. Is this a correct starting point in implementing tagless cache? or is there some thing more to it?? In order to try the idea out, I just changed the vector ports of the SimpleCache and tried to plug it as a second-level cache. The simulation stopped because of this reason, Exiting @ tick 18446744073709551615 because simulate() limit reached. To check out the I also used the simple cache, as it is, as a second-level cache in http://learning.gem5.org/book/part1/cache_config.html. And when I ran the simulation, this is what I encountered, info: Entering event queue @ 0. Starting simulation... panic: Unknown packet type! @ tick 934 [accessFunctional:build/X86/learning_gem5/simple_cache.cc, line 358] Memory Usage: 655584 KBytes Program aborted at tick 934 Kindly help me in this regard. Sorry for this long mail. Thank you Varun ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] Implementing tag-less cache architecture only for the last level cache
Hi Jason, So I should understand how to create new objects in the simulator and try to create a new object for tag-less cache. I will go through the book and see if I get any leads in this regard. I will update on this in a week. Thank you. Regards Varun ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] Implementing tag-less cache architecture only for the last level cache
Hi Varun, You might want to check out http://learning.gem5.org/book/part2/. This walks you through how to create new objects in gem5 and culminates in a simple cache model (that you may be able to build off of). Additionally, you can check out the code in the gem5 source that was just committed (see src/learning_gem5/part2). Cheers, Jason --- Jason Lowe-Power Assistant Professor, Computer Science Department University of California, Davis 3049 Kemper Hall https://faculty.engineering.ucdavis.edu/lowepower/ On Wed, Dec 6, 2017 at 12:40 AM Saivarun R wrote: > > Hi Cho, > Thank you for replying. > > The cache implementation is too huge and confusing when trying to > understand its implementation. I didn't still understand it completely. Any > specific pointers, or methods, to look at while I try to change the > implementation??? > > Any idea which other files or classes do I need to look at, in order to > achieve the tag-less architecture?? > > Thank you > Varun > ___ > gem5-users mailing list > gem5-users@gem5.org > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] Implementing tag-less cache architecture only for the last level cache
Hi Cho, Thank you for replying. The cache implementation is too huge and confusing when trying to understand its implementation. I didn't still understand it completely. Any specific pointers, or methods, to look at while I try to change the implementation??? Any idea which other files or classes do I need to look at, in order to achieve the tag-less architecture?? Thank you Varun ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] Implementing tag-less cache architecture only for the last level cache
Dear, Varun. In my opinion, you can make new class which inherit BaseCache or MemObject. As I think, if you implement tag-less cache in conventional cache class, you need to a flag which indicate tag-less cache and many conditional sentence everywhere operate differently with a conventional cache. It may be also less readable code. But if you make new class, you can write the code for tag-less cache totally. Make a new class and copy the code of the conventional cache. If you inherit MemObject, copy BaseCache code also. After copy them, modify for tag-less cache. Cheers, Haeyoon Cho. 2017-12-06 16:27 GMT+09:00 Saivarun R : > Hi, > > I'm trying to implement a tag-less cache architecture only for the last > level cache. As I understand, there is only one implementation for all > levels of caches. How do I change only the implementation for the last > level cache, leaving other caches being accessed in a conventional manner. > > Any help is deeply appreciated :-) > > Thank you in advance > Varun > > ___ > gem5-users mailing list > gem5-users@gem5.org > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
[gem5-users] Implementing tag-less cache architecture only for the last level cache
Hi, I'm trying to implement a tag-less cache architecture only for the last level cache. As I understand, there is only one implementation for all levels of caches. How do I change only the implementation for the last level cache, leaving other caches being accessed in a conventional manner. Any help is deeply appreciated :-) Thank you in advance Varun ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
