I think the map function has a parameter for "cacheable". From
src/sim/Process.py:
@classmethod
def export_methods(cls, code):
code('bool map(Addr vaddr, Addr paddr, int size, bool
cacheable=true);')
Cheers,
Jason
On Mon, Jan 30, 2017 at 6:44 PM Lorenzo Zuolo wrote:
> Hi Jason,
Hi Lorenzo,
If the access flows through the cache, the cache might be creating an MSHR
and upgrading the packet to a full cache line. You may need to somehow
update the page table entry to make that region as uncachable. I believe
there is a field in either the packet or the request that is set wh
Hi Jason,
thank you again for the help.
Finally I got it. Basically, I've modified the Simulation.py script and
I've added the map function right before the "*** REAL SIMULATION***" print.
I did that because I've realized that I was trying to use a method of the
LiveProcess class when the class it
Hi Lorenzo,
This error means you're trying to access a member of a SimObject from the
Python configuration script that isn't exposed. If you're trying to add a
new member, then you can use an '_' prefix (IIRC). But this new member will
only be accessible from the Python config script, not the C++
Hi Jason,
Sorry for the late replay.
Thank you for your hint. I've used the "map" method exposed by the
LiveProcess class to make my address range not cacheable, however when I
run the se.py script I have this error:
"(C++ object is not yet constructed, so wrapped C++ methods are
unavailable.)"
A
Hi Lorenzo,
Are you trying to use [0x1-0xF] as PIO? If so, this example might
help you figure out how to do what you want.
https://github.com/powerjg/gem5/commit/86394e326cede3be7b26eb728dd6a9a0a93406bf
It's for x86, but it contains an example of how to use PIO in SE mode to
communicate f
Hey Lorenzo,
Just to see if I understand your question, you want to have uncacheable
address range 0x1-0xF in physical memory and not virtual memory?
I hope you realize that accesses to physical memory not actually mapped to
DRAM is only allowed for devices. I am guessing that you don't j
Hi everybody,
I have a very stupid question.
I'm new in gem5 and I would like to understand how to make an address
region uncacheable with ARM architecture in se mode.
Problem is. I would like to have the possibility to access an address
outside the dram range from a c program I'm executing in SE
