Nate, you mentioned that the symbols are used for debugging. Are you talking
about debugging the kernel itself or debugging m5?
Both. Though, for remote debugging, gdb uses the kernel image to get
the symbols. On the m5 side, the symbols can be used for execution
tracing. Also, I forgot to
Are you trying to say that the kernel image that is provided is parsed by
some code and the symbols are collected?
That is correct. I believe that it's all part of the loader code in
src/base/loader.
Nate
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Why are the kernel symbols stored in the m5 checkpoints?
Because the kernel is saved in the checkpoint memory. We could just
extract the symbols from the provided binary a second time, but it
just seemed safer this way. Also, I believe that symbols can be
dynamically added to the system at
I've wondered about this too, and assumed it was so you didn't need to
provide the kernel binary when restarting from a checkpoint. It does seem
like a lot of state to save.
Compared to memory?
Does this really happen? And if it does, we could just save the dynamically
added symbols.
I
This sounds strange to me. How in first place were the symbols figured out
if they cannot be recovered from a memory image?
They come from the kernel image.
Nate
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Call for Participation: ISCA 2011 Tutorial
gem5: A Multiple-ISA Full System Simulator with Detailed Memory Modeling
Sunday, June 5, 2011
http://www.gem5.org
The gem5 simulator is a merger of two of the computer architecture
community’s most popular, open source simulators: M5 and GEMS. The
best
Hi, I need to modify this wrent to allow more exception entries. But in the
M5 source code, I could not find its implementation. I just found that in
osfpal.hh it is defined as 0x34, but no implementation code found. Can
someone tell me how does this instruction be implemented? Thanks.
The
Navid,
Did you figure this out? My guess is that you did not explicitly
instantiate your functions in your .cc file. Look at the template
class statements in the various .cc files of the o3 directory.
Nate
On Mon, Apr 4, 2011 at 5:11 PM, Navid Farazmand navid@gmail.com wrote:
I have a
Does TLS or TM support available in M5? If yes, how could it be used. If no,
whether any body working on it?
People have worked on this in the past, but nothing has ever been
contributed back into the tree. I know that Geoff Blake at UMich did
some work a while ago, but it is likely to be
When report stats, M5 uses cycle as units. It seems to me the reported
cycle is the real cycle determined by the core clock rate, not the
internal tick, right? What should I do if I need to model a processor with
different clock domains? For example, the core is running at 2Ghz, while
the
This is a long shot, but I'm having a terrible time trying to get an old
revision of the M5 to run. I have been using an old copy of the /hg/m5
repo, changeset 5589 (October 2008), because I have patches that don't work
with newer revisions of the repo, and they would take a bunch of
i read about automatic graph generation in m5, i read the python
files inside util/stats .could someone please tell me how to use it?
It's all pretty hackish and undocumented. It is too difficult to
support in its current state.
Nate
___
Just to let everyone know (if you didn't read my commit message), I
renamed the style hook function from check_whitespace to check_style.
I also made the style hook work with pre-qrefresh. This means that
you'll have to edit your .hgrc. You should make the hooks part look
like this:
[hooks]
Tim,
I've got a simple Barrelfish system now running. It gets as far as booting 1
core, starting various system processes on them, and running a user-mode test
app. My current changes are a mess -- both the changes to m5 and to
Barrelfish -- so I'll need to go back and do it properly,
Is there someone who tries to configure M5 to be a heterogeneous multi-core
platform(e.g. a alpha core runs 500MHz and another alpha core runs 1GHz ). I
want to build this platform on M5. But I am not quite sure if that is OK on
M5.
Yes, this works fine. There are some calibrated delays in
with referring the Problem with booting linux kernel 2.6.27 on M5
simulator , I run it on Alpha Full System Simulation mode.
After I google around with this problem ,finally I able to find the solution
,, I apply the patch given from the M5 repo using hg
The line CONFIG_BIG_TSUNAMI should be
As I mentioned before, I expect that setting func to anything other than 0
will effectively hide your device from Linux. If Linux doesn't see it it
won't try to configure it and M5 won't crash, but it also isn't very useful.
Why is that? Linux itself certainly supports multiple functions, is
I'm surely not the only one that has found scons builds to be slow, have
they always been slow. M5 is a reasonably sized body of code, but it is by
no means a behemoth, and from experience I have seen faster builds on much
bigger projects. A colleague also suffering the same problem of waiting
I'm using the tracing facilities to collect a trace, in this case of cache
accesses, to feed to cache simulators. It's useful if I don't need timing
information but do want to try various cache configurations to see hit
rates. So printing everything from the caches really slows down
Did you accidentally delete the AUTHORS file? It should be in the
root of the m5 directory.
Nate
Anyone know how to fix this:
as -o build/ALPHA_FS/python/m5/event.py.o
build/ALPHA_FS/python/m5/event.py.s
scons: *** [build/ALPHA_FS/python/m5/info.py] Source `AUTHORS' not found,
needed by
Yes, Thanks for your reply!
Is there any method that I could figure out this problem? Or Need I use an
old version such as M5.b5? Thank you very much!
From looking at the version of mybench.py on the wiki, I'm not sure
how this worked in the first place since it has no import lines at
all.
I'm Ong Wen Jian, undergraduate student from Malaysia and I'm currently
modeling a GPU to hook into M5 simulator. I have some problem in understand
the interfacing of my GPU model with M5 simulator and I'm modeling a PCI
based GPU.
The problem that I face now is, from the tutorial, it is
What version of M5 are you using? bigint.hh includes base/types.hh
which includes inttypes.hh which defines uint64_t, so you could try to
find out if something is wrong there.
Nate
On Fri, Aug 27, 2010 at 8:45 AM, Sudhanshu(Duke) genius.d...@gmail.com wrote:
Hi,
I tried to build using scons
I want to save the current statistics to the stats.txt file every x cycles.
I managed that this is done in a way that the new values are attached to the
stats.txt file, meaning that every x cycles a new passage beginning with
-- Begin Simulation Statistics -- and ending with
may i know Where can i get the information i need regarding m5elements?
As Gabe said, you should contact the authors of m5elements (the Trimaran people)
Nate
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I don't think InOrder supports FS in any ISA.
Nate
On Tue, Jul 20, 2010 at 11:21 AM, Malek Musleh malek.mus...@gmail.com wrote:
Hello,
Is the InorderCPU Model not fully supported for Full System Simulation
on the ALPHA ISA?
At first I was getting the error that the InorderCPU TmpClass
I am working on some timing attack problems. I was wondering whether it is
possible to use m5 in SE mode to do a pseudo switch of contexts: to execute
a workload, then (using the current processor state including caches, bpreds
etc) switch to another one - to simulate a regular and an attacker
This is a python int which is unbounded. The Tick type in C++ is a
64-bit integer. So, yes it can overflow, but not easily.
I just noticed that the maxtick in configs/common/Options.py (also
configs/splash2/run.py) was defined as:
parser.add_option(-m, --maxtick, type=int)
Is the type int
I’m trying to implement frequency scaling that happens at runtime, but I am
running into a problem with Full System. The kernel is reporting “soft
lockups” being detected. I am guessing that this is related to the timer
interrupts not scaling when I increase the cpu frequency (I am using
Which version of M5?
On Tue, Jul 6, 2010 at 10:45 PM, Michael Moeng mo...@cs.pitt.edu wrote:
I downloaded m5 again today, and tried compiling with gcc-3.4.6, I still get
the same error.
g++ -o build/ALPHA_FS/dev/i8254xGBe.o -c -Wno-deprecated -pipe
-fno-strict-aliasing -Wall
I had an error about 'converting of negative value' when trying to build for
full system simulation. From this post:
http://www.mail-archive.com/m5-users@m5sim.org/msg03300.html, it seemed that
upgrading gcc to 4.* would fix the issue.
Can you try the latest version of m5-dev? I'm pretty
I am trying to build M5 using boost libraries. Unfortunately, the machine I
am stuck using already has boost built using an older version of gcc (3.4),
I installed an updated version of boost in a custom location and added it to
library and include paths. I cannot use the older version of
Hi Tim,
This looks right to me. Assuming that it is working for you, can you
please push this patch?
Thanks,
Nate
On Tue, Jun 22, 2010 at 7:07 AM, Timothy M Jones tjon...@inf.ed.ac.uk wrote:
I think the #ifdef is set up wrongly here. I'm in the process of making
some changes and came
In the case of a multi-core system as you said, the second bin (linked
list) would potentially have more than a single event to be set for
execution at a particular cycle, and although the current structural
order implementation for execution is set for LIFO, there is no
guarantee as to the
v1.1 is nearly 5 years old. Please use a more recent version. So
many things have been fixed since then that it's not even worth
answering questions about 1.1.
Nate
On Wed, Jun 2, 2010 at 2:23 AM, Qingyuan Deng ddq...@gmail.com wrote:
Thanks Korey, does that work on v1.1? I put
My current understanding of the simulator's event queue, is that there
is currently only one main Event Queue in which all the corresponding
simobjects place their scheduled events into this single queue.
This is correct.
This is as opposed to having each SimObject have their own
I compiled and run M5 successfully with the given example scripts. However,
the directory src/python/m5/objects which is said to contain class
definitions and parameters is missing. I cannot find it in the tarball
neither. Is it generated during compilation? If yes, how can I generated it?
There is also a gettid system call, so you can look for that and see
how it gets the tid.
Nate
On Wed, May 26, 2010 at 1:08 PM, Ali Saidi sa...@umich.edu wrote:
There is some way. I don't know how to get the tid, but you should be able to
get a unique value for them by checking the kernel
Thanks Nate. Correct me if I'm wrong: in file
m5-stable/build/ALPHA_SE/python/m5/objects/__init__.py, all the imports
will include the corresponding .py files for each components from src/
directory, and those .py files are the source where I can learn about all
the available classes and
Ah, yes, I figured this out. I simply updated my version of gcc to
4.4.0. Not sure if that was the best solution, but it works for the
moment.
The documentation states that M5 should work with gcc 3.4.6. Is this
still true?
I'm not sure. I imagine that most of us are probably using 4.x
That's probably that your read was to an address, 0xF00188, that wasn't
claimed by any memory, device, etc. That address may fall into a range with
a special purpose in Alpha, but I don't really know.
This is a special purpose address, though I can't quite remember what
it is. I vaguely
We compiled our code using Crosscompiler available on the m5sim website and
then built it into the linux-image.
Are we missing something here??
It's hard to know what's going on. You haven't given us much data.
Send us your changes to M5, send us the error messages on the
terminal. Send us
What version of M5 is this? It must be pretty old because M5
definitely builds on 9.10.
Nate
2010/5/3 徐敏超 xu.minc...@stu.xjtu.edu.cn:
Hi everyone
I tried to build the M5. It gave following compilation error in ubuntu
9.10 64 bit machine. Could you please let me know how to fix it.
This version of M5 is pretty old. Can you either download the stable
version (or even better, the dev version)
Nate
2010/4/22 徐敏超 xu.minc...@stu.xjtu.edu.cn:
hi,everyone
I am trying to compile m5 in ubuntu . I am getting the following error:
x...@xmc:~/桌面/m5-2.0b5$ scons
I'm a new M5 user. I've read that some people have been working on the
integration of M5 and McPAT.
The README file of McPAT says that Richard Strong is working on a parser for
M5, and that its latest version is available on the repository, but I
couldn't find it.
I'd like to know more about
-gnu-ar csr libm5pthread.a m5pthread.o
Funny thing...
On Tue, Apr 20, 2010 at 1:13 AM, nathan binkert n...@binkert.org wrote:
I have created a m5threads static linkable library for Sparc, with the
files
available in the m5 repository. I used the Sparc compiler available in
the
m5
Thank you.
Oddly enough, my experiments definitely show that sim_seconds is
reset, at least with the m5-stable repository.
I'm sure you're right. I just came up with things off the top of my
head. If you want to be certain about what is going on, you'll have
to look in stat_control.cc
I have been struggling with a performance bottleneck in the o3cpu model for
a few weeks (IPC capped at 3, regardless of the width of the core), and I've
been using gdb on m5.debug to try to find the bottleneck. From the debugging
information on the wiki
I was wondering if there was any more complete documentation on
resetstats and dumpstats than can be found at
http://www.m5sim.org/wiki/index.php/M5ops ?
resetstats, in particular does not appear to reset the total instruction
count.
sim_insts, sim_second, sim_freq, host_inst_rate,
Unfortunately, Jiayuan's patches have not yet made it back into the
main M5 tree, so if you want to use them, you'll probably need to get
help from Jiayuan himself or perhaps Rick Strong.
Nate
I am a beginner on M5 and doing a project on cache performance. However, I
found M5 seems not
In debug and opt mode, events have a unique instance number. You can
figure out the instance number and then run again scheduling a
breakpoint when the event matching the instance number is scheduled.
The only other alternative involves hacking code.
Nate
On Mon, Apr 12, 2010 at 8:05 PM,
Gabe,
Can you throw this whole explanation onto the wiki somewhere?
Thanks,
Nate
On Wed, Apr 7, 2010 at 1:36 AM, Gabe Black gbl...@eecs.umich.edu wrote:
The functions in pseudo_inst.cc are the back end implementation of the
standard M5 pseudo instructions. In the ISA definition, opcodes
there are stats on the dtb and itb. The misses result in page faults.
The access violations are also faults due to permission problems.
Nate
but in my simulation results i did not see any statistics on page faults.
here's my simulation result with this email. my command line is
According to the OpenVMS chapter of the Alpha Manual, IPL 31 is machine
check errors, which is baffling. I am curious to why their seems to be so
many of these IPL changes to this level. It doesnt sound right if IPL 31
correspond to machine check errors, I am wondering if this is incorrect.
I think these workarounds are fine, but the problem should not
exist... Nate's our python guru, so I'll give him the first
opportunity respond, but I wanted to confirm that there is a problem
and these workarounds should not be necessary.
I believe that I've fixed it. SCons does somewhat
The directory is in ALPHA_FS/python/m5/objects, though the only thing in
there is __init__.py. The rest of the contents of the directory are
gathered from throughout the M5 source tree. Anything with a SimObject()
call in a SConscript will end up in the objects directory.
Nate
On Mon, Mar 8,
Which version of M5 is this? The latest release version doesn't have
patches required for Ubuntu 9.10, so you'll need to clone the dev
repository.
Nate
On Fri, Feb 19, 2010 at 5:31 PM, arup de arup...@gmail.com wrote:
Hi,
I tried to build the M5. It gave following compilation error in
,
Initially I used the m5-stable repo it gave me
compilation error then Steve told me to use the m5 repo.
It works fine with ubuntu 9.10.
Arup
On Sat, Feb 20, 2010 at 4:43 PM, nathan binkert n...@binkert.org
wrote:
Which version of M5 is this? The latest release version doesn't have
patches
idea if you're not debugging.)
Nate
Hi, Nate, thank you for your reply. Yes, my machine is on the public
internet, but why is this a problem? Should I run M5 on a machine without
internet connection? Thank you!
2010/2/10 nathan binkert n...@binkert.org
My only guess is that there is some
My only guess is that there is some malware out there trying to probe
that port. Is your machine on the public internet?
Nate
Hi, all, I am using M5 ALPHA fs mode to run splash2. I compiled the splash2
programs (CHOLESKY) myself and copied to the ramdisk to boot the linux.
Typically a
Alpha requires that memory accesses are aligned. If they're not, they
trap and must be fixed up in software. x86 explicitly allows
unaligned accesses and they're handled in hardware. So, it's arguably
a bug in your benchmark. You might be able to get the linux kernel to
handle the trap, but I
In simics, we can use Haps to register a callback function, when some
events happen, we can run our own codes to do something. Can we do this in
m5?
To be more specific, I want to simulate until some point, like a function
call, then stop and do something. It seems now that I can only stop
M5 is built using whatever version of python you use to run SCons, so
if you want to use something other than the system python to build M5,
you must use that python to run scons:
path/to/my/python scons ...
I am trying to use the SConstruct file provided with m5.
When I give the command scons
Does M5 currently support a vector processor model? Maybe your answer is no
because, there is not any information in the documentation about vector
processing.
No, there is currently no vector processor model in M5.
Nate
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You need to configure the loopback interface.
ifconfig lo 127.0.0.1
Check out scripts in m5/configs/boot
Nate
On Mon, Dec 21, 2009 at 11:02 AM, Arun Rangasamy
arun.rangas...@gmail.com wrote:
Dear all,
I want to run some multi-threaded benchmarks, which use sockets for
communication, in m5
My AlphaStation 400 EV45 developed a hardware problem and I would like
to boot its Tru64 5.1b OS with M5 so I can recover files. All of the
disks use AdvFS, including the boot disk. I plan to connect the SCSI
drives to my PC which has M5's ALPHA_SE built under RedHat Linux. My
Tru64
This compiles on our systems. What version of m5 are you running?
What compiler? What kind of system?
Nate
2009/11/20 junli gu guju...@gmail.com:
Hi everyone,
I tried to compile scons build/X86_SE/m5.opt. There is error:
build/X86_SE/sim/eventq.hh: In member function 'void
I'll put out one caveat. He's using a 32-bit system and I don't think
anybody has touched that in a while. There may be some issues, but
they wouldn't be anything big.
Nate
On Fri, Nov 20, 2009 at 11:53 AM, Ali Saidi sa...@umich.edu wrote:
What about m5 version? The stable repository
Yeah, you're using too new of stuff for beta6. If you want to use the
latest stuff, you'll need to get the development version of M5.
Nate
2009/11/20 junli gu guju...@gmail.com:
I am using 2.0_beta6. With the m5_system2.0b3
--
Junli
I don't know if anyone has ever run M5 on an itanium. I can imagine
you having to do some debugging. The uncaught std::bad_alloc
exception is usually due to running out of memory though.
Nate
On Fri, Nov 20, 2009 at 3:26 PM, Sage leonard...@gmail.com wrote:
Hi, everyone,
I got the
hmmm. This is a problem with the way the alpha console works.
There's an object called AlphaBackdoor that allows the console code to
get parameters about the system. The AlphaBackdoor uses the system
pointer to get to physmem and query it about how much memory it has.
Unfortunately, this all
Nate, Steve, if you so desire, I could make the X86_32 alpha cross
compiler toolkit available through the M5 page.
Soumyaroop,
The M5 page is a wiki. You should be able to put it up yourself. Can
you try? If the file is too large, I can at least stick it somewhere
and then you can link to
My estimate is that the tar-zipped file should between 250-300 MB.
No problem.
Let me host it somewhere and send you the link so that you may download it.
Sure. Once I get it on the m5 site, you can add the link.
Do you mean providing the link though the wiki? I do not have
permissions to
Do we have McPAT framework in M5 repository?
McPAT is a separate tool. It does work with M5 though. McPAT can be found at:
http://www.hpl.hp.com/research/mcpat/
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On Mon, Oct 19, 2009 at 10:40 AM, Steve Reinhardt ste...@gmail.com wrote:
I think this only works if IPRs do not have side effects. I'm pretty sure
there are IPR writes that need to be serializing because they change things
like ASID. It might be possible to treat IPR writes as serializing
Ah, yes... I used grep to see that there was a rduniq entry in decoder.isa
but failed to realize that that was the SE-mode-only version.
The funny thing is that even though I rightly pointed that out, I
still was confusing the callpal rduniq and the MTPR/MFPR. Seems that
we could have MTPR be
This is a swig problem. I haven't yet had confirmation as to which
version actually causes this problem, but if you upgrade to at least
1.3.31, I believe that it solves this problem. I'm just going to
update the webpage and make this the minimum version.
Nate
On Sun, Oct 18, 2009 at 11:26
I noticed that the M5 pal code is based on the ev5, is it possible to
make it ev6 or ev67? Or are there no benefits?
My main overall issue I am thinking about is I am trying to see if
their is any problems in my compiled benchmarks, as I have made them
ev67 code, ev5 has given me lower ipc
My guess is that this is the result of calling rdunique and wrunique.
These pal instructions keep track of the currently running thread.
They more or less just access a single internal pal temp register.
There are a number of things that could potentially be done to fix the
slowness here. You
build/X86_SE/arch/x86/decoder.cc
build/X86_SE/arch/x86/decoder.cc:54164: error: integer constant is too large
for 'long' type
cc1plus: warnings being treated as errors
build/X86_SE/arch/x86/insts/microldstop.hh:67: error:
'X86ISA::SegmentFlagMask' defined but not used
I'm guessing that
I believe that's a generated file so $self is likely a symptom, not
the root problem. Could you show us a portion of that file around
where the error happens?
No, $self is in a .i file. The problem is the version of swig. I
can't remember exactly what version of swig had this problem (can
Did this diff ever make it into the tree? Was it correct?
Nate
On Wed, May 13, 2009 at 9:06 PM, Rick Strong rstr...@cs.ucsd.edu wrote:
Starring at code and traces, it appears that a fetch attempt occurs
after waiting for a long latency icache block. The rest of the cpu
has nothing to do
Is there any documentation on how events from the main event queue are
processed and how to create new events and schedule them on the main
event queue?
Not really. The code is reasonably well commented though and there
are hundreds of examples of using the event queue in the code. We'd
Hello,
I am following the steps here:
http://m5sim.org/wiki/index.php/Debugging_M5
For kernel debugging
we configure like this:
./configure --target=alpha-linux
however I am getting these issue in the debugger:
Remote 'g' packet reply is too long:
I need more of the message. We need to figure out why it's getting
libpython2.4.a instead of libpython2.4.so
What sort of machine is this? (Please be as detailed as possible.)
Nate
On Fri, Aug 21, 2009 at 9:30 AM, Cong Wangjameswan...@yahoo.com wrote:
Hi All:
I am trying to compile
scripts call these functions, at least
not explicitly, so I'm not sure where I could add the shutdown/destroy
call.
Joe
nathan binkert wrote:
Is there some way to get the simulator to call the destructors of the
components in the test system (FS mode) or to receive an event signaling
If anyone on the list has any good reasons why a trace-driven CPU
should or should not derive from BaseCPU I'd be happy to hear them. I
can see some advantages (like inheriting some of the memory hierarchy
helper functions, like addPrivateSplitL1Caches()), but you also end up
having to
Hi Steve:
Thank you for your reply. The problem for my code to be outside of
the m5/src tree is that there are code in src/cpu/cpu_model.py that
has to
#include cpu/timingtracecpu/timing_trace.hh
If I put my code outside the m5/src/ how do I make sure the
cpu_model.py can still
Thank you for your comment. So, does that also mean that if I
include any of the file in the m5/src/ directory in the EXTRAS=foo/bar
file, I need to specify that file in the path that is relative to the
foo/bar directory?
Let's say that I have my foo/bar file in /home and m5/src is also in
Generally, if you can't mmap at all, it's because of a limitation in
the OS or hardware or something like that. If you have a 32-bit
machine, the limit is virtual memory address space. If you have a
64-bit machine, the limitation is probably total available virtual
memory (RAM + swap) or the
was indeed the problem. I posted an updated console binary
for the ALPHA for anyone interested @ http://rickshin.ucsd.edu/console
Best,
-Rick
nathan binkert wrote:
System.terminal:*
Memory cluster 1 [392 - -262536]
Initalizing mdt_bitmap addr 0xFC038000 mem_pages FFFC
I see one problem with this diff and a couple of nits.
1) What happens if physical memory is not a multiple of chunksize?
You don't actually deal with the tail end properly. (As far as I
know, physical memory is only required to be a multiple of pagesize.)
2) You left commented out code in the
The EIO failures are indeed because you don't have the encumbered EIO
support compiled in. This is a limitation in our testing framework.
(Which I will correct eventually.)
As for the SPARC_SE problem, it's indicated as an internal compiler
error which is generally not an M5 issue. In my
You need to define a function that looks something like this:
Oracle *
OracleParams::create()
{
return new Oracle(this);
}
For more information, check out the tutorial. I believe this is in
there. There's also lots of examples in the tree.
Nate
On Thu, Jul 30, 2009 at 6:37 PM, Cong
Does it work for full system mode?
On Wed, Jul 29, 2009 at 7:01 AM, Korey Sewellksew...@umich.edu wrote:
Yup,
Lisa is correct.
O3's for an of out of order design. If you want to approximate an in-order
using O3 you can restrict some of the out of order queues (IQ,LSQ,etc.)...
However, the
It still gives me the same message. I tried 4.2.2 (which is created in Jan
2007 and 2.0b5 is created in Feb 07) and 4.1.3.
Now I am trying to move to 2.0b6. I have a query here:
In 2.0b5 version, in cpu_builder.cc file. This returns a cpu
DerivO3CPU(params) with params which is of
Which gcc version would work with 2.0b5, if I install that gcc is it going
to work?
I'm guessing 4.2 would work. I'd say that if you want to be sure,
find out what the latest version of gcc was when we created 2.0b5 and
use that.
Nate
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This is just an arithmetic instruction and should be rather easy to
implement. Just look in the Alpha architecture reference manual and
implement the instruction. Check out src/arch/alpha/isa/decoder.isa.
If you have questions, let me know.
PLEASE send us a diff if you do implement these
I do have to mention though that this request comes up frequently, so
if anyone actually ever does write this code, please share it with us!
On Mon, Jul 6, 2009 at 11:10 AM, Steve Reinhardtste...@gmail.com wrote:
I don't believe there's any existing code for flushing the caches. You'd
have to
I want to know if M5 is a deterministic simulator?
Is M5 a single-threaded simulator, or if not, how it support deterministic
simulation (the same result every time running it)? For example, GEMS is
considered deterministic because it is a single-threaded simulator.
Is this related to how we
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