things up properly.) Is the version
built in that directory not python2.4? Do you have a libpython2.4.so
in that directory?
Nate
On Fri, Sep 26, 2008 at 1:28 PM, Eduardo Olmedo Sanchez
[EMAIL PROTECTED] wrote:
Hello I'm trying to run the m5-simulator, but I'm stuck in this error,
here
are described in the second wiki link that steve
posted.
On Fri, Sep 26, 2008 at 1:56 PM, Eduardo Olmedo Sanchez
[EMAIL PROTECTED] wrote:
Hi thanks for your answer, I'll tell you what I did, since I cannot have
root privileges in my machine I installed locally all the packages
Python
Hi whem I'm compiling the m5 with this option scons USE_MYSQL=False
build/ALPHA_FS/m5.debug, everything seems goes well but finally I get this
output:
build/ALPHA_FS build/ALPHA_FS/enums/Enum.cc
build/ALPHA_FS/enums/Enum.cc:5: internal compiler error: in tree_low_cst, at
tree.c:3318
Please
, not M5. I
suggest you use a different compiler.
Nate
On Mon, Sep 29, 2008 at 9:21 AM, Eduardo Olmedo Sanchez
[EMAIL PROTECTED] wrote:
Hi whem I'm compiling the m5 with this option scons USE_MYSQL=False
build/ALPHA_FS/m5.debug, everything seems goes well but finally I get
this
output
should work fine. I think you just got unlucky with
your version number. We generally always compile with versions =
4.0, but I do compile with 3.4.6 on one machine and it works.
Nate
On Mon, Sep 29, 2008 at 9:53 AM, Eduardo Olmedo Sanchez
[EMAIL PROTECTED] wrote:
Hi Nate thanks
, Eduardo Olmedo Sanchez
[EMAIL PROTECTED] wrote:
Hi Nate thanks for your answer. I'm using g++ 3.4.3 version, do you
recommend to update the g++ to another version or use another one
different
than g++?. Thanks.
On Mon, Sep 29, 2008 at 9:49 AM, nathan binkert [EMAIL PROTECTED
Hi, I have to simulate a at least 16 multicore processor with a three levels
cache L1, L2, L3, what we are trying to do is get perfomance results about
the access of the cores to the cache and the memory. I've been reading the
wiki and the sildes of the tutorial at ASPLOS 2008, but I still don;t
Hi Meng-Ju thanks for your answer, is that all?, it's very easy, when I saw
the example I thought that if I put 8, 16 or whatever in the
options.num_cpus what I'm doing is adding more cpus to the system not
cores., so just changing that variable do I change the cores?.
Now I got another question.
, there is nothing. How can I get
those results?, thanks.
On Wed, Oct 1, 2008 at 3:00 PM, Philip Machanick [EMAIL PROTECTED]
wrote:
On Thu, Oct 2, 2008 at 7:41 AM, Eduardo Olmedo Sanchez
[EMAIL PROTECTED] wrote:
Hi Meng-Ju thanks for your answer, is that all?, it's very easy, when I
saw
Hi Meng thanks for your answer I did my test with the example code that it's
here /configs/example/se.py, and this is the command that I used to run the
simulation:
$ build/ALPHA_SE/m5.debug -d /tmp/output configs/example/se.py
And this is the output that I get:
M5 Simulator System
Copyright
on
'Stats::dump()' does it get reached? What if you don't use -d? Does an
m5stats.txt appear in the directory you're running m5 from. Does it
have any statistics in it?
Ali
On Oct 2, 2008, at 10:44 AM, Eduardo Olmedo Sanchez wrote:
Hi Meng thanks for your answer I did my test with the example
Hi Meng yes I got my config.ini, the problem was that M5 couldn't write in
/tmp/output and it didn't say anything, I just changed the directory to a
local one and everything was fine, thank you again.
On Thu, Oct 2, 2008 at 9:27 AM, Meng-Ju Wu [EMAIL PROTECTED] wrote:
Hi Eduardo,
Do you have
Hi:
This is the first time that I simulate my own benchmark, and it's taken a
long time, and I'd like to ask if it's normal, the execution of the program
in my computer takes over 2~5 secons, but the simulation has been 1h30m and
it's not finishied. I think that the simulator is correct
Hi, I'm trying to simulate a system with a Three Level Cache configuration
L1 (one per core), L2 shared and L3 shared. This is my code for the cache:
system.l2 = L2Cache(size='2MB')
system.tol2bus = Bus()
system.l2.cpu_side = system.tol2bus.port
system.l2.mem_side = system.membus.port
system.l3
Hi:
I have to change the policy that the simulator uses to access to the cache.
And I got several questions for example if there are three cores that want
to acces to the shared cache, what policy is used?, hit first, round
robin..., where is the code of that policy?, and finally is it possible
be round robin (if they all access at the same
time), or FCFS if not.
If you want to do something fancier then you could extend the cache to have
multiple CPU-side ports and put the arbitration logic in the cache between
those ports.
Steve
On Fri, Oct 10, 2008 at 9:42 AM, Eduardo Olmedo Sanchez
?. Thanks.
On Tue, Oct 14, 2008 at 2:04 PM, Eduardo Olmedo Sanchez
[EMAIL PROTECTED]wrote:
Hello Steve thanks for your answer, yes I have to do something fancier for
an assignment, can you tell me where is the source code for the policy?,
I've been looking in the cache code and in the cpu code
.
Original message
Date: Wed, 15 Oct 2008 12:19:51 -0700
From: Eduardo Olmedo Sanchez [EMAIL PROTECTED]
Subject: Re: [m5-users] Policy used by the simulator for the cache access
by the cores
To: M5 users mailing list m5-users@m5sim.org
Hi, I hope that someone can help me, Steve said
Hello I have made some changes in the source code in the function
/src/mem/bus.cc, but when I compile with the command scons
build/ALPHA_SE/m5.debug, I get the following output.
build/ALPHA_SE/cpu/checker/memtest/memtest.cc:41:34: error:
cpu/memtest/memtest.hh: No such file or directory
/memtest. Did you accidentally move that directory?
Nate
On Wed, Nov 5, 2008 at 9:11 AM, Eduardo Olmedo Sanchez
[EMAIL PROTECTED] wrote:
Hello I have made some changes in the source code in the function
/src/mem/bus.cc, but when I compile with the command scons
build/ALPHA_SE/m5.debug, I get
Hello,
I have installed bochs and now I have dllinux running and it using as
hard disk a file called hd10meg.img, the kernel is 1.3.89. So the
procedure that I should is: add my binary to the hd10meg.img and after
move the img to the simulator. Where should I put the binary in the
img? and Should
a disk
image with a simple linux on it without user interface and that
stuff?. thanks so much.
2008/11/13 Eduardo Olmedo Sanchez [EMAIL PROTECTED]:
Hello,
I have installed bochs and now I have dllinux running and it using as
hard disk a file called hd10meg.img, the kernel is 1.3.89. So
, Eduardo Olmedo Sanchez [EMAIL PROTECTED]
wrote:
Hi I have been able to run knoppix on vmware, but I still do not get
what I have to do, do I need to do all the procedure from here
http://www.m5sim.org/wiki/index.php/Using_linux-dist_to_Create_Disk_Images_and_Kernels_for_M5
to create
files to the disk image we
provided, and you don't change the name of the image, then you don't need to
change anything in the config scripts. You'd just need to make rcS scripts
to do what you want with the files you added.
Lisa
On Wed, Nov 19, 2008 at 4:38 PM, Eduardo Olmedo Sanchez [EMAIL
again,
On 11/20/08, Lisa Hsu [EMAIL PROTECTED] wrote:
Since you have changed the name/location of your disk image - did you change
the simulator to actually point to it and use it?
Lisa
On Thu, Nov 20, 2008 at 3:12 PM, Eduardo Olmedo Sanchez
[EMAIL PROTECTED]wrote:
Hi Ali thanks for your
These are the changes that I did to the fs.py file:
np = options.num_cpus = 4
test_sys.l2 = L2Cache(size = '4MB', assoc = 4, latency = '30ns')
test_sys.cpu[i].addPrivateSplitL1Caches(L1Cache(size = '64kB', assoc
= 2, latency = '2ns'),
Hello,
I am having problems with the PARSEC benchmarks, I am getting this
error running x264, bodytrack, canneal, swaptions in a 4 core system,
in Full System mode, with 4 threads and with the small workload.
warn: allocating bonus target for snoop
m5.opt: build/ALPHA_FS/mem/tport.cc:97: virtual
what is going wrong and begin to realize how to fix it.
Ali
On Jan 2, 2009, at 5:48 PM, Eduardo Olmedo Sanchez wrote:
ck, canneal, swaptions in a 4 core system,
in Full System mode, with 4 threads and with the small workload.
warn: allocating bonus target for snoop
m5.opt: build/ALPHA_FS
the exact line that you're executing but generally it works. Looking
at those 3 lines I don't understand how they could be causing a
problem. Perhaps your array is allocated incorrectly?
Ali
On Jan 2, 2009, at 8:16 PM, Eduardo Olmedo Sanchez wrote:
Hello Ali, you were right, I tried
Hello, I would like to ask if someone know or have heard about anyone
that have been able to run the NAS benchmarks in the simulator.
Thank you.
___
m5-users mailing list
m5-users@m5sim.org
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Hi Isuru, I found this link using google the other day
http://www.m5sim.org/wiki/index.php/Integrating_M5_and_GEMS
I believe this link is not shown in the m5 wiki. I hope it helps.
On Thu, Jan 22, 2009 at 10:45 AM, Isuru Herath isur...@yahoo.com wrote:
Dear All,
Today I accidentally saw
Hello, I am trying to stop my workload in FS but I am having problems
I am using this instruction in the fs.py file:
test_sys.cpu[i].max_insts_all_threads = 5000
Basically what it happens is that the simulation starts and finish
immediately without running any instructions. In SE mode those
Hello,
Regarding the question of how to run your own benchmarks in FS, it is
not necessary that you create a new disk image. You can use the one
that is provided in the wiki, in this link you can download one
http://www.m5sim.org/dist/current/m5_system_2.0b3.tar.bz2
What you need to do is add
Hello,
I am working with the out of order CPU o3 cpu. And I would like to ask
if it is possible to change size of the instruction window. In
addition can anyone please give some details about how is the
management of the instruction window?.
Thanks a lot in advance.
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