Re: [gem5-users] help

2017-02-04 Thread Jason Lowe-Power
Hello, This is probably a bug in the network test config file. This is not a script that is run very often, so I wouldn't be surprised at all if there was something wrong. The error you're seeing is occurring somewhere in the Python configuration files. I think it's happening before gem5's

Re: [gem5-users] L1 Cache Port Width Size

2017-02-04 Thread Jason Lowe-Power
Hi Yasir, gem5's ports are not as much of a physical model as they are a programming API. The "width" of the CPU->cache connection is determined by the CPU model (how many requests the CPU can issue per cycle) and the cache model (how many requests the cache can accept per cycle). The CPU (or any

Re: [gem5-users] Implementing Cache Hierarchy for running ASIM/MOBY benchmark

2017-02-04 Thread Jason Lowe-Power
Hi, It's unfortunately not that simple to extend the fs.py script. It uses complex and inflexible logic to set up the system. I would strongly encourage you to write your own script from scratch to support this. You can find an example for X86 here: http://learning.gem5.org/book/part3/index.html.

Re: [gem5-users] Number of instructions Vs number of ticks + resetstats + checkpointing

2017-02-04 Thread Jason Lowe-Power
Hi Ali, Since you're doing something that isn't fully supported by the fs.py script, I would suggest making your own config file. The fs.py script, and the other supporting scripts in common/, are not very flexible, and when you want to do something that is a little outside of the norm it becomes

Re: [gem5-users] Issue with creation of L3 Cache (and tol3bus)

2017-02-04 Thread Jason Lowe-Power
This is hard to understand what's going on, but I'll try: The error is "AttributeError: object 'O3_ARM_v7a_3' has no attribute 'tol3bus'". This means that you are referencing the variable tol3bus before it is defined. Did you add this variable to the ARM CPU? It would probably make more sense for