Thank you Jason for your quick reply!
On Sat, May 19, 2018 at 12:50 PM, Srajan Khare wrote:
> Hi friends,
>
> I have been implementing Cache Compression algorithm in gem5.
> So in order to tap data for all the writes into L3 cache I have been using
> handleFill() function in cache.cc file. I ha
Hi Jason,
As per your suggestion I included the recently committed patch (for
creating sector cache) with my gem5 version. Then after, just to get an
idea of Sector Cache performance, I ran simulation for *bzip2 *SPEC CPU2006
benchmark with 1B fast forward and then executing 500M instruction in
De
I have followed the instructions provided in the gem5.org website to run
the Moby benchmarks on gem5 as follows:
1. Downloaded the Asimbench from
https://bitbucket.org/yongbing_huang/asimbench/downloads/ which contains
the following folders and files:
1. asimbench_android_arm_kernel :
v
Dear Mitali Sinha.
In my case, I run moby bench with RealView_PBX machine type.
I don't know if it is the cause, but give it a try.
Best Regard,
Haeyoon Cho.
2018-05-29 20:39 GMT+09:00 Mitali Sinha :
> I have followed the instructions provided in the gem5.org website to run
> the Moby benchmark
Hi Srajan,
Could you post this on our code review site so the patch creator (Daniel)
can take a look? You can register on the site with a google account (e.g.,
your gmail). Then, you can post a reply on this page:
https://gem5-review.googlesource.com/c/public/gem5/+/9741.
One possible source of y
Hello All,
I followed learning.gem5 to create an L1 cache. Than I created another (L2)
cache using same code and connected the two caches using L2XBar.
Now, For small test routines, the two cache configuration works perfectly.
I tried to simulate kmeans (Axbench) with two cache ( L1, L2) version
Hi,
How is a particular instruction being decoded, especially when it has
micro-ops? I looked at the stats in commit_impl.hh
if (!inst->isMicroop() || inst->isLastMicroop())
instsCommitted[tid]++;
opsCommitted[tid]++;
Does this means the micro ops is also stored as a Dynamic Inst, with
different
Hello everyone,
I have been reading several posts in this forum and the gem5 documentation,
I am new with gem5, I have to work with memory subsystem and I have
already changed characteristics on main memory and cache memory as train.
However I have some questions that I have not answered reading
Dear Haeyoon,
Many thanks for your help and guidance. I will try to apply
first scheme suggested by you in previous email.
Best Regards,
Avais
On Mon, May 28, 2018 at 1:18 PM, 조해윤 wrote:
> Dear Avais,
>
> I think it is reasonable to normalize with the numbers of executed
> instru