[gem5-users] Re: Full system files Makefile. missing

The new method is here: https://www.gem5.org/documentation/general_docs/m5ops/ *Chongzhi "Paul" Zhao* Doctoral Student in Computer Engineering Texas A University Email: chongzhizhao4 (at) gmail (dot) com On Fri, Aug 21, 2020 at 12:44 PM Abhishek Singh via gem5-users < gem5-users@gem5.org>

[gem5-users] Full system files Makefile. missing

Hello Everyone, I am trying to build a Full system image using Step 2 "Using gem5 utils and chroot to create a disk image" mentioned here ( https://www.gem5.org/documentation/general_docs/fullsystem/disks). I cannot locate "Makefile." in gem5_20 (util/m5) and develop branch. Is this method no

[gem5-users] SLICC: Main memory overwhelmed by requests?

Hi all, I am trying to run a Linux kernel in FS mode, with a custom-rolled SLICC/Ruby directory-based cache coherence protocol, but it seems like the memory controller is dropping some requests in rare circumstances -- possibly due to it being overwhelmed with requests. The protocol seems to

[gem5-users] Re: [ARM system] Question about the cleassic cache system

Hi, Ciro Thank you for sharing this. I saw Jason initiated a code review for Tiago's update last month. So I guess this work will be added to the main repository soon. ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an

[gem5-users] Re: [ARM system] Question about the cleassic cache system

I'm not sure about the cache hierarchy issue. But about Ruby support, I don't think there's any known ARM specific problem, and ARM contributors have been specifically pushing Ruby recently, see e.g. see Tiago's CHI announcement: https://www.gem5.org/2020/05/29/flexible-cache.html

[gem5-users] Re: issues in FS mode with TimingSimpleCPU+Multicore

Hi Jaspinder, What you observed is consistent with this post: https://www.gem5.org/documentation/benchmark_status/ The common advice is usually that you boot with AtomicSimpleCPU, make a checkpoint, and then restore the checkpoint with a more detailed CPU model. Sincerely, *Chongzhi "Paul" Zhao*

[gem5-users] [ARM system] Question about the cleassic cache system

Hi, ALL I'm doing some design space exploration work using GEM5. My work is exploring the different cache structures, using ARM cores, classic cache structure, and use parsec-3.0 to simulate the multi-core performance. My system has 4-level caches, every level using L2XBar to connect. Use big

[gem5-users] Re: SLICC: Main memory overwhelmed by requests?

Hi Theo, It's possible that if you increase the deadlock timeout your protocol will "just work". There's an infinite queue between the memory controller (DRAMCtrl) and the Ruby directory (which sends the memory requests to the memory controller). We've made some progress to correctly model

[gem5-users] Re: Full system files Makefile. missing

Thanks! Best regards, Abhishek On Fri, Aug 21, 2020 at 1:47 PM Chongzhi Zhao wrote: > The new method is here: > https://www.gem5.org/documentation/general_docs/m5ops/ > > *Chongzhi "Paul" Zhao* > Doctoral Student in Computer Engineering > Texas A University > Email: chongzhizhao4 (at) gmail

[gem5-users] Running Tensorflow application on gem5

Hello Everyone, I am trying to run LeNet and AlexNet (tensor flow code) at this github (Link: https://github.com/iCAS-Lab/IMAC/tree/master/Tensorflow). I have made a disk image using Step 2 "Using gem5 utils and chroot to create a disk image" I am using Linux-4.8.13 kernel and ubuntu 16. I am

[gem5-users] issues in FS mode with TimingSimpleCPU+Multicore

Dear All, I am trying to boot gem5 in FS mode for multiple cores. However, I am facing a problem as mentioned below: 1. Atomic CPU - working properly. 2. TimingSimpleCPU - Single core - working properly. 3. TimingSimpleCPU - multiple cores (2 or 4) - the execution stuck after