Hi Gabriel,
Welcome on board!
Giacomo
-Original Message-
From: gabriel.busnot--- via gem5-users
Sent: 03 November 2020 10:03
To: gem5-users@gem5.org
Cc: gabriel.bus...@arteris.com
Subject: [gem5-users] Introducing myself
Hi Gem5 community,
I want to introduce myself as a new Gem5
Hi Gem5 community,
I want to introduce myself as a new Gem5 user.
My name is Gabriel Busnot and I work at Arteris IP, a major network-on-chip IP
provider.
I am working on a new model for performance evaluation of architectural
changes, coherence protocol testing and quality-of-service
Hi all??
What I want to do now is to run a program in FS mode and observe the
statistical differences among different code segments.
I know that in SE mode, this work can be easily done with M5ops, for example,
add a code:
m5_dump_reset_stats(0,0)
In the FS mode, M5ops can be input through the
In the fetch function in the src/cpu/O3/fetch.impl file, when fetching
instructions to the fetch queue, I saw some operations on the decoder, which
made me very confused. For example, decoder[tid]->decode(thisPC),
decoder[tid]->instReady(), decoder[tid]->needMoreBytes(),
What does TimeBuffer in gem5 do? I read its source code, but there are no
comments and it is not easy to understand operations. I saw in the tick
function in the cpu.cc file that every tick() will proceed
timeBuffer.advance();
fetchQueue.advance();
decodeQueue.advance();
Hello,
I've been using gem5 for ~10 years, and this is the first time I've ever
seen this code :D. It was committed 14 years ago, and it hasn't been
touched since.
It looks to me like it's used for gathering statistics about the activity
of different CPU pipeline stages. However, I *know* it's
Hi all??
About a few months ago, I followed the guidelines of this link to
successfully build M5ops??
https://www.gem5.org/documentation/general_docs/m5ops/
Now I am still using gem5-20.0 and have not updated to the new
version, but when I run this command again:
scons
Hello,
(1) Yes, I believe so.
(2) I thought MOESI_hammer was annotated, but it doesn't look like
(huh...). However, AMD MOESI Base is annotated. See all of the transition
in the core-pair file, for instance:
Hi Pedro,
No, I don't have any specific pointers beyond the code in src/sim/. One
quick note: on develop there is something in flux about how syscalls work.
There's been some recent changes from Gabe to the "Workload" and the
syscall dispatch. I have to admit I don't understand them, but it might
Hi Siqing,
It should be "x86" with a lowercase x rather than "X86".
Regards,
Hoa Nguyen
On Tue, Nov 3, 2020, 12:52 AM -17 via gem5-users
wrote:
> Hi all：
>
> About a few months ago, I followed the guidelines of this link to
> successfully build M5ops：
>
>
Hey guys,
I just interacted with it to fix a bug in the O3 cpu. Seems to me
a Timebuffer is how the pipeline stages communicate with each other.
Looks like a wrapper for the datastructures that
communicate between different stages, as "wires."
Each wire within a time buffer communicates between
Hi,
Though I'm not sure how to add the cache clearing instruction specifically,
those are a few examples that new instructions are added,
https://gem5-review.googlesource.com/c/public/gem5/+/26123
https://gem5-review.googlesource.com/c/public/gem5/+/23262
Hi,
In the file SimpleNetwork.py at line 67 (version v20.1.0.0), it is checked that
the internal side of the network link is connected to ONE OF the routers before
instantiating a buffer for that link:
if link.int_node in self.routers:
This action is done in a loop on the
Hi Yujiecui,
The fetch stage in O3CPU fetches cache lines from instruction cache and
also calls ISA specific decoder implementation to decode the raw bytes into
instructions and access the corresponding micro-ops for these instructions
(In other words, fetch stage outputs the micrco-ops). That's
Hey Liyichao,
I'm sorry to somewhat avoid answering the question (I don't know enough
about dist-gem5 to comment), but dist-gem5 is grossly under-tested and
hasn't had any decent maintenance in a while, so it really comes with no
guarantees, and it wouldn't surprise me at all if it doesn't work
Hi All:
I just add a ethernet object in dist-bigLITTLE.py on VEXPRESS_GEM5_V1, but
AddRange debug print “fatal: Unable to find destination for
[0x4008:0x400c] on system.iobus
So how to config the mem range in RealView.py or in any other code ?
”
The function of create Ethernet is :
Hi Siqing,
You can find the PARSEC ROI example mentioned in the webpage is here,
https://github.com/darchr/parsec-benchmark/commits/gem5-20-annotations
gem5-resources (https://gem5.googlesource.com/public/gem5-resources/)
has the documentation of setting up full system gem5 experiments with
Hello,
I have two C programs. In my first C program I am assigning 2GB memory space to
an integer array and in my second C program I am assigning 4GB memory space to
another integer array. I am assigning memory space via C's malloc() function.
Both my first and second programs work fine on my
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