[gem5-users] Re: Capturing SimPoint and running on ARM CycleModel

Hi Jonathan, I have experience simulating SimPoint area through O3CPU in se mode.(use the checkpoint function of gem5) I don't know if it's only in my case, but not all Benchmarks in spec2017 had a smooth simulation process with SimPoint. I'm still looking for a way to fix some of the workloads.

[gem5-users] TLB Miss penalty in O3CPU and se.py

Hi, I’m currently simulating ARM O3CPU through SE mode. It was confirmed that generic page fault occurred and was restored in mmu. Does this process affect the entire cycle as a penalty? Regards, Haseung ___ gem5-users mailing list --

[gem5-users] Re: Determine the number of pipeline stages

Hi Joao, If it is an in-order, is it implemented by changing all path widths to 1 using o3cpu? Or did you use AtomicSimpleCPU, TimingSimpleCPU, MinorCPU? If your cpu-type is o3cpu, The basic pipeline configuration is shown in the link below.

[gem5-users] Re: There is not 'IsFloating' in arm/operands.isa

he same storage with SIMD (Vector) registers, > so we usually refer to them as SIMD registers. > > This is why in gem5 we don’t use the floating point register type and we > use the vector type only > > > > Kind Regards > > > > Giacomo > > > > *From: *봉하승 via

[gem5-users] There is not 'IsFloating' in arm/operands.isa

Hi,  I'm trying to use gem5 to simulate SPEC2017's LBM.  LBM is an FP workload, and the simulation shows that "system.switch_cpus.commit.floating" is zero in stats.txt.  As a result of a little search, it was confirmed that instructions such as fadd and fsub were classified as 'isVector'.  I

[gem5-users] Re: IprAccess in FUPool

Hi, IPR is Interrupt Priority Register in ARM. I looked it up, But Instructions used to access the IPR can vary depending on the specific implementation of the processor and the Interrupt Controller being used. So, I think that why the Instructions classified as ‘IprAccess’ is not

[gem5-users] Past questions about cpu configuration

Hi, I did not understand how the proposals in the above content would affect the simulation results. What I'm curious about is whether the above has been updated to the current Gem5 version! Regards, Haseung

[gem5-users] Differences between simulating spec2017 in fs mode and se mode

Hi :) I simulated SPEC2017 in SE mode and FS mode. I created a checkpoint before the workload was executed through bootscript and after this checkpoint, I checked the log with the option of --debug-flags=ExecEnable,ExecUser for the simulation result in fs mode. In the log, there was an

[gem5-users] Query regarding Running Custom FS image for ARM FS simulation

Hello, I don't know exactly what kind of error it is in your mail, I think you should consider using "--bootloader" and "--kernel-init" among the options. ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to