Re: [gem5-users] ARM DerivO3CPU assertion failed

*From:* gem5-users on behalf of Carlos Escuin *Sent:* 11 February 2020 16:46 *To:* gem5-users@gem5.org *Subject:* [gem5-users] ARM DerivO3CPU assertion failed Hi all, I'm trying to execute bzip2 spec 2006 benchmark in ARM

Re: [gem5-users] Modifying source code in gem5

Make sure you activate the 'option' for executing with O3 cpu:    --cpu-type=DerivO3CPU Carlos On 1/3/20 10:27, Eun-Sung Kim wrote: I’m trying to modify source code in gem5. For testing, I add a cprintf() statement to src/cpu/o3/fetch_impl.hh. Then using scons, I rebuild gem5. But, any

[gem5-users] [ARM se Ruby] Page fault with SPEC CPU 2006 for ARM ISA

Hi, I'm trying to execute the SPEC CPU 2006 benchmark on multicore, ARM, se. However I'm having this problem:    panic: Page table fault when accessing virtual address 0x11 So far, I have read that the problem may come from the cross-compiling of the SPEC benchmarks. Any hint in which

Re: [gem5-users] ARM DerivO3CPU assertion failed

nected()' failed. == MOESI_hammer build Same as MESI_Three_Level, except that the checkpoint with --ruby works before bb94296373dde1d0ce971ee58ad111f4225c425e as expected. On 2/12/20 9:45 AM, Carlos Escuin wrote: Thank you for replying, Yes, it seems that something is not going well whil

Re: [gem5-users] [ARM se Ruby] Page fault with SPEC CPU 2006 for ARM ISA

ARM/BuildEABIChroot>. On 3/2/20 8:00 PM, Carlos Escuin wrote: Hi, I'm trying to execute the SPEC CPU 2006 benchmark on multicore, ARM, se. However I'm having this problem:    panic: Page table fault when accessing virtual address 0x11 So far, I have read that the problem may come fro

[gem5-users] [SE Multicore Ruby] Assertion failed for multicore simulation

Hi all, I'm trying to execute gem5 in se mode, multicore, using Ruby memory subsystem, X86 ISA. An assertion is failing for most of the benchmark mixes I'm trying: $> command line: ./gem5.opt --outdir=gem5/m5out/spec2k6/leslie3dsoplexGemsFDTDlibquantum se.py --num-cpus=4

Re: [gem5-users] MultiProgrammed Workload X86 O3CPU error using SMT

Hi Abhishek, I think when you check *m5out/config.ini*, you should look at *switch.cpu* instead of *system.cpu*. System.cpu is always initialized to AtomicSimpleCPU by se.py. Switch.cpu is the one you indicate in options and the one whose stats you should be looking at. System.cpu

[gem5-users] ARM DerivO3CPU assertion failed

Hi all, I'm trying to execute bzip2 spec 2006 benchmark in ARM, se, DerivO3CPU, ruby, fast-forward. Anyone has any idea why I'm getting this assertion failing? Thank you, Carlos OUTPUT: command line: gem5/build/ARM_MOESI_CMP_directory/gem5.opt -v

[gem5-users] Re: GEM5/Ruby and MESI_Three_Level protocol

Hello, Open the file 'MESI_Three_Level.slicc' and you will see the files the protocol MESI_Three_Level is being generated from. You will see that it is using some components from the MESI_Two_Level protocol. Hope this is helping you. Carlos On 28/5/20 11:48, Javed Osmany via gem5-users

[gem5-users] Re: [SE Multicore Ruby] Assertion failed for multicore simulation

Hi Taiyu, Jason, As far as I could go through it I end up thinking that something is crashing during a syscall: The crash is related to unfound input files of the benchmark/application you are running over the 'se'. Therefore, what I did is to double check the input/output data files the

[gem5-users] Assertion failing for SE mode for O3 cpu ARM

Hi all, I'm encountering the assertion fail reported herehttps://gem5.atlassian.net/browse/GEM5-438. I'm trying to execute SPEC CPU 2006 in SE mode for O3 cpu. I'm doing fast forward and I'm getting the assertion fail at the switching cpu. As I

[gem5-users] [ARM O3 SE] Panic: Page table fault

Hi all, Since executing workloads compiled for arm-32-bits is giving me problems (https://gem5.atlassian.net/browse/GEM5-438), I compiled them for AArch64. However, for some of the workloads (SPEC CPU 2006) I'm encountering a page table fault. Has anyone already dealt with this issue?

[gem5-users] Re: In Ruby, I have changed my MESI_Three_Level-L0cache.sm, but panic: Runtime error, assert failure

Hello Zhen, Icache is the reference to the L0-instructions cache and Dcache is the one to the L0-data cache. It's usual to find the first level of a conventional cache hierarchy split into instructions and data. The purpose of the assert is, basically, to check that the same block is not