Re: [gem5-users] Arm Instruction length in Gem5

Lyn, You are right about the length of the instructions as defined by the ISAs. However, within gem5 we use a few extra bits in the upper 32 bits to indicate what ISA mode we’re in, i.e. v7, Thumb, v8, etc. since it is possible to switch between them. Curtis From: gem5-users [mailto:gem5-use

Re: [gem5-users] arm, aarch64: asymmetry between load-pair and store-pair implementation

Hi Arthur, Apologies on the delay in responding. Thanks for looking into this. As to why it is that way, I think it's mostly an accident of history. If you were to reimplement the store pair as a single 128 bit store we would be in support of the patch entering mainline gem5. It is reasonable to

Re: [gem5-users] DRAMCtrl parameters for DDR4_2400_8x8

Hi all, I've posted Wendy's fix: https://gem5-review.googlesource.com/c/public/gem5/+/8101 We're a maintainer-ack away from getting the fix merged. Thanks, Curtis -Original Message- From: gem5-users [mailto:gem5-users-boun...@gem5.org] On Behalf Of Wendy Elsasser Sent: Friday, February