Hi,
I am trying to take simpoints for a X86 multicore machine. I compiled
version 21.0.1 for X86_MOESI_Hammer protocol, and applied KVM patches.
Now, I can boot up and see all the cores online. However, when I pass
--take-simpoint-checkpoint arguments with simpoint files and intervals,
what
Can someone explain the trick behind "RubySystem::memWriteback()" function?
More specifically, why all events first dequeued from ruby's queue and then
simulation invoked with the current tick, and fianlly all events are
written back to the queue?
On Fri, Jun 11, 2021 at 1:08 PM Majid Jalili
Hi,
I hope you read this email entirely.
I have been working with gem5, for now, more than a few years. However, I
am still struggling with multicore simulation, although I have found
single-core simulation very convenient with gem5. This is particularly
weird given lots of new features are
Has anyone faced the following error when compiling gem5 on an ARM host?
error: 'struct kvm_sync_regs' has no member named 'device_irq_level
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Hi,
checkpoint_aggregator.py works on X86 checkpoints, has anyone converted it
to work with ARM checkpoints ?
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a file), which seems doable for a microbenchmark, but
> maybe not for a large workload.
>
> Arthur
> On 4/15/21 5:18 AM, Majid Jalili via gem5-users wrote:
>
> I have tried this option, the problem is for a simple microbenchmark, if I
> do not use KVM, the IPCs make no sens
Hi,
Can someone help me to understand the difference between the snoop filter
and the directory? They are very similar in terms of functionality, but I
do not understand the differences.
Majid
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To
Hi,
When I was running SPEC CPU 2017, in particular 505.mcf_r, I noticed that
if gem5 should open a file, it will not make any progress. I dig into mcf
code and found when the read_min function is called the simulation freezes.
Then I started running a simple benchmark as follows, that just prints
> Davis,
> CA, 95616
>
> web: https://www.bobbybruce.net
>
>
> On Fri, Apr 9, 2021 at 2:29 PM Majid Jalili via gem5-users <
> gem5-users@gem5.org> wrote:
>
>> Hi,
>>
>> Is it practically possible to convert the KVM-taken checkpoint such that
>>
Hi,
Why does the recent version of gem5 takes very long on the last step when
creating the gem5.opt? My 2-month old repo is just fine, but the new
version takes a very long to finish link.
I tried on three different machines with the different OS but no
improvement.
Hi,
Is it practically possible to convert the KVM-taken checkpoint such that I
can restore it with Atomic CPU? This is particularly important because I
have to use KVM to take my checkpoints on an ARM machine and then transfer
them to my X86 cluster to run the checkpoints.
I cannot avoid KVM on
Matching up performance with that of a real machine is extremely difficult.
I have been trying this and usually cannot come very close. However, you
can find my advice below:
1) Use prefetchers, at least one per level. They can make a huge
difference! For example, for predictable access patterns
Hi,
I am using the following commands for the fs.py and fs_bigLITTLE.py:
./build/ARM/gem5.opt ./configs/example/fs.py --caches --mem-size=64GB
--kernel /home/cc/disks/binaries/vmlinux.arm64 --disk
/home/cc/disks/disks/ubuntu-18.04-arm64-docker_big.img -n 4 --machine-type
VExpress_GEM5_V1
Thanks for the reply!
I'm using MESI_Threee_Level. I checked both develop and stable branches.
Based n what I see, only one prefetcher is created at this line
https://github.com/gem5/gem5/blob/eb919229e63c4daa208a1d9e4856755c1e914154/configs/ruby/MESI_Three_Level.py#L129
Also, by looking at the
Thanks, that's great!
I just have a follow-up question: Can we have CHI for X86? I compiled gem5
for X86_CHI, and it was compiled successfully. However, I was wondering if
it would be working correctly in terms of functionality and for longer
runs?
On Fri, Jul 16, 2021 at 10:26 AM Gabriel Busnot
Could you
> try to rebuild the bootloader in system/arm/bootloader/arm64 and make sure
> the config script is pointing to it?
> (Either with M5_PATH or by using the --bootloader option)
>
> Please let me know if this works
>
> Kind Regards
>
> Giacomo
>
> > -----Or
Has anyone attempted to enable L2 and L1 prefetchers for Ruby? I have seen
the L0 prefetcher, but could not find L1 and L2's. I am trying to add such
a feature, but I found the L1 and L2's state machines more complicated than
L0's. Do you have any advises?
Majid
Hi,
Is there any way or trick to make a debug flag conditional? For example,
--Debug-flags=Cache if pkt->getAddr()==0xABCD
Thanks!
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Hi,
I am trying to take simpoint for some SPEC 17 applications, using the
command below in fs mode:
sudo build/X86/gem5.opt -d lbm_checkpoint ./configs/example/fs.py --caches
--l2cache -n 1 --disk-image /home/cc/disks/disks/linux-x86.spec.img
--kernel /home/cc/disks/binaries/vmlinux-4.19.83
This is the commit breaking the simulation:
https://github.com/gem5/gem5/commit/d0b7de0f870d22f7d271ad0c698567b24d38fe80
I am still trying to figure out what needs to be fixed. Any help would be
appreciated!
On Tue, Feb 15, 2022 at 1:59 PM Majid Jalili wrote:
> Hi,
>
> I am trying to take
Hi,
I compiled the latest stable version of gem5 and tested the Hello World:
build/X86/gem5.opt ./configs/example/se.py --caches --l2cache -n 1 -c
tests/test-progs/hello/bin/x86/linux/hello --cpu-type=DerivO3CPU
However, as soon as I enable the -F flag to fast-forward with the atomic
CPU, I
With lld, it is way faster! I'm done to 25 seconds.
Thanks!
[I did not get your email Gabriel in my inbox to reply to]
On Wed, Mar 23, 2022 at 10:35 PM Majid Jalili wrote:
> Hi,
>
> I feel compiling gem5 is taking longer than what it should take for me. I
> was wondering if anyone can measure
Hi,
I feel compiling gem5 is taking longer than what it should take for me. I
was wondering if anyone can measure and report for this scenario:
[a routine scenario happens when we debug]:
Compile gem5. Then touch one cc file, and then recompile with the command
below:
time scons
Hi,
The default value for the snoop directory is 8MiB. I am trying to find the
minimum size for my configuration. I ran a dual-core system (-n 2) with 2
levels of caches with one L1D prefetcher (DCPT), with small L1 and L2
caches:
build/X86/gem5.fast ./configs/example/se.py --caches --l2cache
Hi,
Make sure your system has enough MSHRs, out of the box, L1, and L2 are set
to have a few MSHR entries.
Also, stride prefetcher is not the best, you may try something better: DCPT
gives me better numbers.
On Fri, Apr 15, 2022 at 4:57 AM Zicong Wang via gem5-users <
gem5-users@gem5.org> wrote:
I think it is hard to get to a real machine level in terms of BW. But By
looking at your stats, I found the lsqFullEvents is high.
You can go after the CPU to make it more aggressive, increasing Load/Store
queue size, and ROB depth are the minimal changes you can make. I
usually do at least ROB
Hi,
You can find the configuration I usually use. There are a few things that
are a bit unrealistic, for example, large SQ size, but I usually do so to
account for better features on a real machine that we do not have at the
moment. The command would have:
--cpu-type=DerivO3CPU
ce
>> Room 3050,
>> Kemper Hall, UC Davis
>> Davis,
>> CA, 95616
>>
>> web: https://www.bobbybruce.net
>>
>>
>> On Thu, Feb 17, 2022 at 11:52 AM Majid Jalili via gem5-users <
>> gem5-users@gem5.org> wrote:
>>
>>>
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