[gem5-users] Response for WritebackDirty packets (learning.gem5)

2018-05-20 Thread Muhammad Ali Akhtar
tor output, it seems that it moves on to next instrutions without waiting for response from memory for this particular request. Muhammad Ali Akhtar Principal Design Engineer http://www.linkedin.com/in/muhammadakhtar ___ gem5-users mailing list gem5-users@gem5.

Re: [gem5-users] Response for WritebackDirty packets (learning.gem5)

2018-05-25 Thread Muhammad Ali Akhtar
ase Memory is blocked and called 'sendReqRetry()" later. Muhammad Ali Akhtar Principal Design Engineer http://www.linkedin.com/in/muhammadakhtar On Tue, May 22, 2018 at 3:40 AM, Jason Lowe-Power <ja...@lowepower.com> wrote: > Hello, > > No. You should not have a response for Writeb

[gem5-users] How to distinguish b/w Instruction and Data in L2

2018-02-13 Thread Muhammad Ali Akhtar
and instruction blocks? Muhammad Ali Akhtar Principal Design Engineer http://www.linkedin.com/in/muhammadakhtar ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

[gem5-users] Profiling GEM5

2018-03-29 Thread Muhammad Ali Akhtar
As everyone knows, gem5 simulations take loong time. Can anyone comment on which parts of code in gem5 itself are most time consuming / computationally intensive?. e.g. Fetch Routines, Decode / Execute functions or what else? I am talking about TimingSimple x86 CPU. -- Muhammad Ali Akhtar