Re: [gem5-users] Cache Management

2018-08-06 Thread Abhishek Singh
; > > *From: *gem5-users on behalf of Timon > Evenblij > *Reply-To: *gem5 users mailing list > *Date: *Monday, 6 August 2018 at 06:56 > *To: *gem5 users mailing list > *Subject: *Re: [gem5-users] Cache Management > > > > Hi Abishek, > > > > Everything

Re: [gem5-users] Cache Management

2018-08-06 Thread Abhishek Singh
second request with the first and > will service both of them at once when the response arrives to L1. > > > > Nikos > > > > *From: *gem5-users on behalf of Timon > Evenblij > *Reply-To: *gem5 users mailing list > *Date: *Monday, 6 August 2018 at 06:56 > *To

Re: [gem5-users] Cache Management

2018-08-06 Thread Nikos Nikoleris
of Timon Evenblij Reply-To: gem5 users mailing list Date: Monday, 6 August 2018 at 06:56 To: gem5 users mailing list Subject: Re: [gem5-users] Cache Management Hi Abishek, Everything is possible, it all depends on the cache policy. I think the default behavior in gem5 is a write-back cache, and I

Re: [gem5-users] Cache Management

2018-08-05 Thread Timon Evenblij
Hi Abishek, Everything is possible, it all depends on the cache policy. I think the default behavior in gem5 is a write-back cache, and I am not sure if any other policies are implemented (Can someone else confirm?). A write-back cache only writes the data back upon eviction, unlike a

Re: [gem5-users] Cache Management

2018-08-05 Thread Abhishek Singh
Hi Timon, I had one question eviction of write back. What happens when a dirty block is evicted from L1 cache. Does it check L2 cache updates the content of that block in L2 and then goes to memory and update contents in memory ? On Thu, Aug 2, 2018 at 4:04 AM Timon Evenblij wrote: > Hi

Re: [gem5-users] Cache Management

2018-08-02 Thread Timon Evenblij
Hi Abishek, No, for this case, MSHRs (miss status handling registers) exists. These are registers that keep track of missed cache accesses (in your case packet 1 that misses in L1), so the cache can be freed to reply to other accesses (packet 2) while waiting for the answer of the miss (packet 1