A more up-to-date version of the tutorial can be found at
http://learning.gem5.org. This is where it will live for the foreseeable
future.
Jason
On Mon, Feb 27, 2017 at 5:58 AM Serhat Gesoglu <
serhat.geso...@manchester.ac.uk> wrote:
> Hello,
> L3 cache is not implemented in gem5 but you can
Hello,
L3 cache is not implemented in gem5 but you can manually implement it (and add
a command line option such as --l3caches), unless you are using ruby (as far as
I know due to not having a 3-level coherence protocol).
You may want to check this tutorial for more information about adding
Dear Trophy,
Thank you for the inspiring help.
The problem has been fixed.
It is indeed the missing of the l2 option that causes this issue.
Chao Zhang
Peking University
在 2013-7-18，下午12:28，Trophy Zheng nimeitia...@gmail.com 写道：
Hi Chao,
I think you still have to connect the cpu ports
HI Chao,
Do you notice that there is :
if options.l2cache:
system.cpu[i].connectAllPorts(system.tol2bus, system.membus)
else:
system.cpu[i].connectAllPorts(system.membus)
in the original configuration file.
So, if you config l4cache, there will be no
Dear Trophy,
Thank you very much!
I'm so stupid to forget the l2option issue, to connect the cpu ports to l4bus
at the end of the configuration, just as that you pointed out.
But after this has been figured out, a new error comes.
I need a cache system with shared L2, shared l3 and shared l4. So
Hi Chao,
I think you still have to connect the cpu ports to the l2bus. Just make
sure the options.l2cache exists, in order to make the
system.cpu[i].connectAllPorts(system.tol2bus, system.membus) works.
Best,
On Thu, Jul 18, 2013 at 10:21 AM, Chao Zhang zhang.c...@pku.edu.cn wrote:
Dear
Are you using Ruby? If yes, then you will have to write a three level
coherence protocol first.
--
Nilay
On Wed, 8 Feb 2012, Simon Hammond wrote:
Hey guys,
Can you tell me how I can configure a simulation to use a L3 cache?
I have taken a look in the simulation scripts provided and the CPU
