On Thu, 26 Nov 2015 20:19:08 +0100
Tristan Gingold wrote:
> > Is it somehow possible to tell ghld, "yes, i know there is something
> > not ok, but please just stop this one assert from file X at line Y" ?
> > If possible without disabling all others.
>
> Not exactly but what
On Thu, 26 Nov 2015 21:23:41 +0100
Attila Kinali wrote:
> BTW: that bug is kind of puzzling me, i cannot see the error in my code.
Ok. I think this is a bug in ghdl.
Attached is a file that demonstrates it. I run it with:
ghdl -i --std=08 ctrl_algo.vhd &&
ghdl -m --std=08
On 27/11/15 01:31, David Koontz wrote:
On 27/11/2015, at 11:47 am, Attila Kinali > wrote:
It seems like there is some strange interaction between the TDC_BUF
process
and its for loops and the TDCSIGNAL generate statement at the bottom.
Longest
> On 27/11/2015, at 4:43 pm, Tristan Gingold wrote:
>
> I would simply add that this is one of vhdl pitfall. VHDL behaviour
> is not very intuitive.
>
> This could be detected at elaboration time by using std_ulogic instead of
> std_logic.
>
> (You'd better to always use
Moin,
I just build myself a larger testbench that takes larger array of
randomly generated real values and casts them into an sfixed.
For obvious reasons i get this warning:
../../src/ieee2008/fixed_generic_pkg-body.vhdl:2546:9:@57675ps:(assertion
warning):
On 26/11/15 11:28, Simon Thijs de Feber wrote:
Currently I am building ghdl with Slackware-current 32-bit version.
This release has native gcc @ 4.9.3
Using the build script from sourceforge.
All works fine except for the ghdl-install itself.
Can fix it by copying the required files.
Great.
On 26/11/15 18:41, Attila Kinali wrote:
Moin,
I just build myself a larger testbench that takes larger array of
randomly generated real values and casts them into an sfixed.
For obvious reasons i get this warning:
../../src/ieee2008/fixed_generic_pkg-body.vhdl:2546:9:@57675ps:(assertion
On 26/11/15 08:08, KIMURA Masaru wrote:
FYI, and you may know, but i've not tested actually,
some closed source VHDL simulators (such as Aldec Riviera-PRO) have
relax
options (e.g. integer range), IIRC.
Never heard about that. Any pointer or detail about this feature
would be useful.
e.g.