On 12 October 2016 at 13:32, Frank Kleinewoerdemann
wrote:
>
> the solder joints on the U20 and the NXP TQFP package look tip-top.
Better than on the X3 crystal ;-)
>
> I got the signals of P81(/WP), P82(/HOLD) and P68(/CS) into the logic
analyzer. Set the trigger to /CS
Hi
the solder joints on the U20 and the NXP TQFP package look tip-top. Better
than on the X3 crystal ;-)
I got the signals of P81(/WP), P82(/HOLD) and P68(/CS) into the logic
analyzer. Set the trigger to /CS falling edge.
On hackrf_spi flash write, the /HOLD and /WP are high level throughout
On 8 October 2016 at 22:34, Frank Kleinewoerdemann
wrote:
> On Sat, Oct 8, 2016 at 6:25 PM, Dominic Spill wrote:
>>
>> > There is also SPI data after reset/reboot but it's not what was sent
to the SPI flash and the clock signal in relation to MOSI/MISO
Hi,
thanks for your response!
Rest is inline.
On Sat, Oct 8, 2016 at 6:25 PM, Dominic Spill wrote:
> On 5 October 2016 at 10:41, Frank Kleinewoerdemann
> wrote:
> >
> > I had a HackRF One with firmware version 2014.08.1 working with Linux,
>
On 5 October 2016 at 10:41, Frank Kleinewoerdemann
wrote:
>
> I had a HackRF One with firmware version 2014.08.1 working with Linux,
Android OTG as well as Windows gear.
Is 2014.08.1 the firmware that came on the device?
> If I skip the CPLD update and press the reset