Re: Question about negative indexes

I think I understand where you got confused. Quoting: "Addresses generated by the CPU that may be virtual addresses always wrap." The cases where interrupts can happen are not with virtual memory accesses (such as your example). Eric Rossman, CISSP® ICSF Cryptographic Security Development

Re: Question about negative indexes

On Sat, 23 Oct 2021 21:16:48 -0400, Eric D Rossman wrote: >You are welcome to submit an RCF. However, the interruption is not on >accessing storage. It is on the address wrapping. > >I'm not involved in the architecture but I strongly doubt that the book is >wrong. > >Eric Rossman, CISSP� >ICSF

Re: Question about negative indexes

You are welcome to submit an RCF. However, the interruption is not on accessing storage. It is on the address wrapping. I'm not involved in the architecture but I strongly doubt that the book is wrong. Eric Rossman, CISSP® ICSF Cryptographic Security Development z/OS Enabling Technologies

Re: Question about negative indexes

Everybody has a senior moment every now and then after 55, including me. Joe On Sat, Oct 23, 2021 at 7:44 PM Seymour J Metz wrote: > The D value is the offset of the literal from the relevant USING. the R > values is the register from the USING and the X value is zero. This is very > basic

Re: Question about negative indexes

On Sat, 23 Oct 2021 20:21:53 -0400, Eric D Rossman wrote: > >In Chapter 3 (Storage), section Address Wraparound: > >When, during the generation of the address, ... >... >1. The carry out of the high-order bit position of the address is ignored. > >2. An interruption condition is recognized. >

Re: Question about negative indexes

The D value is the offset of the literal from the relevant USING. the R values is the register from the USING and the X value is zero. This is very basic stuff. -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 From: IBM Mainframe Discussion

Re: Question about negative indexes

OK thanks :) Joe On Sat, Oct 23, 2021 at 7:37 PM David Spiegel wrote: > Hi Joe, > You are forgetting that '=H' creates a storage area of a half-byte, > which is addressed by the RX Instruction. > Here is what happens: >Active Usings: None >Loc Object CodeAddr1 Addr2 Stmt Source

Re: Question about negative indexes

Hi Joe, You are forgetting that '=H' creates a storage area of a half-byte, which is addressed by the RX Instruction. Here is what happens:   Active Usings: None   Loc  Object Code    Addr1 Addr2  Stmt   Source Statement  HLASM R6.0  2021/10/23 20.37 00 

Re: Question about negative indexes

By definition, base and index registers are treated as 64 bit binary values (unsigned), with only the relevant bits (24, 31, or 64) used. The relevant bits are simply added with overflow discarded. There is no sign bit to ignore. In Chapter 3 (Storage), section Address Wraparound: When,

Re: Question about negative indexes

OK then explain this: LH is an RX format instruction. What are the D, X and B values if the second operand is simply =H'-5'? Joe On Sat, Oct 23, 2021 at 6:49 PM Paul Gilmartin < 000433f07816-dmarc-requ...@listserv.ua.edu> wrote: > On Sat, 23 Oct 2021 18:36:54 -0500, Joe Monk wrote: > > >LH

Re: Question about negative indexes

Use LGH instead of LH (or maybe even LGHI). If you are not in AMODE 64, you probably don't care about messing with the high order half of the register. In this case, the low order bits of the register will contain the same value they would have contained with LH. -Original Message-

Re: Question about negative indexes

On Sat, 23 Oct 2021 18:36:54 -0500, Joe Monk wrote: >LH is an RX instruction. > >So, LH 3,=H'-5' would give an addressing exception, no? Because the second >operand is treated as coming from storage? So that would be a negative >address? > No. >If you said LH 3,0(=H'-5',2), that would give you

Re: Question about negative indexes

LH is an RX instruction. So, LH 3,=H'-5' would give an addressing exception, no? Because the second operand is treated as coming from storage? So that would be a negative address? If you said LH 3,0(=H'-5',2), that would give you ITEM+5? Joe On Sat, Oct 23, 2021 at 6:01 PM Bernd Oppolzer

Re: Question about negative indexes

On Sun, 24 Oct 2021 00:57:53 +0200, Bernd Oppolzer wrote: >So this means that > >LA   2,ITEM+10 >LH   3,=H'-5' >LA   2,0(2,3) > >will put the address ITEM+5 in register 2, at least in AMODE 24/31? > I believe so. BTW, the HLASM Ref. says the address operand of a USING must be non-negative, but

Re: Question about negative indexes

So this means that LA   2,ITEM+10 LH   3,=H'-5' LA   2,0(2,3) will put the address ITEM+5 in register 2, at least in AMODE 24/31? With AMODE 64, this will be a problem, because the LH instruction only fills the right half of the 64 bit register 3, right? Is there a way to do this right in

Re: Vector examples?

Thanks again to all who assisted. I got my example working. Biggest problems were lack of understanding of the basic architecture (128-bit registers that can be logically segmented into quadwords, doublewords, fullwords, halfwords, and/or bytes, depending on the function) and then, once I had

Re: IBM z/OS Learner's Edition

On Sat, Oct 23, 2021 at 01:59:49PM -0400, Mark Regan wrote: > I've done that options #2 process too, and all I have received back is a > canned response that says: > > Contact request confirmation - Your request to be contacted by IBM Sales > was received. We will contact you as soon as your

Re: Question about negative indexes

I'm pretty sure that given the context, the question is about AMODE 64 on z/Architecture. To the original question: the sign is never "ignored". But there is no sign on base or index addresses. They are treated as unsigned numbers with the length of addresses of the current AMODE. When added

Re: Question about negative indexes

On Sat, Oct 23, 2021 at 7:41 PM Paul Gilmartin <000433f07816-dmarc-requ...@listserv.ua.edu> wrote: > > On Sat, 23 Oct 2021 11:33:33 -0500, Joe Monk wrote: > > > >I know this will probably be an easy answer for somebody... but I dont deal > >with AM64 much. > > > AMD64?

Re: IBM z/OS Learner's Edition

The Learners Edition will only support z/OS. These links detail the breakdown for each edition of ZD: https://www.ibm.com/products/z-development-test-environment/pricing https://www.ibm.com/docs/en/zdt/13.2.0 Regards, Mark Regan, K8MTR *CTO1 USNR-Retired, 1969-1991* *Nationwide Insurance,

Re: IBM z/OS Learner's Edition

On Sat, 23 Oct 2021 12:26:40 -0500, Kevin Monceaux wrote: >On Tue, Oct 12, 2021 at 11:19:41AM -0500, Lionel B. Dyck wrote: >> More information https://ibm.github.io/zdt-learners-edition-about/ >> >I went with the single step under option 2 and e-mailed sales. I received a >reply back with

Re: Question about negative indexes

On Sat, 23 Oct 2021 11:33:33 -0500, Joe Monk wrote: > >I know this will probably be an easy answer for somebody... but I dont deal >with AM64 much. > AMD64? >If Im in AM64 and I load an index register with -1, does the machine ignore >the sign when using

Re: IBM z/OS Learner's Edition

I've done that options #2 process too, and all I have received back is a canned response that says: Contact request confirmation - Your request to be contacted by IBM Sales was received. We will contact you as soon as your question is answered. I'm still waiting for a response from them.

Re: IBM z/OS Learner's Edition

On Tue, Oct 12, 2021 at 11:19:41AM -0500, Lionel B. Dyck wrote: > More information https://ibm.github.io/zdt-learners-edition-about/ > > According to this there are 3 steps to acquire with the 3rd being to contact > IBM Sales - I've been on an online chat with them for 30+ minutes and they >

Re: Question about negative indexes

On Sat, 23 Oct 2021 11:33:33 -0500 Joe Monk wrote: :>Howdy, :>I know this will probably be an easy answer for somebody... but I dont deal :>with AM64 much. :>If Im in AM64 and I load an index register with -1, does the machine ignore :>the sign when using it in an RX instruction such as STC?

Question about negative indexes

Howdy, I know this will probably be an easy answer for somebody... but I dont deal with AM64 much. If Im in AM64 and I load an index register with -1, does the machine ignore the sign when using it in an RX instruction such as STC? I know it ignores the sign in AM24/31... Thanks, Joe

Re: Mainframe Modernization

On 23/10/2021 6:52 am, Andrew Rowley wrote: On 22/10/2021 8:21 pm, David Crayford wrote: I wouldn't consider a drag race using a prime number sieve a good indication of the overall performance of Java on z/OS. That's a very specific use case and not one that anybody would ever use on the