On Thu, 5 Sep 2019 04:54:02 +, Jon Perryman wrote:
>>SVC allows you to execute authorized code in YOUR address space.
I should have said "SVC invokes a system service that runs in
Supervisor state in your address space."
>>It does not allow you to execute code in any arbitrary address
> SVC allows you to execute authorized code in YOUR address space.
> It does not allow you to execute code in any arbitrary address space.
There is no YOUR address space. E.g. Getmain belongs to RSM but run authorized
in any address space that uses the getmain macro.
>From a product
On Sat, 31 Aug 2019 01:16:55 +, Jon Perryman wrote:
>>What you describe as being able to run code in any
>>address space sounds more like scheduling an SRB.
>
>SRB is one method to execute authorized code in any address space
>but surely you must be familiar with others such as SVC, PC and
> What you describe as being able to run code in any
> address space sounds more like scheduling an SRB.
SRB is one method to execute authorized code in any address space but surely
you must be familiar with others such as SVC, PC and IEFSSREQ. Or are you
suggesting that getmain and storage
(ITOP NM) - KLM
Sent: Friday, August 30, 2019 3:07 AM
To: IBM-MAIN@LISTSERV.UA.EDU
Subject: Re: Assembler :- PC Instruction
A little less I think.
I remember their meaning became vague when comparing performance and MIPS of
Amdahl and IBM machines gave unexplainable differences during the 80's
du/~smetz3
From: IBM Mainframe Discussion List on behalf of
Peter Relson
Sent: Friday, August 30, 2019 8:24 AM
To: IBM-MAIN@LISTSERV.UA.EDU
Subject: Re: Assembler :- PC Instruction
>From what I understood of the PC instruction: with 1 instruction you ca
19 5:25 AM
To: IBM-MAIN@LISTSERV.UA.EDU
Subject: Re: Assembler :- PC Instruction
>From what I understood of the PC instruction: with 1 instruction you can
now execute a 'function' that might have taken pages of assembler
instructions before.
I'm not sure where this thought comes
On Thu, 29 Aug 2019 20:59:02 +, Jon Perryman wrote:
>As for "executing authorized code in other address spaces", I actually meant
>any address space.
What do you mean by that? A PC instruction can pass control to code
in a specific address space, as defined when the PC routine was
From: Tom Marchant <000a2a8c2020-dmarc-requ...@listserv.ua.edu>
To: IBM-MAIN@LISTSERV.UA.EDU
Date: 30/08/2019 16:00
Subject: Re: Assembler :- PC Instruction
Sent by:IBM Mainframe Discussion List
On Thu, 29 Aug 2019 19:56:57 -1000, Anne & Lynn Wheeler wrote:
On Thu, 29 Aug 2019 19:56:57 -1000, Anne & Lynn Wheeler wrote:
>in the wake of the FS faulure (FS was going to be completely different
>than 370, and 370 efforts were being shutdown during FS period, also
>lack of 370 offerings during FS period is credited with giving clone
>mainframe vendors
U
> Subject: Re: Assembler :- PC Instruction
>
>
> From what I understood of the PC instruction: with 1 instruction you can
> now execute a 'function' that might have taken pages of assembler
> instructions before.
>
>
> I'm not sure where this thought comes from.
>From what I understood of the PC instruction: with 1 instruction you can
now execute a 'function' that might have taken pages of assembler
instructions before.
I'm not sure where this thought comes from. The PC instruction is not
magic. It does not execute a "function" beyond the function
of Processor Speed.
Kees.
> -Original Message-
> From: IBM Mainframe Discussion List [mailto:IBM-MAIN@LISTSERV.UA.EDU] On
> Behalf Of Seymour J Metz
> Sent: 29 August, 2019 19:04
> To: IBM-MAIN@LISTSERV.UA.EDU
> Subject: Re: Assembler :- PC Instruction
>
> SVC
apoorva.kanm...@gmail.com (SUBSCRIBE IBM-MAIN Anonymous) writes:
> I have a question on PC instruction for which I have been looking for
> an answer for quite sometime now. According to "Priciples of
> operations" manual, execution of an SVC instruction causes a new PSW
> to be loaded from x'1C0'
My point with ETCRE was that it is the start of the black box. You can't just
depend upon this being a hardware only instruction nor can you rely upon your
PC routine to be started directly from the instruction. IBM could easily pass
your routine's address in another parm. Only someone who's
>> The PC instruction is a replacement for SVC.
> That's one use case. What about privileged code that scheduled an SRB into
> another address space and waited for a cross-memory post? A PC is potentially
> much less overhead.
PC routines are not necessary to use XMEM but they make it so
Of course PC is the replacement for SVC. You have to look at SVC when PC came
out and how it was being used. It doesn't matter what it was on OS/360. PC came
out when address spaces and running authorized was available. Nearly every
feature of PC was implemented to address use cases of SVC
From: IBM Mainframe Discussion List on behalf of Jon
Perryman
Sent: Thursday, August 29, 2019 12:10 AM
To: IBM-MAIN@LISTSERV.UA.EDU
Subject: Re: Assembler :- PC Instruction
For "who will perform the translation process", it's not going to be clear.
First, rather than translati
__
From: IBM Mainframe Discussion List on behalf of Jon
Perryman
Sent: Thursday, August 29, 2019 12:22 AM
To: IBM-MAIN@LISTSERV.UA.EDU
Subject: Re: Assembler :- PC Instruction
The PC instruction is a replacement for SVC. Both instructions exist solely
to run authorized programs in other addres
August 29, 2019 12:38 AM
To: IBM-MAIN@LISTSERV.UA.EDU
Subject: Re: Assembler :- PC Instruction
PC does not have a larger address space. It simply has the option to access
other address spaces.
Collisions for PC environments cannot occur because the PC instruction must use
the token returned when y
you want and I'll write the benchmark to prove it's correct.
--
Shmuel (Seymour J.) Metz
http://mason.gmu.edu/~smetz3
From: IBM Mainframe Discussion List on behalf of
scott Ford
Sent: Thursday, August 29, 2019 8:18 AM
To: IBM-MAIN@LISTSERV.UA.EDU
Subje
smetz3
From: IBM Mainframe Discussion List on behalf of
Vernooij, Kees (ITOP NM) - KLM
Sent: Thursday, August 29, 2019 8:27 AM
To: IBM-MAIN@LISTSERV.UA.EDU
Subject: Re: Assembler :- PC Instruction
"against SVC plus the SVC interrupt handler".
Possibly also: Plus S
On Thu, 29 Aug 2019 04:22:02 +, Jon Perryman wrote:
>The PC instruction is a replacement for SVC. Both instructions exist
>solely to run authorized programs in other address spaces.
No. The SVC instruction, as implemented by OS/360 and its descendants,
exists to provide a service that
> how do you measure the performance..?
For the PC instruction, performance is simply a curiosity and doesn't really
matter. The alternatives are SVC and SSI. The benefits of PC far outweigh any
possible savings by using SVC. The SSI is a special use case.
As for measuring performance, is
> Kees.
>
> > -Original Message-
> > From: IBM Mainframe Discussion List [mailto:IBM-MAIN@LISTSERV.UA.EDU] On
> > Behalf Of Peter Relson
> > Sent: 29 August, 2019 13:45
> > To: IBM-MAIN@LISTSERV.UA.EDU
> > Subject: Re: Assembler :- PC Instruction
>
29 August, 2019 13:45
> To: IBM-MAIN@LISTSERV.UA.EDU
> Subject: Re: Assembler :- PC Instruction
>
>
> You can do a BASR and STORAGE OBTAIN, STORAGE RELEASE and BR in less time
> than a BAKR.
>
>
> No you can't.
>
>
> How does its performance stack up against
Peter,
This begs a question for me how do you measure the performance..?
What I am seeing via the post and understanding performance matters even
with the faster Z processors.
Scott
On Thu, Aug 29, 2019 at 7:45 AM Peter Relson wrote:
>
> You can do a BASR and STORAGE OBTAIN, STORAGE RELEASE
You can do a BASR and STORAGE OBTAIN, STORAGE RELEASE and BR in less time
than a BAKR.
No you can't.
How does its performance stack up against SVC?
That's not a useful comparison. What is useful is "how does its
performance stack up against SVC plus the SVC interrupt handler".
Peter
8, 2019 1:09 PM
To: IBM-MAIN@LISTSERV.UA.EDU
Subject: Re: Assembler :- PC Instruction
Correct me if I am wrong. I don't pretend to be an expert on this subject.
I think of SVCs as hailing from the era of centralized monolithic operating
system construction. I would guess that IBM had an "SVC
PC does not have a larger address space. It simply has the option to access
other address spaces.
Collisions for PC environments cannot occur because the PC instruction must use
the token returned when you created the environment. The problem is passing
this token to programs issuing the PC
The PC instruction is a replacement for SVC. Both instructions exist solely
to run authorized programs in other address spaces. PC was designed to fix and
simplify many of those problems with SVC. Some of the important problems
addressed (not all):
1. 256 static defined SVC's replaced by
For "who will perform the translation process", it's not going to be clear.
First, rather than translation, the PC instruction builds the environment from
the token. ETDEF defines the PC environment but ETCRE or ETCON could easily
insert calls into the environment entry without us being
Thanks everyone for all your inputs.
--
For IBM-MAIN subscribe / signoff / archive access instructions,
send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN
J Metz
Sent: Wednesday, August 28, 2019 1:40 PM
To: IBM-MAIN@LISTSERV.UA.EDU
Subject: Re: Assembler :- PC Instruction
An SVC can schedule an SRB into another address space; that may be more
overhead, but it's still space switching. But, yes, there are far fewer use
cases for new VCs these days
Mainframe Discussion List on behalf of
Christopher Y. Blaicher
Sent: Wednesday, August 28, 2019 12:48 PM
To: IBM-MAIN@LISTSERV.UA.EDU
Subject: Re: Assembler :- PC Instruction
Never measured SVC vs PC. While in some cases PC and SVC are similar, in many
ways PC is far superior to SVC. It can
Mills
Sent: Wednesday, August 28, 2019 1:09 PM
To: IBM-MAIN@LISTSERV.UA.EDU
Subject: Re: Assembler :- PC Instruction
Correct me if I am wrong. I don't pretend to be an expert on this subject.
I think of SVCs as hailing from the era of centralized monolithic operating
system construction. I would
ednesday, August 28, 2019 9:48 AM
To: IBM-MAIN@LISTSERV.UA.EDU
Subject: Re: Assembler :- PC Instruction
Never measured SVC vs PC. While in some cases PC and SVC are similar, in
many ways PC is far superior to SVC. It can be local or globally defined
and it can be dynamically defined and removed
Sent: Wednesday, August 28, 2019 12:19 PM
To: IBM-MAIN@LISTSERV.UA.EDU
Subject: Re: Assembler :- PC Instruction
PC and BAKR, which is another stacking type instruction, are not cheap. You
can do a BASR and STORAGE OBTAIN, STORAGE RELEASE and BR in less time than a
BAKR. I do not know for sure
: Wednesday, August 28, 2019 12:19 PM
To: IBM-MAIN@LISTSERV.UA.EDU
Subject: Re: Assembler :- PC Instruction
PC and BAKR, which is another stacking type instruction, are not cheap. You
can do a BASR and STORAGE OBTAIN, STORAGE RELEASE and BR in less time than a
BAKR. I do not know for sure
Technical Architect
Syncsort, Inc.
-Original Message-
From: IBM Mainframe Discussion List [mailto:IBM-MAIN@LISTSERV.UA.EDU] On Behalf
Of scott Ford
Sent: Wednesday, August 28, 2019 11:21 AM
To: IBM-MAIN@LISTSERV.UA.EDU
Subject: Re: Assembler :- PC Instruction
I feel it’s important how to use
From: IBM Mainframe Discussion List on behalf of
SUBSCRIBE IBM-MAIN Anonymous
Sent: Wednesday, August 28, 2019 3:35 AM
To: IBM-MAIN@LISTSERV.UA.EDU
Subject: Re: Assembler :- PC Instruction
Thanks for your response. Yes I agree that PC doesn't involve any
I feel it’s important how to use the instruction and it’s pros and cons.
I am not sure how important speed of instructions or width , halfword or
full word are that pressing of an issue with today’s processors, but that’s
my opinion.
Scott
On Wed, Aug 28, 2019 at 11:18 AM scott Ford wrote:
>
Charles,
Exactly, what is being done under the covers, i.e; microcode etc ..
Scott
On Wed, Aug 28, 2019 at 10:49 AM Tony Harminc wrote:
> On Wed, 28 Aug 2019 at 09:59, Charles Mills wrote:
>
> > In answer to your question, I guess the answer is no. There is a DAT
> "facility" (some of us
On Wed, 28 Aug 2019 at 09:59, Charles Mills wrote:
> In answer to your question, I guess the answer is no. There is a DAT
> "facility" (some of us remember when there was a DAT box!) but no, there is
> no named "PC facility" any more than there is a "BAL facility." It's just
> part of the
28, 2019 12:36 AM
To: IBM-MAIN@LISTSERV.UA.EDU
Subject: Re: Assembler :- PC Instruction
Thanks for your response. Yes I agree that PC doesn't involve any interruption.
"Principles of operations" manual clearly explains the PC translation process
but I wanted to know "Who" will
On Wed, 28 Aug 2019 02:35:47 -0500 SUBSCRIBE IBM-MAIN Anonymous
wrote:
:>Thanks for your response. Yes I agree that PC doesn't involve any
interruption. "Principles of operations" manual clearly explains the PC
translation process but I wanted to know "Who" will perform this translation
Thanks for your response. Yes I agree that PC doesn't involve any interruption.
"Principles of operations" manual clearly explains the PC translation process
but I wanted to know "Who" will perform this translation process? For example
we have "Dynamic Address translation" facility to transform
RIBE IBM-MAIN Anonymous
:>> Sent: 28 August, 2019 8:36
:>> To: IBM-MAIN@LISTSERV.UA.EDU
:>> Subject: Assembler :- PC Instruction
:>>
:>> I have a question on PC instruction for which I have been looking for an
:>> answer for quite sometime now. According to "P
t: 28 August, 2019 8:36
> To: IBM-MAIN@LISTSERV.UA.EDU
> Subject: Assembler :- PC Instruction
>
> I have a question on PC instruction for which I have been looking for an
> answer for quite sometime now. According to "Priciples of operations"
> manual, executio
I have a question on PC instruction for which I have been looking for an answer
for quite sometime now. According to "Priciples of operations" manual,
execution of an SVC instruction causes a new PSW to be loaded from x'1C0' (SVC
FLIH), and program interruption causes a new PSW loaded from
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