BAKR (was Re: Question about negative indexes)

I don't know why BAKR/PR is "slow" either, but I do know that it's not really significant except in very intense usage. I worked on a product that used it for all calls except small internal subroutines. And avoided a whole bunch of errors caused by mismatched linkage conventions, not to mention

Re: Question about negative indexes

On Tue, Oct 26, 2021 at 7:16 AM Peter Relson wrote: > John M wrote: > > I really would like the Linkage Stack to become generally > useful. So I could just use a BAKR to save state on entry and PC to > return. > > > In what way does BAKR...PR not let you accomplish that (if by "state" you > are

Re: Question about negative indexes

John M wrote: I really would like the Linkage Stack to become generally useful. So I could just use a BAKR to save state on entry and PC to return. In what way does BAKR...PR not let you accomplish that (if by "state" you are referring to thing such as registers and PSW state)? BAKR 14,0 ... P

Re: Question about negative indexes

On Sun, 24 Oct 2021 at 12:11, Paul Gilmartin <000433f07816-dmarc-requ...@listserv.ua.edu> wrote: > What I believe most important is to clarify the distinction between address > generation and storage access. It's easy to overlook this distinction > because 99+% of instructions performing addr

Re: Question about negative indexes

former. Charles -Original Message- From: IBM Mainframe Discussion List [mailto:IBM-MAIN@LISTSERV.UA.EDU] On Behalf Of Peter Relson Sent: Monday, October 25, 2021 6:55 AM To: IBM-MAIN@LISTSERV.UA.EDU Subject: Re: Question about negative indexes This discussion has morphed into a discussion

Re: Question about negative indexes

You will take a performance hit (unless things have improved) On Mon, 25 Oct 2021 09:04:02 -0500 John McKown wrote: :>Personally, I really would like the Linkage Stack to become generally :>useful. So I could just use a BAKR to save state on entry and PC to return. :>Not likely, but y can dream.

Re: Question about negative indexes

Personally, I really would like the Linkage Stack to become generally useful. So I could just use a BAKR to save state on entry and PC to return. Not likely, but y can dream. At least until I retire sometime next year. Dates to get rid of our z9BC keep getting pushed back. But my boss says he's pla

Re: Question about negative indexes

This discussion has morphed into a discussion of linkage conventions which are clearly spelled out in the publications, such as with respect to save area sizes and formats. I suggest that those interested take the time to re-read those sections. A "legacy" AMODE 24 or AMODE 31 routine will not e

Re: Question about negative indexes

21 2:14 PM To: IBM-MAIN@LISTSERV.UA.EDU Subject: Re: Question about negative indexes Not necessarily. An A64 routine can step down to call an A31 routine which will not save top halves and will only provide an 18 word save area. On Sun, 24 Oct 2021 17:23:31 + Seymour J Metz wrote: :>

Re: Question about negative indexes

On Sun, 24 Oct 2021 19:28:42 +, Gibney, Dave wrote: >Seem that is this case, it would be the responsibility of the new A64 code >(by definition, A64 code is new) to protect itself by saving before the call >and restoring after. > That may not be necessary. If the AMODE 24/31 subroutine is

Re: Question about negative indexes

Sent: Sunday, October 24, 2021 11:14 AM > To: IBM-MAIN@LISTSERV.UA.EDU > Subject: Re: Question about negative indexes > > Not necessarily. > > An A64 routine can step down to call an A31 routine which will not save top > halves and will only provide an 18 word save area. >

Re: Question about negative indexes

: Sunday, October 24, 2021 5:58 AM :>To: IBM-MAIN@LISTSERV.UA.EDU :>Subject: Re: Question about negative indexes :> :>Well :> :>Your only serious issue would be when the calling chain includes a 64bit which :>steps down to 31bit which then invokes your 64bit code,

Re: Question about negative indexes

behalf of Binyamin Dissen Sent: Sunday, October 24, 2021 5:58 AM To: IBM-MAIN@LISTSERV.UA.EDU Subject: Re: Question about negative indexes Well Your only serious issue would be when the calling chain includes a 64bit which steps down to 31bit which then invokes your 64bit code, as the

Re: Question about negative indexes

; Sent: Saturday, October 23, 2021 8:54 PM To: IBM-MAIN@LISTSERV.UA.EDU Subject: Re: Question about negative indexes On Sat, 23 Oct 2021 20:21:53 -0400, Eric D Rossman wrote: > >In Chapter 3 (Storage), section Address Wraparound: > >When, during the generation of the address, ... >

Re: Question about negative indexes

On Sun, 24 Oct 2021 10:27:36 -0400, Eric D Rossman wrote: >... >I do agree that you should submit an RCF to get that section cleared up. >When none of the multiple technical folks reading a definitive source >(Principles of Operations) don't understand what something means in a >given contex

Re: Question about negative indexes

On Sun, 24 Oct 2021 08:55:00 -0400 Peter Relson wrote: :>Therefore we conclude that this statement is not correct for the case of :>CPU table entries addressed by real or absolute addresses. :>(I don't know exactly what a "CPU table entry" is in this context.) DAT-table entries when used for im

Re: Question about negative indexes

By the way, I just wanted to say that I REALLY ENJOY these sorts of conversations (technical ones) on this list. The obnoxious sniping we are seeing between some of our members needs to stop. I don't understand why the moderators let it continue. If it were me, the folks doing the sniping would

Re: Question about negative indexes

Yes, long (20-bit) displacements can be negative, while regular (12-bit) displacement can not. Eric Rossman, CISSP® ICSF Cryptographic Security Development z/OS Enabling Technologies edros...@us.ibm.com "Hobart Spitz" : > AFAIK, RXY format instructions support negative offsets just fine. > > L

Re: Question about negative indexes

On Sun, 24 Oct 2021 08:55:00 -0400, Peter Relson wrote: >... >That post omitted this phrase from the PoP that follows shortly after: > >For CPU table entries that are addressed by real or absolute addresses, it >is unpredictable >whether the address wraps or an addressing exception is recogniz

Re: Question about negative indexes

AFAIK, RXY format instructions support negative offsets just fine. LHY 5,-1(0,12) On Sun, 24 Oct 2021, 7:55 am Peter Relson, wrote: > Eric R posted (from the PoP): > > When, during the generation of the address, an > address is obtained that exceeds the value allowed > for the address size (2^

Re: Question about negative indexes

Eric R posted (from the PoP): When, during the generation of the address, an address is obtained that exceeds the value allowed for the address size (2^24 - 1, 2^31 - 1, or 2^64 - 1), one of the following two actions is taken: 1. The carry out of the high-order bit position of the address is igno

Re: Question about negative indexes

Well Your only serious issue would be when the calling chain includes a 64bit which steps down to 31bit which then invokes your 64bit code, as the passed save area will only have room for the bottom halves. You would need to store the top halves in a local work area before initializing th

Re: Question about negative indexes

Thanks a lot. I have found new important (for me) insights from this discussion, that is: similar to the AMODE 24 to AMODE 31 transition, we will face serious problems with existing programs, because such logic as below, which will work correctly with AMODE 24/31, is simply plain wrong with AM

Re: Question about negative indexes

I think I understand where you got confused. Quoting: "Addresses generated by the CPU that may be virtual addresses always wrap." The cases where interrupts can happen are not with virtual memory accesses (such as your example). Eric Rossman, CISSP® ICSF Cryptographic Security Development z/OS

Re: Question about negative indexes

On Sat, 23 Oct 2021 21:16:48 -0400, Eric D Rossman wrote: >You are welcome to submit an RCF. However, the interruption is not on >accessing storage. It is on the address wrapping. > >I'm not involved in the architecture but I strongly doubt that the book is >wrong. > >Eric Rossman, CISSP� >ICSF

Re: Question about negative indexes

You are welcome to submit an RCF. However, the interruption is not on accessing storage. It is on the address wrapping. I'm not involved in the architecture but I strongly doubt that the book is wrong. Eric Rossman, CISSP® ICSF Cryptographic Security Development z/OS Enabling Technologies edros

Re: Question about negative indexes

gt; basic stuff. > > > -- > Shmuel (Seymour J.) Metz > http://mason.gmu.edu/~smetz3 > > > > From: IBM Mainframe Discussion List on behalf > of Joe Monk > Sent: Saturday, October 23, 2021 8:18 PM > To: IBM-MAIN@LISTSERV.

Re: Question about negative indexes

On Sat, 23 Oct 2021 20:21:53 -0400, Eric D Rossman wrote: > >In Chapter 3 (Storage), section Address Wraparound: > >When, during the generation of the address, ... >... >1. The carry out of the high-order bit position of the address is ignored. > >2. An interruption condition is recognized. > I

Re: Question about negative indexes

List on behalf of Joe Monk Sent: Saturday, October 23, 2021 8:18 PM To: IBM-MAIN@LISTSERV.UA.EDU Subject: Re: Question about negative indexes OK then explain this: LH is an RX format instruction. What are the D, X and B values if the second operand is simply =H'-5'? Joe On Sat, Oct 2

Re: Question about negative indexes

OK thanks :) Joe On Sat, Oct 23, 2021 at 7:37 PM David Spiegel wrote: > Hi Joe, > You are forgetting that '=H' creates a storage area of a half-byte, > which is addressed by the RX Instruction. > Here is what happens: >Active Usings: None >Loc Object CodeAddr1 Addr2 Stmt Source

Re: Question about negative indexes

Hi Joe, You are forgetting that '=H' creates a storage area of a half-byte, which is addressed by the RX Instruction. Here is what happens:   Active Usings: None   Loc  Object Code    Addr1 Addr2  Stmt   Source Statement  HLASM R6.0  2021/10/23 20.37 00 

Re: Question about negative indexes

By definition, base and index registers are treated as 64 bit binary values (unsigned), with only the relevant bits (24, 31, or 64) used. The relevant bits are simply added with overflow discarded. There is no sign bit to ignore. In Chapter 3 (Storage), section Address Wraparound: When, during

Re: Question about negative indexes

OK then explain this: LH is an RX format instruction. What are the D, X and B values if the second operand is simply =H'-5'? Joe On Sat, Oct 23, 2021 at 6:49 PM Paul Gilmartin < 000433f07816-dmarc-requ...@listserv.ua.edu> wrote: > On Sat, 23 Oct 2021 18:36:54 -0500, Joe Monk wrote: > > >LH

Re: Question about negative indexes

ssage- From: IBM Mainframe Discussion List On Behalf Of Bernd Oppolzer Sent: Saturday, October 23, 2021 3:58 PM To: IBM-MAIN@LISTSERV.UA.EDU Subject: Re: Question about negative indexes So this means that LA 2,ITEM+10 LH 3,=H'-5' LA 2,0(2,3) will put the address ITEM+5 in register

Re: Question about negative indexes

On Sat, 23 Oct 2021 18:36:54 -0500, Joe Monk wrote: >LH is an RX instruction. > >So, LH 3,=H'-5' would give an addressing exception, no? Because the second >operand is treated as coming from storage? So that would be a negative >address? > No. >If you said LH 3,0(=H'-5',2), that would give you IT

Re: Question about negative indexes

LH is an RX instruction. So, LH 3,=H'-5' would give an addressing exception, no? Because the second operand is treated as coming from storage? So that would be a negative address? If you said LH 3,0(=H'-5',2), that would give you ITEM+5? Joe On Sat, Oct 23, 2021 at 6:01 PM Bernd Oppolzer wro

Re: Question about negative indexes

On Sun, 24 Oct 2021 00:57:53 +0200, Bernd Oppolzer wrote: >So this means that > >LA   2,ITEM+10 >LH   3,=H'-5' >LA   2,0(2,3) > >will put the address ITEM+5 in register 2, at least in AMODE 24/31? > I believe so. BTW, the HLASM Ref. says the address operand of a USING must be non-negative, but I

Re: Question about negative indexes

So this means that LA   2,ITEM+10 LH   3,=H'-5' LA   2,0(2,3) will put the address ITEM+5 in register 2, at least in AMODE 24/31? With AMODE 64, this will be a problem, because the LH instruction only fills the right half of the 64 bit register 3, right? Is there a way to do this right in al

Re: Question about negative indexes

I'm pretty sure that given the context, the question is about AMODE 64 on z/Architecture. To the original question: the sign is never "ignored". But there is no sign on base or index addresses. They are treated as unsigned numbers with the length of addresses of the current AMODE. When added up

Re: Question about negative indexes

On Sat, Oct 23, 2021 at 7:41 PM Paul Gilmartin <000433f07816-dmarc-requ...@listserv.ua.edu> wrote: > > On Sat, 23 Oct 2021 11:33:33 -0500, Joe Monk wrote: > > > >I know this will probably be an easy answer for somebody... but I dont deal > >with AM64 much. > > > AMD64?

Re: Question about negative indexes

On Sat, 23 Oct 2021 11:33:33 -0500, Joe Monk wrote: > >I know this will probably be an easy answer for somebody... but I dont deal >with AM64 much. > AMD64? >If Im in AM64 and I load an index register with -1, does the machine ignore >the sign when using it

Re: Question about negative indexes

On Sat, 23 Oct 2021 11:33:33 -0500 Joe Monk wrote: :>Howdy, :>I know this will probably be an easy answer for somebody... but I dont deal :>with AM64 much. :>If Im in AM64 and I load an index register with -1, does the machine ignore :>the sign when using it in an RX instruction such as STC? :

Question about negative indexes

Howdy, I know this will probably be an easy answer for somebody... but I dont deal with AM64 much. If Im in AM64 and I load an index register with -1, does the machine ignore the sign when using it in an RX instruction such as STC? I know it ignores the sign in AM24/31... Thanks, Joe