OH, read this again.
I retract my comment - I didn't spot the reference to mutual authentication.
There would be an alternative for the server end to trust a client certificate
signed by the client's CA by trusting the client's root CA.
Mike Wawiorko
-Original Message-
From: IBM
One of the differences between PDSes and PDSEs is that PDSEs reclaim the space
of deleted members. In order for that to be done, however, the PDSE address
space needs to know that the member is no longer in use so it is safe for the
space to be reclaimed. If the space cannot be reclaimed at the
Charles sent this
"But for certificate-based client authentication, the server admin must send
the client admin a client certificate AND its private (???) key."
Surely that should say public key. Or am I missing something?
Mike Wawiorko I Mainframe Connectivity I Global Technology
You can do a BASR and STORAGE OBTAIN, STORAGE RELEASE and BR in less time
than a BAKR.
No you can't.
How does its performance stack up against SVC?
That's not a useful comparison. What is useful is "how does its
performance stack up against SVC plus the SVC interrupt handler".
Peter
Hello!
Global Copy bytes transferred (Out of Sync)... is this available in SMF
anywhere, by any chance?
- Vignesh
Mainframe Infrastructure
MARKSANDSPENCER.COM
Unless otherwise stated above:
Marks and Spencer plc
Registered Office:
Waterside House
35 North
>> PC has a larger address space, but IBM still has to reserve numbers for its
>> own use, and 3rd party vendors still must avoid collisions.
Avoid collisions?
PC number is formed by ETE sequence number suffixed to LX number returned by
LXRES.
As someone who has written quite a few software
> So, has anyone IPL'd z/OS 2.2 or higher with the data sets on the sysres
> catalogued to volume instead of volume ** ???
Not in my shop (z/OS 2.3). All my references to are all contained in
IEASYM00 and are used to substring its first four characters for the setting of
, etc.
Bob
I was unaware of the PERFORMPENDINGDELETE option. Nice.
Anecdotal: I'm a automation administrator, and have struggled with
NetView's DSILIST data set that is used to retain various automation table
listings/reports. IBM recommends allocating this data set as a PDSE to
avoid Sx37 ABENDs and/or the
Hi Matthew,
That is not the same as CATALOGing Datasets to VOL().
Regards,
David
On 2019-08-29 08:44, Matthew Stitt wrote:
> On my systems, I use the volume parameter of the LPALSTxx, PROGxx, etc.
> Volume is set to (or (on mod-54, so not needed now) ). Have no
> issues with IPL using this
Kees good point
On Thu, Aug 29, 2019 at 8:29 AM Vernooij, Kees (ITOP NM) - KLM <
kees.verno...@klm.com> wrote:
> "against SVC plus the SVC interrupt handler".
> Possibly also: Plus SVC code?
> The SVC instruction performs a function, the PC instruction does too.
>
> From what I understood of the
"against SVC plus the SVC interrupt handler".
Possibly also: Plus SVC code?
The SVC instruction performs a function, the PC instruction does too.
>From what I understood of the PC instruction: with 1 instruction you can now
>execute a 'function' that might have taken pages of assembler
> crypto non-repudiation can show it came from your machine
I certainly agree with this, but you can restrict what "your machine" is so
that it's a lot better than just "came from a particular PC" or "came from a
particular mainframe". For example, the private key may be stored in something
Hi Barbara,
z/OS 2.2, SYS1.PARMLIB cataloged using **, SYS1.PROCLIB not on the res
volume, everything else cataloged to It works fine. I'll keep your
warning about PARMLIB in the back of my mind and not try something dumb like
recataloging it to when we go to 2.4 next year. :-)
Rex
I got curious. Looks like ** and are interchangeable for
everything with one restriction noted below
RTFMing in Init & Tuning:
https://www.ibm.com/support/knowledgecenter/en/SSLTBW_2.2.0/com.ibm.zos.v2r2.ieae200/ieae20035.htm
I see the following restrictions for indirect cataloging:
On my systems, I use the volume parameter of the LPALSTxx, PROGxx, etc. Volume
is set to (or (on mod-54, so not needed now) ). Have no issues
with IPL using this method.
Matthew
On Thu, 29 Aug 2019 10:58:15 +, Richards, Robert B.
wrote:
>> So, has anyone IPL'd z/OS 2.2 or higher
Does this mean
That BALR is length code 1 and BAL is 2
And for BALR bit 32 is on BAL bit 33 is on
Thanks
---T--T-T-┐
│IL│ │Prog │ │
│C │CC│Mask │ Instruction Address │
L--+--+-+--
32 34 36 4 63
The instruction-length code is
Peter,
This begs a question for me how do you measure the performance..?
What I am seeing via the post and understanding performance matters even
with the faster Z processors.
Scott
On Thu, Aug 29, 2019 at 7:45 AM Peter Relson wrote:
>
> You can do a BASR and STORAGE OBTAIN, STORAGE RELEASE
David Crayford says...
> ...It would be fantastic to have bash as the default shell for z/OS but that
> ain't gonna happen anytime soon :)
FWIW: Here's how I tend to work on z/OS.
* I leave my default login shell (in the OMVS segment) as /bin/sh.
* I have my .profile/.bash_profile/.bashrc files
I mis-wrote.
My LPALSTxx and PROGxx do not utilized the variable. Only on the APF
statements is it used. Sorry for the confusion.
All the datasets except for the VSAM (ZFS) on my the volume I use for SMP/E
target and IPL are cataloged with for the volume name. Even
SYS1.NUCLEUS,
Any potential packaging error should be reported to the vendor.
Lizette
> -Original Message-
> From: IBM Mainframe Discussion List On Behalf Of
> Jake Anderson
> Sent: Wednesday, August 28, 2019 9:26 PM
> To: IBM-MAIN@LISTSERV.UA.EDU
> Subject: Re: GIM23901E clarification
>
> Hi
Hi list,
Just wanted to circle back for closure on this in case somebody else hits the
same snag. We're using something called CyberArk to monitor and log all
privileged access to Windows servers (and soon coming to Linux here). The SKLM
documentation says to perform the install as a local
I just checked my master cat and EVERY entry has , 2, or 3 except
SYS1.PARMLIB on the SYSRES It has **. and both are set
to since we use mod 27s. We are at z/OS 2.3.
On Thu, Aug 29, 2019 at 12:17 AM Barbara Nitz wrote:
> >I have never has a problem using anywhere ** could have
Yes, it looks like you unfortunately landed on a temporary server issue
- everything seems to work fine now. Please let me know if you run into
similar glitches that aren't resolved within a few hours and I'll alert
the appropriate team/s.
-Sue Shumway
On 8/27/2019 4:54 PM, Mike Hochee
On Thu, 29 Aug 2019 16:54:15 +, Seymour J Metz wrote:
>No, that means that for 24-bit mode, bits 32-33 are 01 after BALR and 10 after
>BAL, per p. 6-7; the ILC is not stored for 31-bit and 64-bit modes.
>
In AMODE 24, BALR sets bit 32 to 0; in AMODE 31 to 1. I have used
this to detect AMODE
I think I got 0 in the first byte after BAL Thanks got a reply for my C
compiler issue will forward
Joe Reichman
170-10 73 rd ave
Fresh meadows NY 11366
> On Aug 29, 2019, at 12:54 PM, Seymour J Metz wrote:
>
> No, that means that for 24-bit mode, bits 32-33 are 01 after BALR and 10
>
On Thu, 29 Aug 2019 04:22:02 +, Jon Perryman wrote:
>The PC instruction is a replacement for SVC. Both instructions exist
>solely to run authorized programs in other address spaces.
No. The SVC instruction, as implemented by OS/360 and its descendants,
exists to provide a service that
Hi Dana and Andy,
You can omit (ZPARM) OPMODE and let it default as a first attempt.
You can code MEMLIMIT=3G, provided that OPMODE is set to either
(NEWFUNC,800) or (NEWFUNC,900) (in a later attempt).
You should also code REGION=0M in the MSTR Proc.
Just before shutting down the Queue Manager,
SVC itself performs a simple function. SVC together with its interrupt
handlers is not so simple. What with the serialization for the GETMAIN or
whatever it uses these days, I'd expect it to be at least as expensive as PC.
If you need to operate in another address space, add in the overhead of
In this case the term "address space was generic", referring to the range of
permissible numbers. SV
--
Shmuel (Seymour J.) Metz
http://mason.gmu.edu/~smetz3
From: IBM Mainframe Discussion List on behalf of Jon
Perryman
Sent: Thursday, August 29,
Hi, Dana...
I did this exact upgrade last year when our shop upgraded z/OS v1.13 to v2.2.
As far as I remember, this upgrade only needed an MQ parm changed for the
correct / new version - can't recall what parm it was, but I'm sure you can
find it. Didn't have to change anything else, and
Begin forwarded message:
> From: "Basil Kanneth"
> Date: August 29, 2019 at 11:01:57 AM EDT
> To: "Joseph Reichman"
> Subject: RE: Case TS002648607 (PMR 76523,082,000) - Compiler abend
>
> Hi Joseph,
>
> It turns out the system protection exception occurred because of a missing
> semicolon
ETCRE et al are part of the setup prior to issuing the PC instruction; the
actual implementation of the PC is a black box and need not be the same between
models, as long as it complies with PoOps.
--
Shmuel (Seymour J.) Metz
http://mason.gmu.edu/~smetz3
> how do you measure the performance..?
For the PC instruction, performance is simply a curiosity and doesn't really
matter. The alternatives are SVC and SSI. The benefits of PC far outweigh any
possible savings by using SVC. The SSI is a special use case.
As for measuring performance, is
On Thu, 29 Aug 2019 06:34:34 -0500, Steve Horein wrote:
>
>Much better.
>While I can't help with the question of "what really happens...", it does
>seem that -something- must happen to the PDSE to allow successful deletion
>of those members. In the case of this particular NetView data set, "REACC"
> In AMODE 24, BALR sets bit 32 to 0;
Yes, and BAL sets it to 1, for the same reason. As I stated, "for 24-bit mode,
bits 32-33 are 01 after BALR and 10 after BAL"
> in AMODE 31 to 1. I have used this to detect AMODE in code that had to run in
> both XA and 370 without causing a program
Amazing!
Charles
-Original Message-
From: IBM Mainframe Discussion List [mailto:IBM-MAIN@LISTSERV.UA.EDU] On Behalf
Of Joseph Reichman
Sent: Thursday, August 29, 2019 10:27 AM
To: IBM-MAIN@LISTSERV.UA.EDU
Subject: Fwd: Case TS002648607 (PMR 76523,082,000) - Compiler abend
Begin
No, that means that for 24-bit mode, bits 32-33 are 01 after BALR and 10 after
BAL, per p. 6-7; the ILC is not stored for 31-bit and 64-bit modes.
--
Shmuel (Seymour J.) Metz
http://mason.gmu.edu/~smetz3
From: IBM Mainframe Discussion List on behalf
> This begs a question for me how do you measure the performance..?
ObPedant ITYM raises.
There are several ways you can measure performance, but the key questions, as
always, are "What do you mean by performance?" and "Performance of what?" Tell
me the answer you want and I'll write the
> The PC instruction is a replacement for SVC.
That's one use case. What about privileged code that scheduled an SRB into
another address space and waited for a cross-memory post? A PC is potentially
much less overhead.
> Both instructions exist solely to run authorized programs in other
Found another instance of the same thing many years ago. I forget if it was
COBOL-E or COBOL-F.
A missing period caused the compiler to abend.
Ah! The good old days.
-Original Message-
From: IBM Mainframe Discussion List On Behalf Of
Charles Mills
Sent: Thursday, August 29, 2019 12:37
I saw one on a BUNCH machine compiler, except that it didn't fail, it just gave
the wrong result. It was a fairly straightforward COMPUTE statement, something
along the lines of COMPUTE D=C-(A*B). The result came back as D=C+(A*B).
Didn't take the company long to produce a fix for that one!
>> The PC instruction is a replacement for SVC.
> That's one use case. What about privileged code that scheduled an SRB into
> another address space and waited for a cross-memory post? A PC is potentially
> much less overhead.
PC routines are not necessary to use XMEM but they make it so
My point with ETCRE was that it is the start of the black box. You can't just
depend upon this being a hardware only instruction nor can you rely upon your
PC routine to be started directly from the instruction. IBM could easily pass
your routine's address in another parm. Only someone who's
I have a confusing issue with using COBOL E15/E35 exit programs where the exit
programs dynamically call application-specific subroutines in a JCL SYNCSORT.
The issue is from which library the exit programs are actually loading the
dynamically called subroutines. It seems that the dynamic
It was in the early 80s. And, it might have been the Capex Optimizer we used
then. Problem went away when he changed the installation option.
> -Original Message-
> From: IBM Mainframe Discussion List On
> Behalf Of Mark Jacobs
> Sent: Thursday, August 29, 2019 1:56 PM
> To:
Of course PC is the replacement for SVC. You have to look at SVC when PC came
out and how it was being used. It doesn't matter what it was on OS/360. PC came
out when address spaces and running authorized was available. Nearly every
feature of PC was implemented to address use cases of SVC
I've had the COBOL compiler abend during the SQL preprocessor step with a
malformed EXEC SQL statement.
From: IBM Mainframe Discussion List on behalf of
Allan Staller
Sent: Thursday, August 29, 2019 11:46 AM
To: IBM-MAIN@LISTSERV.UA.EDU
Subject: Re: Case
One reason to love Swift. No semicolons required!!!
From: IBM Mainframe Discussion List on behalf of
Matt Hogstrom
Sent: Thursday, August 29, 2019 12:28 PM
To: IBM-MAIN@LISTSERV.UA.EDU
Subject: Re: Case TS002648607 (PMR 76523,082,000) - Compiler abend
I
Very early. Fairly new at the job COBOL programming. Compiler was updated
and started dying. I went a couple weeks round and round with the guy who did
the install, trying to get him to open the issue with IBM. We were kind of
formal in those days and he didn't believe the young newcomer.
Surprising that the configuration of a COBOL compiler would care about a TMS,
but OK.
Mark Jacobs
Sent from ProtonMail, Swiss-based encrypted email.
GPG Public Key -
https://api.protonmail.ch/pks/lookup?op=get=markjac...@protonmail.com
‐‐‐ Original Message ‐‐‐
On Thursday, August
On Thu, 29 Aug 2019 17:13:35 +, Seymour J Metz wrote:
>> In AMODE 24, BALR sets bit 32 to 0;
Yes, and BAL sets it to 1, for the same reason. As I stated, "for 24-bit mode,
bits 32-33 are 01 after BALR and 10 after BAL"
> in AMODE 31 to 1. I have used this to detect AMODE in code that had
I expected this to be a missing paren causing the S0C4 but a semicolon is
surprising. Usually you get a confusing message for a missing semicolon.
Notice that IBM says they will get back to you by Sept 5. You caused this guy
extra work by declaring this a sev 1. I don't know about today but in
> There are an infinite number of things that won't work. Why should I try any
> of them?
Because you brought up AMODE as if it were relevant to the ILC, and I was
pointing out that it was irrelevant.
--
Shmuel (Seymour J.) Metz
http://mason.gmu.edu/~smetz3
So many times I worked on a script or compiled/assembled code, got an
error that made no sense, and then complained to anyone who would
listen, "The system is obviously broken". And I'm sure you can guess
*exactly* how many of those times the system really turned out to be
broken :)
On
I always knew semi-colons were dangerous. Most people butcher their usage in
grammar and now abends … who knows what mischief they will stir up next.
Matt Hogstrom
m...@hogstrom.org
+1-919-656-0564
PGP Key: 0x90ECB270
Facebook LinkedIn
I saw one as lab assistant. The bright young thing came tromping in 'the
eight's broken, I need it fixed'. Turns out she was right! The adder's carry
bit wasn't propagating. 3+3=6, 3+4=7, 4+4=7? Whoa nelly call the CE.
In a message dated 8/29/2019 3:16:16 PM Central Standard Time,
I am considering what upgrade path (if any) I might take from my current z/OS
2.1 RSU 1903 system. I thought that I wouldn't go to 2.3 because I was using
SMTP and not CSSMTP. The configuring and implementation of CSSMTP has proven
remarkably uneventful. I am not aware of any other gotchas
> But for certificate-based client authentication, the server admin must send
> the client admin a client certificate AND its private key.
Yes, he sends the client a key intended to be used only by that client. That's
very different from a vendor sending his own private key to customers.
--
Going to as soon as I m done with work
On Aug 29, 2019, at 1:13 PM, Seymour J Metz wrote:
>> In AMODE 24, BALR sets bit 32 to 0;
>
> Yes, and BAL sets it to 1, for the same reason. As I stated, "for 24-bit
> mode, bits 32-33 are 01 after BALR and 10 after BAL"
>
>> in AMODE 31 to 1.
That would correspond to 2 bytes and 4 bytes. Hence the word "code".
(These lengths check out for BALR and BAL on the green card facsimiles
hanging in a frame on the wall of my home office - that John Ehrman gave
me.)
Cheers, Martin
Martin Packer
zChampion, Systems Investigator & Performance
On 29/08/2019 9:18 am, Charles Mills wrote:
But for certificate-based client authentication, the server admin must send the
client admin a client certificate AND its private key. Why? Philosophically,
because a client certificate signed by a trusted CA does not prove the
authenticity of the
My assumption is that SMF performs some house-keeping functions before passing
control over to IEFU83/IEFU84 exits. The minimum house-keeping functions that I
could think of are a. Establish an ESTAE recovery routine (may be FRR for
IEFU84??) b. GETMAIN to obtain SAVEAREA for the exits
apoorva.kanm...@gmail.com (SUBSCRIBE IBM-MAIN Anonymous) writes:
> I have a question on PC instruction for which I have been looking for
> an answer for quite sometime now. According to "Priciples of
> operations" manual, execution of an SVC instruction causes a new PSW
> to be loaded from x'1C0'
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