Re: Assembler :- PC Instruction
On Thu, 5 Sep 2019 04:54:02 +, Jon Perryman wrote: >>SVC allows you to execute authorized code in YOUR address space. I should have said "SVC invokes a system service that runs in Supervisor state in your address space." >>It does not allow you to execute code in any arbitrary address space. > >There is no YOUR address space. Really? Your address space is the address space in which your program is running. >E.g. Getmain belongs to RSM but run authorized in any address >space that uses the getmain macro. ITYM VSM. And GETMAIN does not "run authorized", but it invokes a system service that runs in Supervisor state. It isn't the same thing. -- Tom Marchant -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN
Re: Assembler :- PC Instruction
> SVC allows you to execute authorized code in YOUR address space. > It does not allow you to execute code in any arbitrary address space. There is no YOUR address space. E.g. Getmain belongs to RSM but run authorized in any address space that uses the getmain macro. >From a product perspective, the active address space is seldom related to the >SVC or PC. They usually occur in macro's where our services are needed. Jon. -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN
Re: Assembler :- PC Instruction
On Sat, 31 Aug 2019 01:16:55 +, Jon Perryman wrote: >>What you describe as being able to run code in any >>address space sounds more like scheduling an SRB. > >SRB is one method to execute authorized code in any address space >but surely you must be familiar with others such as SVC, PC and >IEFSSREQ. Or are you suggesting that getmain and storage macro's >somehow use an SRB to execute authorized code in any address >space? SVC allows you to execute authorized code in YOUR address space. It does not allow you to execute code in any arbitrary address space. If you mean that an SVC can be issued in any address space, I hope you can see why I didn't understand what you meant. Likewise, PC can be used to execute authorized code in either your address space or a specific other address space, depending on how the PC routine was established. It does not allow you to execute code (authorized or not) in any arbitrary address space. I'm not familiar enough with IEFSSREQ to comment about it. -- Tom Marchant -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN
Re: Assembler :- PC Instruction
> What you describe as being able to run code in any > address space sounds more like scheduling an SRB. SRB is one method to execute authorized code in any address space but surely you must be familiar with others such as SVC, PC and IEFSSREQ. Or are you suggesting that getmain and storage macro's somehow use an SRB to execute authorized code in any address space? Jon. On Friday, August 30, 2019, 08:08:32 AM PDT, Tom Marchant <000a2a8c2020-dmarc-requ...@listserv.ua.edu> wrote: On Thu, 29 Aug 2019 20:59:02 +, Jon Perryman wrote: >As for "executing authorized code in other address spaces", I actually meant >any address space. What do you mean by that? A PC instruction can pass control to code in a specific address space, as defined when the PC routine was established. What you describe as being able to run code in any address space sounds more like scheduling an SRB. -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN
Re: Assembler :- PC Instruction
Their meaning was vague in the 1950s. Try using MIPS to compare the performance of a 704 and 704 without knowing the workload. -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 From: IBM Mainframe Discussion List on behalf of Vernooij, Kees (ITOP NM) - KLM Sent: Friday, August 30, 2019 3:07 AM To: IBM-MAIN@LISTSERV.UA.EDU Subject: Re: Assembler :- PC Instruction A little less I think. I remember their meaning became vague when comparing performance and MIPS of Amdahl and IBM machines gave unexplainable differences during the 80's. And when IBM started putting more functionality into an instruction, if was definitely renamed to Meaningless Indicator of Processor Speed. Kees. > -Original Message- > From: IBM Mainframe Discussion List [mailto:IBM-MAIN@LISTSERV.UA.EDU] On > Behalf Of Seymour J Metz > Sent: 29 August, 2019 19:04 > To: IBM-MAIN@LISTSERV.UA.EDU > Subject: Re: Assembler :- PC Instruction > > SVC itself performs a simple function. SVC together with its interrupt > handlers is not so simple. What with the serialization for the GETMAIN or > whatever it uses these days, I'd expect it to be at least as expensive as > PC. If you need to operate in another address space, add in the overhead > of acquiring, scheduling and freeing SRBs. > > > The times that machine performance could be expressed in Million > Instructions Per Second are long gone. > > > They've been gone for half a century, if they ever existed. > > > -- > Shmuel (Seymour J.) Metz > http://mason.gmu.edu/~smetz3 > > > > From: IBM Mainframe Discussion List on behalf > of Vernooij, Kees (ITOP NM) - KLM > Sent: Thursday, August 29, 2019 8:27 AM > To: IBM-MAIN@LISTSERV.UA.EDU > Subject: Re: Assembler :- PC Instruction > > "against SVC plus the SVC interrupt handler". > Possibly also: Plus SVC code? > The SVC instruction performs a function, the PC instruction does too. > > From what I understood of the PC instruction: with 1 instruction you can > now execute a 'function' that might have taken pages of assembler > instructions before. > > The times that machine performance could be expressed in Million > Instructions Per Second are long gone. > > Kees. > > > -Original Message- > > From: IBM Mainframe Discussion List [mailto:IBM-MAIN@LISTSERV.UA.EDU] On > > Behalf Of Peter Relson > > Sent: 29 August, 2019 13:45 > > To: IBM-MAIN@LISTSERV.UA.EDU > > Subject: Re: Assembler :- PC Instruction > > > > > > You can do a BASR and STORAGE OBTAIN, STORAGE RELEASE and BR in less > time > > than a BAKR. > > > > > > No you can't. > > > > > > How does its performance stack up against SVC? > > > > > > That's not a useful comparison. What is useful is "how does its > > performance stack up against SVC plus the SVC interrupt handler". > > > > Peter Relson > > z/OS Core Technology Design > > > > > > -- > > For IBM-MAIN subscribe / signoff / archive access instructions, > > send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN > > For information, services and offers, please visit our web site: > http://secure-web.cisco.com/1SDiyZznrzneuHMlVlorXfTN4MTOpKavy-U7CQXEF7Om1cw7VKvBjMioACkhSTdJ1UnT0iDSIquIbZapsrpfepa_vxpOjTUhLmTFVYyX8-WUvuITkLgcyQSfx70Z0S1L32cpQemqODSaxoEapfhZJJFgHMr4DIg0lLch-REK7PAtQBFbQeMqmiNaONF0Q9oouQ66ESvhUuR7h4qumKtr8gqNkU55CHeadMTwQaTFxq8o2o4E1w1Sity7ZnmLgUss1CZ4CSDC5BA6oVAezdvnolPJdO3B2Q8IuilFkIrrrOeygikyBnH2nbnpkNCyzAIX0HK379LjyMP_MlC4IW_p_xt80CSihKm2wQeeqdQ9FySf76x4sM9Yo17aeOy3Cm-hd9UR_GRjyAv49alg08lumuRTxlZxx76WGjT12MdnIrVQ/http%3A%2F%2Fsecure- > web.cisco.com/1yFCMng_oi34MeuWoGQVFSplOg6fpaFLyxdbGdQb9STPypzNLAxj2z3H1yPe > 4hmcGsoQrveXhGIGpIQn4y5avwq7BULLqLr7LDIdVd3uZfyPSdpqKPZLOf85a9_UOdAfEEkGjP > nXcTp7oZjO72UlCrOrkWCx9XGTouvxIvkrdhdxx7mbiJCUcsSNwdIhGoKmSm_S4VqyCCu_- > 5BvvEZ79ciMla-Ce6L9JM5Ftywxolu5eN46Eq6qEk2Cf- > Zcs5T9IkVQzK7gnyAmr3_tZBL1XW1EDny_9mYCBo58WeWGmKDzZaHMjFOWAKa7le7wuJMXxvxG > huhm_EyVpP7hsmqb89fuquitBk3uYlWjLHQFCW51CPwAUMtM3_g4RZTozHtzb/http%3A%2F%2 > Fhttp://secure-web.cisco.com/1AQKdY4EiF6WcU0D3keYzjZkkvl1a6EzqmnBNLIn4X5Fpyr6naYn2j3cK2vDIyJsRpJ8dy0XFV07AUcRzyOm9vfesfF5N18Nyxc6Fb2ihZ4V9dzLkGZvO_e8LJX2zmAzPdyMciW-NYkwSFEMrbhRuigmI1OLsiM3Lk9SK_MFWdRRUw8QzWdl7Da15Uos1aiQ5iAZecQ2V5eykSp_OvNAOOWoJMiNhW1U__9eVmVGlmRtNGiJi2mmiovMjYSppmRFCqA9sPEmpSPY-E5q8hSnkHWF2W6QNid1IxGFsWnhvsf1f2dzjLYL3zqOWMDpI51nN_BxkZ9BiGcw7jOmaVk9zwwhbrQb2_0BqZWIl2nX7kcb482OaSCWurfQYBbKrp0IyXE6RdP1MNHo1k8VCms7kH9LNPSd32LhpxKPIvDc-XbX9ptaIm63
Re: Assembler :- PC Instruction
I interpreted "might have taken pages of assembler instructions" as referring to GETMAIN, FREEMAIN and linkage needed in conjunction with the BALR. With PC/PR the registers are saved and restored with no additional user code. -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 From: IBM Mainframe Discussion List on behalf of Peter Relson Sent: Friday, August 30, 2019 8:24 AM To: IBM-MAIN@LISTSERV.UA.EDU Subject: Re: Assembler :- PC Instruction >From what I understood of the PC instruction: with 1 instruction you can now execute a 'function' that might have taken pages of assembler instructions before. I'm not sure where this thought comes from. The PC instruction is not magic. It does not execute a "function" beyond the function of the instruction itself. It passes control somewhere, may change state, may create an entry on the linkage stack. Peter Relson z/OS Core Technology Design -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN
Re: Assembler :- PC Instruction
"A PC can execute what might have taken many instructions before" is true in the same sense that it is true for BAL: one instruction that you code goes off and does a bunch of stuff elsewhere, saving you having to code all those instructions. It is also true in the sense that a PC can do in one instruction what would have taken a whole series of instructions before: switching AMODE, switching problem state, and branching. Charles -Original Message- From: IBM Mainframe Discussion List [mailto:IBM-MAIN@LISTSERV.UA.EDU] On Behalf Of Peter Relson Sent: Friday, August 30, 2019 5:25 AM To: IBM-MAIN@LISTSERV.UA.EDU Subject: Re: Assembler :- PC Instruction >From what I understood of the PC instruction: with 1 instruction you can now execute a 'function' that might have taken pages of assembler instructions before. I'm not sure where this thought comes from. The PC instruction is not magic. It does not execute a "function" beyond the function of the instruction itself. It passes control somewhere, may change state, may create an entry on the linkage stack. -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN
Re: Assembler :- PC Instruction
On Thu, 29 Aug 2019 20:59:02 +, Jon Perryman wrote: >As for "executing authorized code in other address spaces", I actually meant >any address space. What do you mean by that? A PC instruction can pass control to code in a specific address space, as defined when the PC routine was established. What you describe as being able to run code in any address space sounds more like scheduling an SRB. -- Tom Marchant -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN
Re: Assembler :- PC Instruction
Maybe he's talking about the more limited Primary and Secondary address spaces. Cheers, Martin Martin Packer zChampion, Systems Investigator & Performance Troubleshooter, IBM +44-7802-245-584 email: martin_pac...@uk.ibm.com Twitter / Facebook IDs: MartinPacker Blog: https://www.ibm.com/developerworks/mydeveloperworks/blogs/MartinPacker Podcast Series (With Marna Walle): https://developer.ibm.com/tv/mpt/or https://itunes.apple.com/gb/podcast/mainframe-performance-topics/id1127943573?mt=2 Youtube channel: https://www.youtube.com/channel/UCu_65HaYgksbF6Q8SQ4oOvA From: Tom Marchant <000a2a8c2020-dmarc-requ...@listserv.ua.edu> To: IBM-MAIN@LISTSERV.UA.EDU Date: 30/08/2019 16:00 Subject: Re: Assembler :- PC Instruction Sent by:IBM Mainframe Discussion List On Thu, 29 Aug 2019 19:56:57 -1000, Anne & Lynn Wheeler wrote: >in the wake of the FS faulure (FS was going to be completely different >than 370, and 370 efforts were being shutdown during FS period, also >lack of 370 offerings during FS period is credited with giving clone >mainframe vendors market foothold), there was mad rush to get stuff back >into 370 product pipeline ... 303x and 3081 Q efforts were kicked off >in parallel. 3081 included 370/xa, 31bit addressing and "access >registers" (subsystems had their own virtual address space, but could >use "access registers" to access "parameter" storage in application >address space). All this was known informally as "811" for the Nov1978 >publication date of the architecture specification documents. I don't know about IBM internal plans or discussions, but Access Registers and AR mode were not publicly announced as part of 370/XA. They were first documented in the Enterprise System Architecture/370 Principles of Operation, SA22-7200-0, which can be found at https://urldefense.proofpoint.com/v2/url?u=http-3A__bitsavers.trailing-2Dedge.com_pdf_ibm_370_princOps_SA22-2D7200-2D0-5F370-2DESA-5FPrinciples-5Fof-5FOperation-5FAug88.pdf=DwIFaQ=jf_iaSHvJObTbx-siA1ZOg=BsPGKdq7-Vl8MW2-WOWZjlZ0NwmcFSpQCLphNznBSDQ=GjItMeo-vHych-AkF0VZDvBsdcmOPmD-rPThhcKZDsg=EnehEvQA2zc3fw8_iaVQ7p0AUMyW3J4EULsynDXB2cc= Appendix D of that manual describes differences between 370-XA and ESA/370. On page D-1 it has this: New Facilities in ESA/370 The following facilities are new in ESA/370 and are not provided in 370-XA. Access registers, home address space, linkage stack, and load and store using real address are provided by all ESA/370 models. Move with source or destination key and private space are provided by some ESA/370 models. > >In part because of the increasing threat of CSA increasing to 8mbytes >for larger 3033 customers, a subset of "access registers" was >retrofitted to 3033 as "dual-address space" mode ... subsystems could >have their own address space, but also a 2nd address space to access >calling application parameters directly ... w/o needing CSA space. > >In 370 (3033) dual-address space mode ... there still wasn't program >call, but a supervisor call which in software would move the application >space address space to secondary and then load the subsystem address >space and enter the called subsystem. In 370/xa and "access register" >program call had a system defined table with all the necessary >information to do that function directly as part of the program call >instruction (whether implemented in hardware, microcode, picocode and/or >some combination) To clarify a bit, there was no Linkage Stack until ESA/370, and hence no stacking PC. -- Tom Marchant -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN Unless stated otherwise above: IBM United Kingdom Limited - Registered in England and Wales with number 741598. Registered office: PO Box 41, North Harbour, Portsmouth, Hampshire PO6 3AU -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN
Re: Assembler :- PC Instruction
On Thu, 29 Aug 2019 19:56:57 -1000, Anne & Lynn Wheeler wrote: >in the wake of the FS faulure (FS was going to be completely different >than 370, and 370 efforts were being shutdown during FS period, also >lack of 370 offerings during FS period is credited with giving clone >mainframe vendors market foothold), there was mad rush to get stuff back >into 370 product pipeline ... 303x and 3081 Q efforts were kicked off >in parallel. 3081 included 370/xa, 31bit addressing and "access >registers" (subsystems had their own virtual address space, but could >use "access registers" to access "parameter" storage in application >address space). All this was known informally as "811" for the Nov1978 >publication date of the architecture specification documents. I don't know about IBM internal plans or discussions, but Access Registers and AR mode were not publicly announced as part of 370/XA. They were first documented in the Enterprise System Architecture/370 Principles of Operation, SA22-7200-0, which can be found at http://bitsavers.trailing-edge.com/pdf/ibm/370/princOps/SA22-7200-0_370-ESA_Principles_of_Operation_Aug88.pdf Appendix D of that manual describes differences between 370-XA and ESA/370. On page D-1 it has this: New Facilities in ESA/370 The following facilities are new in ESA/370 and are not provided in 370-XA. Access registers, home address space, linkage stack, and load and store using real address are provided by all ESA/370 models. Move with source or destination key and private space are provided by some ESA/370 models. > >In part because of the increasing threat of CSA increasing to 8mbytes >for larger 3033 customers, a subset of "access registers" was >retrofitted to 3033 as "dual-address space" mode ... subsystems could >have their own address space, but also a 2nd address space to access >calling application parameters directly ... w/o needing CSA space. > >In 370 (3033) dual-address space mode ... there still wasn't program >call, but a supervisor call which in software would move the application >space address space to secondary and then load the subsystem address >space and enter the called subsystem. In 370/xa and "access register" >program call had a system defined table with all the necessary >information to do that function directly as part of the program call >instruction (whether implemented in hardware, microcode, picocode and/or >some combination) To clarify a bit, there was no Linkage Stack until ESA/370, and hence no stacking PC. -- Tom Marchant -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN
Re: Assembler :- PC Instruction
Peter, Ok, than I misunderstood what was or could be put into the PC microcode. Kees. > -Original Message- > From: IBM Mainframe Discussion List [mailto:IBM-MAIN@LISTSERV.UA.EDU] On > Behalf Of Peter Relson > Sent: 30 August, 2019 14:25 > To: IBM-MAIN@LISTSERV.UA.EDU > Subject: Re: Assembler :- PC Instruction > > > From what I understood of the PC instruction: with 1 instruction you can > now execute a 'function' that might have taken pages of assembler > instructions before. > > > I'm not sure where this thought comes from. The PC instruction is not > magic. It does not execute a "function" beyond the function of the > instruction itself. > It passes control somewhere, may change state, may create an entry on the > linkage stack. > > Peter Relson > z/OS Core Technology Design > > > -- > For IBM-MAIN subscribe / signoff / archive access instructions, > send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN For information, services and offers, please visit our web site: http://www.klm.com. This e-mail and any attachment may contain confidential and privileged material intended for the addressee only. If you are not the addressee, you are notified that no part of the e-mail or any attachment may be disclosed, copied or distributed, and that any other action related to this e-mail or attachment is strictly prohibited, and may be unlawful. If you have received this e-mail by error, please notify the sender immediately by return e-mail, and delete this message. Koninklijke Luchtvaart Maatschappij NV (KLM), its subsidiaries and/or its employees shall not be liable for the incorrect or incomplete transmission of this e-mail or any attachments, nor responsible for any delay in receipt. Koninklijke Luchtvaart Maatschappij N.V. (also known as KLM Royal Dutch Airlines) is registered in Amstelveen, The Netherlands, with registered number 33014286 -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN
Re: Assembler :- PC Instruction
>From what I understood of the PC instruction: with 1 instruction you can now execute a 'function' that might have taken pages of assembler instructions before. I'm not sure where this thought comes from. The PC instruction is not magic. It does not execute a "function" beyond the function of the instruction itself. It passes control somewhere, may change state, may create an entry on the linkage stack. Peter Relson z/OS Core Technology Design -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN
Re: Assembler :- PC Instruction
A little less I think. I remember their meaning became vague when comparing performance and MIPS of Amdahl and IBM machines gave unexplainable differences during the 80's. And when IBM started putting more functionality into an instruction, if was definitely renamed to Meaningless Indicator of Processor Speed. Kees. > -Original Message- > From: IBM Mainframe Discussion List [mailto:IBM-MAIN@LISTSERV.UA.EDU] On > Behalf Of Seymour J Metz > Sent: 29 August, 2019 19:04 > To: IBM-MAIN@LISTSERV.UA.EDU > Subject: Re: Assembler :- PC Instruction > > SVC itself performs a simple function. SVC together with its interrupt > handlers is not so simple. What with the serialization for the GETMAIN or > whatever it uses these days, I'd expect it to be at least as expensive as > PC. If you need to operate in another address space, add in the overhead > of acquiring, scheduling and freeing SRBs. > > > The times that machine performance could be expressed in Million > Instructions Per Second are long gone. > > > They've been gone for half a century, if they ever existed. > > > -- > Shmuel (Seymour J.) Metz > http://mason.gmu.edu/~smetz3 > > > > From: IBM Mainframe Discussion List on behalf > of Vernooij, Kees (ITOP NM) - KLM > Sent: Thursday, August 29, 2019 8:27 AM > To: IBM-MAIN@LISTSERV.UA.EDU > Subject: Re: Assembler :- PC Instruction > > "against SVC plus the SVC interrupt handler". > Possibly also: Plus SVC code? > The SVC instruction performs a function, the PC instruction does too. > > From what I understood of the PC instruction: with 1 instruction you can > now execute a 'function' that might have taken pages of assembler > instructions before. > > The times that machine performance could be expressed in Million > Instructions Per Second are long gone. > > Kees. > > > -Original Message- > > From: IBM Mainframe Discussion List [mailto:IBM-MAIN@LISTSERV.UA.EDU] On > > Behalf Of Peter Relson > > Sent: 29 August, 2019 13:45 > > To: IBM-MAIN@LISTSERV.UA.EDU > > Subject: Re: Assembler :- PC Instruction > > > > > > You can do a BASR and STORAGE OBTAIN, STORAGE RELEASE and BR in less > time > > than a BAKR. > > > > > > No you can't. > > > > > > How does its performance stack up against SVC? > > > > > > That's not a useful comparison. What is useful is "how does its > > performance stack up against SVC plus the SVC interrupt handler". > > > > Peter Relson > > z/OS Core Technology Design > > > > > > -- > > For IBM-MAIN subscribe / signoff / archive access instructions, > > send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN > > For information, services and offers, please visit our web site: > http://secure- > web.cisco.com/1yFCMng_oi34MeuWoGQVFSplOg6fpaFLyxdbGdQb9STPypzNLAxj2z3H1yPe > 4hmcGsoQrveXhGIGpIQn4y5avwq7BULLqLr7LDIdVd3uZfyPSdpqKPZLOf85a9_UOdAfEEkGjP > nXcTp7oZjO72UlCrOrkWCx9XGTouvxIvkrdhdxx7mbiJCUcsSNwdIhGoKmSm_S4VqyCCu_- > 5BvvEZ79ciMla-Ce6L9JM5Ftywxolu5eN46Eq6qEk2Cf- > Zcs5T9IkVQzK7gnyAmr3_tZBL1XW1EDny_9mYCBo58WeWGmKDzZaHMjFOWAKa7le7wuJMXxvxG > huhm_EyVpP7hsmqb89fuquitBk3uYlWjLHQFCW51CPwAUMtM3_g4RZTozHtzb/http%3A%2F%2 > Fwww.klm.com. This e-mail and any attachment may contain confidential and > privileged material intended for the addressee only. If you are not the > addressee, you are notified that no part of the e-mail or any attachment > may be disclosed, copied or distributed, and that any other action related > to this e-mail or attachment is strictly prohibited, and may be unlawful. > If you have received this e-mail by error, please notify the sender > immediately by return e-mail, and delete this message. > > Koninklijke Luchtvaart Maatschappij NV (KLM), its subsidiaries and/or its > employees shall not be liable for the incorrect or incomplete transmission > of this e-mail or any attachments, nor responsible for any delay in > receipt. > Koninklijke Luchtvaart Maatschappij N.V. (also known as KLM Royal Dutch > Airlines) is registered in Amstelveen, The Netherlands, with registered > number 33014286 > > > -- > For IBM-MAIN subscribe / signoff / archive access instructions, > send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN > > h the > -- >
Re: Assembler :- PC Instruction
apoorva.kanm...@gmail.com (SUBSCRIBE IBM-MAIN Anonymous) writes: > I have a question on PC instruction for which I have been looking for > an answer for quite sometime now. According to "Priciples of > operations" manual, execution of an SVC instruction causes a new PSW > to be loaded from x'1C0' (SVC FLIH), and program interruption causes a > new PSW loaded from x'1D0' (Program Interruption FLIH). Now my > question is what happens when a "PC" instruction is executed. Does a > new PSW gets loaded from a pre-determined location (like SVC/program > interrruption) or it's all handled through some micro code? The problem started with move from OS/VS2 SVS (and single address space) to OS/VS2 MVS and multiple address spaces (each application) ... however OS/360 heritage was heavily pointer passing APIs ... as a result an 8mbyte image of the MVS kernel had to appear in every application 16mbyte virtual address space ... so that kernel could access storage pointed to be the past pointers. the issue was then all the subsystems were put in each of their own address spaces and when application passed pointer to subsystem ... the subsystem was running in different address space than the address space that the parameter pointed to (by the passed pointer). The solution was the common segment area, a one megabyte area in every application 16mbyte address space ... where applications could obtain parameter space so the pointer to the parameter list passed to subsystem was identical address in both the application and the subsystem. However, the requirement for common segment area space was somewhat proportional to number of concurrent applications and number of subsystems ... which quickl exceeded one (mbyte) segement ... and the common segment area (CSA) morphed into the common system area (CSA). As systems continued to grow, the CSA requirement got larger and larger, 4mbytes (kernel+csa is 12mbytes, leaving only 4mbytes for applications, then 6mbytes in 3033 time-frame (kernel+csa 14mbytes, leaving only 2mbytes for applications) and threatening to become 8mbytes ... leaving zero bytes for applications. in the wake of the FS faulure (FS was going to be completely different than 370, and 370 efforts were being shutdown during FS period, also lack of 370 offerings during FS period is credited with giving clone mainframe vendors market foothold), there was mad rush to get stuff back into 370 product pipeline ... 303x and 3081 Q efforts were kicked off in parallel. 3081 included 370/xa, 31bit addressing and "access registers" (subsystems had their own virtual address space, but could use "access registers" to access "parameter" storage in application address space). All this was known informally as "811" for the Nov1978 publication date of the architecture specification documents. In part because of the increasing threat of CSA increasing to 8mbytes for larger 3033 customers, a subset of "access registers" was retrofitted to 3033 as "dual-address space" mode ... subsystems could have their own address space, but also a 2nd address space to access calling application parameters directly ... w/o needing CSA space. In 370 (3033) dual-address space mode ... there still wasn't program call, but a supervisor call which in software would move the application space address space to secondary and then load the subsystem address space and enter the called subsystem. In 370/xa and "access register" program call had a system defined table with all the necessary information to do that function directly as part of the program call instruction (whether implemented in hardware, microcode, picocode and/or some combination) Z/archiecture principles of opration references system defined ETEs (entry-table entrys) for program call instruction which includes a number options, including switching address spaces or not switching address spaces, changing instruction address, etc. "Interrupts" save the current PSW and load a new (static) PSW. Each Program Call ETE has controls for PSW fields that are saved and how much of new fields (unique to each ETE) are loaded ... as well as any address space games that might be played ... and various other rules (description goes on for more than dozen pages). -- virtualization experience starting Jan1968, online at home since Mar1970 -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN
Re: Assembler :- PC Instruction
My point with ETCRE was that it is the start of the black box. You can't just depend upon this being a hardware only instruction nor can you rely upon your PC routine to be started directly from the instruction. IBM could easily pass your routine's address in another parm. Only someone who's looked at ETDEF could say for sure. Jon. On Thursday, August 29, 2019, 10:40:41 AM PDT, Seymour J Metz wrote: ETCRE et al are part of the setup prior to issuing the PC instruction; the actual implementation of the PC is a black box and need not be the same between models, as long as it complies with PoOps. From: IBM Mainframe Discussion List on behalf of Jon Perryman For "who will perform the translation process", it's not going to be clear. First, rather than translation, the PC instruction builds the environment from the token. ETDEF defines the PC environment but ETCRE or ETCON could easily insert calls into the environment entry without us being aware. P/OPS only tells us the hardware side and we don't have access to the internals (e.g. establishing ARR). So the answer is we can't say for sure. -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN
Re: Assembler :- PC Instruction
>> The PC instruction is a replacement for SVC. > That's one use case. What about privileged code that scheduled an SRB into > another address space and waited for a cross-memory post? A PC is potentially > much less overhead. PC routines are not necessary to use XMEM but they make it so easy, why bother setting up XMEM unless you absolutely need to run as fast as possible. >> Both instructions exist solely to run authorized programs in other address >> spaces. > How did you run programs in another OS/360 address space. I don't see any > time machines here. ;-) My bad for saying "other address space" when I meant "any address space". At least I didn't say existed. Jon. -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN
Re: Assembler :- PC Instruction
Of course PC is the replacement for SVC. You have to look at SVC when PC came out and how it was being used. It doesn't matter what it was on OS/360. PC came out when address spaces and running authorized was available. Nearly every feature of PC was implemented to address use cases of SVC (e.g. xmem, limitations and restrictions). Even non-authorized came from an SVC use case (running non-authorized as much as possible). Can you name any PC instruction features that don't fill a niche we needed in SVC? Remember that there were a lot of tricks we used to get around SVC's limitations. As for "executing authorized code in other address spaces", I actually meant any address space. I was not thinking specifically about running code located in private which was another problem we had with SVC. Jon. On Thursday, August 29, 2019, 09:49:03 AM PDT, Tom Marchant <000a2a8c2020-dmarc-requ...@listserv.ua.edu> wrote: On Thu, 29 Aug 2019 04:22:02 +, Jon Perryman wrote: >The PC instruction is a replacement for SVC. Both instructions exist >solely to run authorized programs in other address spaces. No. The SVC instruction, as implemented by OS/360 and its descendants, exists to provide a service that requires execution in Supervisor state. The concepts of address spaces and authorized programs didn't exist until years later. While a common use case for PC routines is to execute code in another address space, that is not its only use case. Also, PC routines can be defined which receive control in problem state. -- Tom Marchant -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN
Re: Assembler :- PC Instruction
ETCRE et al are part of the setup prior to issuing the PC instruction; the actual implementation of the PC is a black box and need not be the same between models, as long as it complies with PoOps. -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 From: IBM Mainframe Discussion List on behalf of Jon Perryman Sent: Thursday, August 29, 2019 12:10 AM To: IBM-MAIN@LISTSERV.UA.EDU Subject: Re: Assembler :- PC Instruction For "who will perform the translation process", it's not going to be clear. First, rather than translation, the PC instruction builds the environment from the token. ETDEF defines the PC environment but ETCRE or ETCON could easily insert calls into the environment entry without us being aware. P/OPS only tells us the hardware side and we don't have access to the internals (e.g. establishing ARR). So the answer is we can't say for sure. Jon. On Wednesday, August 28, 2019, 12:36:10 AM PDT, SUBSCRIBE IBM-MAIN Anonymous wrote: Thanks for your response. Yes I agree that PC doesn't involve any interruption. "Principles of operations" manual clearly explains the PC translation process but I wanted to know "Who" will perform this translation process? For example we have "Dynamic Address translation" facility to transform Virtual addresses, and is there any similar facility to perform PC translation process. -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN
Re: Assembler :- PC Instruction
> The PC instruction is a replacement for SVC. That's one use case. What about privileged code that scheduled an SRB into another address space and waited for a cross-memory post? A PC is potentially much less overhead. > Both instructions exist solely to run authorized programs in other address > spaces. How did you run programs in another OS/360 address space. I don't see any time machines here. ;-) > If I remember correctly, You do; no SVRB, just a stack entry. -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 From: IBM Mainframe Discussion List on behalf of Jon Perryman Sent: Thursday, August 29, 2019 12:22 AM To: IBM-MAIN@LISTSERV.UA.EDU Subject: Re: Assembler :- PC Instruction The PC instruction is a replacement for SVC. Both instructions exist solely to run authorized programs in other address spaces. PC was designed to fix and simplify many of those problems with SVC. Some of the important problems addressed (not all): 1. 256 static defined SVC's replaced by dynamically assigned PC token that are fully under the products control without sysprog intervention (e.g. SVC table def). 2. SVC SRB replaced by simple xmem implementation that occurs automatically. 3. Abend recovery easily implemented in PC routine. 4. Eliminates the need for programs in CSA or SQA. PC routines should run as fast (probably faster) as an SVC. If I remember correctly, > If I remember correctly, PC's don't have an RB and use the linkage stack instead. Jon. On Wednesday, August 28, 2019, 09:23:28 AM PDT, Seymour J Metz wrote: I doubt that PC was ever intended as a replacement for, e.g., BASR. How does its performance stack up against SVC? -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN
Re: Assembler :- PC Instruction
In this case the term "address space was generic", referring to the range of permissible numbers. SV -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 From: IBM Mainframe Discussion List on behalf of Jon Perryman Sent: Thursday, August 29, 2019 12:38 AM To: IBM-MAIN@LISTSERV.UA.EDU Subject: Re: Assembler :- PC Instruction PC does not have a larger address space. It simply has the option to access other address spaces. Collisions for PC environments cannot occur because the PC instruction must use the token returned when you created the environment. The problem is passing this token to programs issuing the PC instruction. I believe IBM has some statically defined PC tokens. Jon. On Wednesday, August 28, 2019, 10:35:07 AM PDT, Seymour J Metz wrote: PC has a larger address space, but IBM still has to reserve numbers for its own use, and 3rd party vendors still must avoid collisions. -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN is limited to 8 bits. -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN
Re: Assembler :- PC Instruction
> This begs a question for me how do you measure the performance..? ObPedant ITYM raises. There are several ways you can measure performance, but the key questions, as always, are "What do you mean by performance?" and "Performance of what?" Tell me the answer you want and I'll write the benchmark to prove it's correct. -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 From: IBM Mainframe Discussion List on behalf of scott Ford Sent: Thursday, August 29, 2019 8:18 AM To: IBM-MAIN@LISTSERV.UA.EDU Subject: Re: Assembler :- PC Instruction Peter, This begs a question for me how do you measure the performance..? What I am seeing via the post and understanding performance matters even with the faster Z processors. Scott On Thu, Aug 29, 2019 at 7:45 AM Peter Relson wrote: > > You can do a BASR and STORAGE OBTAIN, STORAGE RELEASE and BR in less time > than a BAKR. > > > No you can't. > > > How does its performance stack up against SVC? > > > That's not a useful comparison. What is useful is "how does its > performance stack up against SVC plus the SVC interrupt handler". > > Peter Relson > z/OS Core Technology Design > > > -- > For IBM-MAIN subscribe / signoff / archive access instructions, > send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN > -- Scott Ford IDMWORKS z/OS Development -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN
Re: Assembler :- PC Instruction
SVC itself performs a simple function. SVC together with its interrupt handlers is not so simple. What with the serialization for the GETMAIN or whatever it uses these days, I'd expect it to be at least as expensive as PC. If you need to operate in another address space, add in the overhead of acquiring, scheduling and freeing SRBs. > The times that machine performance could be expressed in Million Instructions > Per Second are long gone. They've been gone for half a century, if they ever existed. -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 From: IBM Mainframe Discussion List on behalf of Vernooij, Kees (ITOP NM) - KLM Sent: Thursday, August 29, 2019 8:27 AM To: IBM-MAIN@LISTSERV.UA.EDU Subject: Re: Assembler :- PC Instruction "against SVC plus the SVC interrupt handler". Possibly also: Plus SVC code? The SVC instruction performs a function, the PC instruction does too. >From what I understood of the PC instruction: with 1 instruction you can now >execute a 'function' that might have taken pages of assembler instructions >before. The times that machine performance could be expressed in Million Instructions Per Second are long gone. Kees. > -Original Message- > From: IBM Mainframe Discussion List [mailto:IBM-MAIN@LISTSERV.UA.EDU] On > Behalf Of Peter Relson > Sent: 29 August, 2019 13:45 > To: IBM-MAIN@LISTSERV.UA.EDU > Subject: Re: Assembler :- PC Instruction > > > You can do a BASR and STORAGE OBTAIN, STORAGE RELEASE and BR in less time > than a BAKR. > > > No you can't. > > > How does its performance stack up against SVC? > > > That's not a useful comparison. What is useful is "how does its > performance stack up against SVC plus the SVC interrupt handler". > > Peter Relson > z/OS Core Technology Design > > > -- > For IBM-MAIN subscribe / signoff / archive access instructions, > send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN For information, services and offers, please visit our web site: http://secure-web.cisco.com/1yFCMng_oi34MeuWoGQVFSplOg6fpaFLyxdbGdQb9STPypzNLAxj2z3H1yPe4hmcGsoQrveXhGIGpIQn4y5avwq7BULLqLr7LDIdVd3uZfyPSdpqKPZLOf85a9_UOdAfEEkGjPnXcTp7oZjO72UlCrOrkWCx9XGTouvxIvkrdhdxx7mbiJCUcsSNwdIhGoKmSm_S4VqyCCu_-5BvvEZ79ciMla-Ce6L9JM5Ftywxolu5eN46Eq6qEk2Cf-Zcs5T9IkVQzK7gnyAmr3_tZBL1XW1EDny_9mYCBo58WeWGmKDzZaHMjFOWAKa7le7wuJMXxvxGhuhm_EyVpP7hsmqb89fuquitBk3uYlWjLHQFCW51CPwAUMtM3_g4RZTozHtzb/http%3A%2F%2Fwww.klm.com. This e-mail and any attachment may contain confidential and privileged material intended for the addressee only. If you are not the addressee, you are notified that no part of the e-mail or any attachment may be disclosed, copied or distributed, and that any other action related to this e-mail or attachment is strictly prohibited, and may be unlawful. If you have received this e-mail by error, please notify the sender immediately by return e-mail, and delete this message. Koninklijke Luchtvaart Maatschappij NV (KLM), its subsidiaries and/or its employees shall not be liable for the incorrect or incomplete transmission of this e-mail or any attachments, nor responsible for any delay in receipt. Koninklijke Luchtvaart Maatschappij N.V. (also known as KLM Royal Dutch Airlines) is registered in Amstelveen, The Netherlands, with registered number 33014286 -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN h the -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN
Re: Assembler :- PC Instruction
On Thu, 29 Aug 2019 04:22:02 +, Jon Perryman wrote: >The PC instruction is a replacement for SVC. Both instructions exist >solely to run authorized programs in other address spaces. No. The SVC instruction, as implemented by OS/360 and its descendants, exists to provide a service that requires execution in Supervisor state. The concepts of address spaces and authorized programs didn't exist until years later. While a common use case for PC routines is to execute code in another address space, that is not its only use case. Also, PC routines can be defined which receive control in problem state. -- Tom Marchant -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN
Re: Assembler :- PC Instruction
> how do you measure the performance..? For the PC instruction, performance is simply a curiosity and doesn't really matter. The alternatives are SVC and SSI. The benefits of PC far outweigh any possible savings by using SVC. The SSI is a special use case. As for measuring performance, is there any possible metric that would be meaningful and useful? Do you ignore some instruction options? Do you include OS support routines that are included after the instruction complete's (e.g. SVC interrupt handler). Jon.. On Thursday, August 29, 2019, 05:19:04 AM PDT, scott Ford wrote: Peter, This begs a question for me how do you measure the performance..? What I am seeing via the post and understanding performance matters even with the faster Z processors. Scott On Thu, Aug 29, 2019 at 7:45 AM Peter Relson wrote: > > You can do a BASR and STORAGE OBTAIN, STORAGE RELEASE and BR in less time > than a BAKR. > > > No you can't. > > > How does its performance stack up against SVC? > > > That's not a useful comparison. What is useful is "how does its > performance stack up against SVC plus the SVC interrupt handler". > > Peter Relson > z/OS Core Technology Design > > > -- > For IBM-MAIN subscribe / signoff / archive access instructions, > send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN > -- Scott Ford IDMWORKS z/OS Development -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN
Re: Assembler :- PC Instruction
Kees good point On Thu, Aug 29, 2019 at 8:29 AM Vernooij, Kees (ITOP NM) - KLM < kees.verno...@klm.com> wrote: > "against SVC plus the SVC interrupt handler". > Possibly also: Plus SVC code? > The SVC instruction performs a function, the PC instruction does too. > > From what I understood of the PC instruction: with 1 instruction you can > now execute a 'function' that might have taken pages of assembler > instructions before. > > The times that machine performance could be expressed in Million > Instructions Per Second are long gone. > > Kees. > > > -Original Message- > > From: IBM Mainframe Discussion List [mailto:IBM-MAIN@LISTSERV.UA.EDU] On > > Behalf Of Peter Relson > > Sent: 29 August, 2019 13:45 > > To: IBM-MAIN@LISTSERV.UA.EDU > > Subject: Re: Assembler :- PC Instruction > > > > > > You can do a BASR and STORAGE OBTAIN, STORAGE RELEASE and BR in less time > > than a BAKR. > > > > > > No you can't. > > > > > > How does its performance stack up against SVC? > > > > > > That's not a useful comparison. What is useful is "how does its > > performance stack up against SVC plus the SVC interrupt handler". > > > > Peter Relson > > z/OS Core Technology Design > > > > > > -- > > For IBM-MAIN subscribe / signoff / archive access instructions, > > send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN > > For information, services and offers, please visit our web site: > http://www.klm.com. This e-mail and any attachment may contain > confidential and privileged material intended for the addressee only. If > you are not the addressee, you are notified that no part of the e-mail or > any attachment may be disclosed, copied or distributed, and that any other > action related to this e-mail or attachment is strictly prohibited, and may > be unlawful. If you have received this e-mail by error, please notify the > sender immediately by return e-mail, and delete this message. > > Koninklijke Luchtvaart Maatschappij NV (KLM), its subsidiaries and/or its > employees shall not be liable for the incorrect or incomplete transmission > of this e-mail or any attachments, nor responsible for any delay in receipt. > Koninklijke Luchtvaart Maatschappij N.V. (also known as KLM Royal Dutch > Airlines) is registered in Amstelveen, The Netherlands, with registered > number 33014286 > > > -- > For IBM-MAIN subscribe / signoff / archive access instructions, > send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN > -- Scott Ford IDMWORKS z/OS Development -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN
Re: Assembler :- PC Instruction
"against SVC plus the SVC interrupt handler". Possibly also: Plus SVC code? The SVC instruction performs a function, the PC instruction does too. >From what I understood of the PC instruction: with 1 instruction you can now >execute a 'function' that might have taken pages of assembler instructions >before. The times that machine performance could be expressed in Million Instructions Per Second are long gone. Kees. > -Original Message- > From: IBM Mainframe Discussion List [mailto:IBM-MAIN@LISTSERV.UA.EDU] On > Behalf Of Peter Relson > Sent: 29 August, 2019 13:45 > To: IBM-MAIN@LISTSERV.UA.EDU > Subject: Re: Assembler :- PC Instruction > > > You can do a BASR and STORAGE OBTAIN, STORAGE RELEASE and BR in less time > than a BAKR. > > > No you can't. > > > How does its performance stack up against SVC? > > > That's not a useful comparison. What is useful is "how does its > performance stack up against SVC plus the SVC interrupt handler". > > Peter Relson > z/OS Core Technology Design > > > -- > For IBM-MAIN subscribe / signoff / archive access instructions, > send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN For information, services and offers, please visit our web site: http://www.klm.com. This e-mail and any attachment may contain confidential and privileged material intended for the addressee only. If you are not the addressee, you are notified that no part of the e-mail or any attachment may be disclosed, copied or distributed, and that any other action related to this e-mail or attachment is strictly prohibited, and may be unlawful. If you have received this e-mail by error, please notify the sender immediately by return e-mail, and delete this message. Koninklijke Luchtvaart Maatschappij NV (KLM), its subsidiaries and/or its employees shall not be liable for the incorrect or incomplete transmission of this e-mail or any attachments, nor responsible for any delay in receipt. Koninklijke Luchtvaart Maatschappij N.V. (also known as KLM Royal Dutch Airlines) is registered in Amstelveen, The Netherlands, with registered number 33014286 -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN
Re: Assembler :- PC Instruction
Peter, This begs a question for me how do you measure the performance..? What I am seeing via the post and understanding performance matters even with the faster Z processors. Scott On Thu, Aug 29, 2019 at 7:45 AM Peter Relson wrote: > > You can do a BASR and STORAGE OBTAIN, STORAGE RELEASE and BR in less time > than a BAKR. > > > No you can't. > > > How does its performance stack up against SVC? > > > That's not a useful comparison. What is useful is "how does its > performance stack up against SVC plus the SVC interrupt handler". > > Peter Relson > z/OS Core Technology Design > > > -- > For IBM-MAIN subscribe / signoff / archive access instructions, > send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN > -- Scott Ford IDMWORKS z/OS Development -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN
Re: Assembler :- PC Instruction
You can do a BASR and STORAGE OBTAIN, STORAGE RELEASE and BR in less time than a BAKR. No you can't. How does its performance stack up against SVC? That's not a useful comparison. What is useful is "how does its performance stack up against SVC plus the SVC interrupt handler". Peter Relson z/OS Core Technology Design -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN
Re: Assembler :- PC Instruction
>> PC has a larger address space, but IBM still has to reserve numbers for its >> own use, and 3rd party vendors still must avoid collisions. Avoid collisions? PC number is formed by ETE sequence number suffixed to LX number returned by LXRES. As someone who has written quite a few software products that provide PC routines, I have never had to worry about collisions with IBM (or other ISV) software. -Original Message- From: IBM Mainframe Discussion List On Behalf Of Seymour J Metz Sent: Wednesday, August 28, 2019 6:35 PM To: IBM-MAIN@LISTSERV.UA.EDU Subject: Re: Assembler :- PC Instruction PC has a larger address space, but IBM still has to reserve numbers for its own use, and 3rd party vendors still must avoid collisions. -- Shmuel (Seymour J.) Metz https://nam01.safelinks.protection.outlook.com/?url=http:%2F%2Fmason.gmu.edu%2F~smetz3data=02%7C01%7C%7Cdc0dd6d386f14dd64c6708d72bde10d2%7C79544c1eed224879a082b67a9a672aae%7C0%7C0%7C637026105076814212sdata=g0T%2FxZM94KxBQ0MVmkG%2B1WyyUxqsn6v4qL8W6cuyMfU%3Dreserved=0 From: IBM Mainframe Discussion List on behalf of Charles Mills Sent: Wednesday, August 28, 2019 1:09 PM To: IBM-MAIN@LISTSERV.UA.EDU Subject: Re: Assembler :- PC Instruction Correct me if I am wrong. I don't pretend to be an expert on this subject. I think of SVCs as hailing from the era of centralized monolithic operating system construction. I would guess that IBM had an "SVC number committee" and they sat down and said "SVC 1 shall do this; SVC 2 shall do that; and so forth." Yes, you can add a user SVC, but fundamentally the SVC has a fixed architecture of 256 possibilities, requiring some sort of central administration. Chris and I cannot both add an SVC 201 to our customers' computers. (Yes, having the number in a config file would be a workaround.) PCs are inherently much more decentralized. There can be a nearly unlimited number of PCs. Chris and I can both add a PC to our customers' computers without much fear of a collision. And yes, not to disagree with what Chris says, the architecture of SVC is more suited to a single address space, or at least an addressing scheme in which all "privileged services" are at least partially resident in common address space. Charles -Original Message- From: IBM Mainframe Discussion List [mailto:IBM-MAIN@LISTSERV.UA.EDU] On Behalf Of Christopher Y. Blaicher Sent: Wednesday, August 28, 2019 9:48 AM To: IBM-MAIN@LISTSERV.UA.EDU Subject: Re: Assembler :- PC Instruction Never measured SVC vs PC. While in some cases PC and SVC are similar, in many ways PC is far superior to SVC. It can be local or globally defined and it can be dynamically defined and removed. (OK, so can an SVC be added and deleted, but I think PC's are easier). Also, an SVC can't do space switching. -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN Rocket Software, Inc. and subsidiaries ■ 77 Fourth Avenue, Waltham MA 02451 ■ Main Office Toll Free Number: +1 855.577.4323 Contact Customer Support: https://my.rocketsoftware.com/RocketCommunity/RCEmailSupport Unsubscribe from Marketing Messages/Manage Your Subscription Preferences - http://www.rocketsoftware.com/manage-your-email-preferences Privacy Policy - http://www.rocketsoftware.com/company/legal/privacy-policy This communication and any attachments may contain confidential information of Rocket Software, Inc. All unauthorized use, disclosure or distribution is prohibited. If you are not the intended recipient, please notify Rocket Software immediately and destroy all copies of this communication. Thank you. -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN
Re: Assembler :- PC Instruction
PC does not have a larger address space. It simply has the option to access other address spaces. Collisions for PC environments cannot occur because the PC instruction must use the token returned when you created the environment. The problem is passing this token to programs issuing the PC instruction. I believe IBM has some statically defined PC tokens. Jon. On Wednesday, August 28, 2019, 10:35:07 AM PDT, Seymour J Metz wrote: PC has a larger address space, but IBM still has to reserve numbers for its own use, and 3rd party vendors still must avoid collisions. -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN
Re: Assembler :- PC Instruction
The PC instruction is a replacement for SVC. Both instructions exist solely to run authorized programs in other address spaces. PC was designed to fix and simplify many of those problems with SVC. Some of the important problems addressed (not all): 1. 256 static defined SVC's replaced by dynamically assigned PC token that are fully under the products control without sysprog intervention (e.g. SVC table def). 2. SVC SRB replaced by simple xmem implementation that occurs automatically. 3. Abend recovery easily implemented in PC routine. 4. Eliminates the need for programs in CSA or SQA. PC routines should run as fast (probably faster) as an SVC. If I remember correctly, PC's don't have an RB and use the linkage stack instead. Jon. On Wednesday, August 28, 2019, 09:23:28 AM PDT, Seymour J Metz wrote: I doubt that PC was ever intended as a replacement for, e.g., BASR. How does its performance stack up against SVC? -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN
Re: Assembler :- PC Instruction
For "who will perform the translation process", it's not going to be clear. First, rather than translation, the PC instruction builds the environment from the token. ETDEF defines the PC environment but ETCRE or ETCON could easily insert calls into the environment entry without us being aware. P/OPS only tells us the hardware side and we don't have access to the internals (e.g. establishing ARR). So the answer is we can't say for sure. Jon. On Wednesday, August 28, 2019, 12:36:10 AM PDT, SUBSCRIBE IBM-MAIN Anonymous wrote: Thanks for your response. Yes I agree that PC doesn't involve any interruption. "Principles of operations" manual clearly explains the PC translation process but I wanted to know "Who" will perform this translation process? For example we have "Dynamic Address translation" facility to transform Virtual addresses, and is there any similar facility to perform PC translation process. -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN
Re: Assembler :- PC Instruction
Thanks everyone for all your inputs. -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN
Re: Assembler :- PC Instruction
One other advantage of PC over SVC, you can issue them in SRB mode. A very big thing if you are running on zIIP processors. Chris Blaicher Technical Architect Syncsort, Inc. -Original Message- From: IBM Mainframe Discussion List [mailto:IBM-MAIN@LISTSERV.UA.EDU] On Behalf Of Seymour J Metz Sent: Wednesday, August 28, 2019 1:40 PM To: IBM-MAIN@LISTSERV.UA.EDU Subject: Re: Assembler :- PC Instruction An SVC can schedule an SRB into another address space; that may be more overhead, but it's still space switching. But, yes, there are far fewer use cases for new VCs these days. -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 From: IBM Mainframe Discussion List on behalf of Christopher Y. Blaicher Sent: Wednesday, August 28, 2019 12:48 PM To: IBM-MAIN@LISTSERV.UA.EDU Subject: Re: Assembler :- PC Instruction Never measured SVC vs PC. While in some cases PC and SVC are similar, in many ways PC is far superior to SVC. It can be local or globally defined and it can be dynamically defined and removed. (OK, so can an SVC be added and deleted, but I think PC's are easier). Also, an SVC can't do space switching. Chris Blaicher Technical Architect Syncsort, Inc. -Original Message- From: IBM Mainframe Discussion List [mailto:IBM-MAIN@LISTSERV.UA.EDU] On Behalf Of Seymour J Metz Sent: Wednesday, August 28, 2019 12:23 PM To: IBM-MAIN@LISTSERV.UA.EDU Subject: Re: Assembler :- PC Instruction I doubt that PC was ever intended as a replacement for, e.g., BASR. How does its performance stack up against SVC? -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 From: IBM Mainframe Discussion List on behalf of Christopher Y. Blaicher Sent: Wednesday, August 28, 2019 12:19 PM To: IBM-MAIN@LISTSERV.UA.EDU Subject: Re: Assembler :- PC Instruction PC and BAKR, which is another stacking type instruction, are not cheap. You can do a BASR and STORAGE OBTAIN, STORAGE RELEASE and BR in less time than a BAKR. I do not know for sure, but I would guess that 99% of what PC, BAKR and PR do is millicode, and they do a lot. Chris Blaicher Technical Architect Syncsort, Inc. -Original Message- From: IBM Mainframe Discussion List [mailto:IBM-MAIN@LISTSERV.UA.EDU] On Behalf Of scott Ford Sent: Wednesday, August 28, 2019 11:21 AM To: IBM-MAIN@LISTSERV.UA.EDU Subject: Re: Assembler :- PC Instruction I feel it's important how to use the instruction and it's pros and cons. I am not sure how important speed of instructions or width , halfword or full word are that pressing of an issue with today's processors, but that's my opinion. Scott On Wed, Aug 28, 2019 at 11:18 AM scott Ford wrote: > Charles, > > Exactly, what is being done under the covers, i.e; microcode etc .. > > Scott > > On Wed, Aug 28, 2019 at 10:49 AM Tony Harminc wrote: > >> On Wed, 28 Aug 2019 at 09:59, Charles Mills wrote: >> >> > In answer to your question, I guess the answer is no. There is a >> > DAT >> "facility" (some of us remember when there was a DAT box!) but no, >> there is no named "PC facility" any more than there is a "BAL >> facility." It's just part of the processors. >> >> It's arguable that ASN translation is (usually) the part of the >> architecture that corresponds best to DAT in the context of PC and PR >> instruction processing. But not all PCs invoke ASN translation, and >> those that do do it a bit differently than how it is described in >> Chapter 3. >> >> But really, as Binyamin said, the excruciating details of what PC >> *does* are covered in the POPS, both under the PC instruction itself, >> and in Chapter 5 in the section "Stacking Process" under "Linkage >> Stack Operations". >> >> Tony H. >> >> - >> - For IBM-MAIN subscribe / signoff / archive access instructions, >> send email to lists...@listserv.ua.edu with the message: INFO >> IBM-MAIN >> > -- > Scott Ford > IDMWORKS > z/OS Development > -- Scott Ford IDMWORKS z/OS Development -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@list
Re: Assembler :- PC Instruction
An SVC can schedule an SRB into another address space; that may be more overhead, but it's still space switching. But, yes, there are far fewer use cases for new VCs these days. -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 From: IBM Mainframe Discussion List on behalf of Christopher Y. Blaicher Sent: Wednesday, August 28, 2019 12:48 PM To: IBM-MAIN@LISTSERV.UA.EDU Subject: Re: Assembler :- PC Instruction Never measured SVC vs PC. While in some cases PC and SVC are similar, in many ways PC is far superior to SVC. It can be local or globally defined and it can be dynamically defined and removed. (OK, so can an SVC be added and deleted, but I think PC's are easier). Also, an SVC can't do space switching. Chris Blaicher Technical Architect Syncsort, Inc. -Original Message- From: IBM Mainframe Discussion List [mailto:IBM-MAIN@LISTSERV.UA.EDU] On Behalf Of Seymour J Metz Sent: Wednesday, August 28, 2019 12:23 PM To: IBM-MAIN@LISTSERV.UA.EDU Subject: Re: Assembler :- PC Instruction I doubt that PC was ever intended as a replacement for, e.g., BASR. How does its performance stack up against SVC? -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 From: IBM Mainframe Discussion List on behalf of Christopher Y. Blaicher Sent: Wednesday, August 28, 2019 12:19 PM To: IBM-MAIN@LISTSERV.UA.EDU Subject: Re: Assembler :- PC Instruction PC and BAKR, which is another stacking type instruction, are not cheap. You can do a BASR and STORAGE OBTAIN, STORAGE RELEASE and BR in less time than a BAKR. I do not know for sure, but I would guess that 99% of what PC, BAKR and PR do is millicode, and they do a lot. Chris Blaicher Technical Architect Syncsort, Inc. -Original Message- From: IBM Mainframe Discussion List [mailto:IBM-MAIN@LISTSERV.UA.EDU] On Behalf Of scott Ford Sent: Wednesday, August 28, 2019 11:21 AM To: IBM-MAIN@LISTSERV.UA.EDU Subject: Re: Assembler :- PC Instruction I feel it's important how to use the instruction and it's pros and cons. I am not sure how important speed of instructions or width , halfword or full word are that pressing of an issue with today's processors, but that's my opinion. Scott On Wed, Aug 28, 2019 at 11:18 AM scott Ford wrote: > Charles, > > Exactly, what is being done under the covers, i.e; microcode etc .. > > Scott > > On Wed, Aug 28, 2019 at 10:49 AM Tony Harminc wrote: > >> On Wed, 28 Aug 2019 at 09:59, Charles Mills wrote: >> >> > In answer to your question, I guess the answer is no. There is a >> > DAT >> "facility" (some of us remember when there was a DAT box!) but no, >> there is no named "PC facility" any more than there is a "BAL >> facility." It's just part of the processors. >> >> It's arguable that ASN translation is (usually) the part of the >> architecture that corresponds best to DAT in the context of PC and PR >> instruction processing. But not all PCs invoke ASN translation, and >> those that do do it a bit differently than how it is described in >> Chapter 3. >> >> But really, as Binyamin said, the excruciating details of what PC >> *does* are covered in the POPS, both under the PC instruction itself, >> and in Chapter 5 in the section "Stacking Process" under "Linkage >> Stack Operations". >> >> Tony H. >> >> - >> - For IBM-MAIN subscribe / signoff / archive access instructions, >> send email to lists...@listserv.ua.edu with the message: INFO >> IBM-MAIN >> > -- > Scott Ford > IDMWORKS > z/OS Development > -- Scott Ford IDMWORKS z/OS Development -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN
Re: Assembler :- PC Instruction
PC has a larger address space, but IBM still has to reserve numbers for its own use, and 3rd party vendors still must avoid collisions. -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 From: IBM Mainframe Discussion List on behalf of Charles Mills Sent: Wednesday, August 28, 2019 1:09 PM To: IBM-MAIN@LISTSERV.UA.EDU Subject: Re: Assembler :- PC Instruction Correct me if I am wrong. I don't pretend to be an expert on this subject. I think of SVCs as hailing from the era of centralized monolithic operating system construction. I would guess that IBM had an "SVC number committee" and they sat down and said "SVC 1 shall do this; SVC 2 shall do that; and so forth." Yes, you can add a user SVC, but fundamentally the SVC has a fixed architecture of 256 possibilities, requiring some sort of central administration. Chris and I cannot both add an SVC 201 to our customers' computers. (Yes, having the number in a config file would be a workaround.) PCs are inherently much more decentralized. There can be a nearly unlimited number of PCs. Chris and I can both add a PC to our customers' computers without much fear of a collision. And yes, not to disagree with what Chris says, the architecture of SVC is more suited to a single address space, or at least an addressing scheme in which all "privileged services" are at least partially resident in common address space. Charles -Original Message- From: IBM Mainframe Discussion List [mailto:IBM-MAIN@LISTSERV.UA.EDU] On Behalf Of Christopher Y. Blaicher Sent: Wednesday, August 28, 2019 9:48 AM To: IBM-MAIN@LISTSERV.UA.EDU Subject: Re: Assembler :- PC Instruction Never measured SVC vs PC. While in some cases PC and SVC are similar, in many ways PC is far superior to SVC. It can be local or globally defined and it can be dynamically defined and removed. (OK, so can an SVC be added and deleted, but I think PC's are easier). Also, an SVC can't do space switching. -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN
Re: Assembler :- PC Instruction
Correct me if I am wrong. I don't pretend to be an expert on this subject. I think of SVCs as hailing from the era of centralized monolithic operating system construction. I would guess that IBM had an "SVC number committee" and they sat down and said "SVC 1 shall do this; SVC 2 shall do that; and so forth." Yes, you can add a user SVC, but fundamentally the SVC has a fixed architecture of 256 possibilities, requiring some sort of central administration. Chris and I cannot both add an SVC 201 to our customers' computers. (Yes, having the number in a config file would be a workaround.) PCs are inherently much more decentralized. There can be a nearly unlimited number of PCs. Chris and I can both add a PC to our customers' computers without much fear of a collision. And yes, not to disagree with what Chris says, the architecture of SVC is more suited to a single address space, or at least an addressing scheme in which all "privileged services" are at least partially resident in common address space. Charles -Original Message- From: IBM Mainframe Discussion List [mailto:IBM-MAIN@LISTSERV.UA.EDU] On Behalf Of Christopher Y. Blaicher Sent: Wednesday, August 28, 2019 9:48 AM To: IBM-MAIN@LISTSERV.UA.EDU Subject: Re: Assembler :- PC Instruction Never measured SVC vs PC. While in some cases PC and SVC are similar, in many ways PC is far superior to SVC. It can be local or globally defined and it can be dynamically defined and removed. (OK, so can an SVC be added and deleted, but I think PC's are easier). Also, an SVC can't do space switching. -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN
Re: Assembler :- PC Instruction
Never measured SVC vs PC. While in some cases PC and SVC are similar, in many ways PC is far superior to SVC. It can be local or globally defined and it can be dynamically defined and removed. (OK, so can an SVC be added and deleted, but I think PC's are easier). Also, an SVC can't do space switching. Chris Blaicher Technical Architect Syncsort, Inc. -Original Message- From: IBM Mainframe Discussion List [mailto:IBM-MAIN@LISTSERV.UA.EDU] On Behalf Of Seymour J Metz Sent: Wednesday, August 28, 2019 12:23 PM To: IBM-MAIN@LISTSERV.UA.EDU Subject: Re: Assembler :- PC Instruction I doubt that PC was ever intended as a replacement for, e.g., BASR. How does its performance stack up against SVC? -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 From: IBM Mainframe Discussion List on behalf of Christopher Y. Blaicher Sent: Wednesday, August 28, 2019 12:19 PM To: IBM-MAIN@LISTSERV.UA.EDU Subject: Re: Assembler :- PC Instruction PC and BAKR, which is another stacking type instruction, are not cheap. You can do a BASR and STORAGE OBTAIN, STORAGE RELEASE and BR in less time than a BAKR. I do not know for sure, but I would guess that 99% of what PC, BAKR and PR do is millicode, and they do a lot. Chris Blaicher Technical Architect Syncsort, Inc. -Original Message- From: IBM Mainframe Discussion List [mailto:IBM-MAIN@LISTSERV.UA.EDU] On Behalf Of scott Ford Sent: Wednesday, August 28, 2019 11:21 AM To: IBM-MAIN@LISTSERV.UA.EDU Subject: Re: Assembler :- PC Instruction I feel it's important how to use the instruction and it's pros and cons. I am not sure how important speed of instructions or width , halfword or full word are that pressing of an issue with today's processors, but that's my opinion. Scott On Wed, Aug 28, 2019 at 11:18 AM scott Ford wrote: > Charles, > > Exactly, what is being done under the covers, i.e; microcode etc .. > > Scott > > On Wed, Aug 28, 2019 at 10:49 AM Tony Harminc wrote: > >> On Wed, 28 Aug 2019 at 09:59, Charles Mills wrote: >> >> > In answer to your question, I guess the answer is no. There is a >> > DAT >> "facility" (some of us remember when there was a DAT box!) but no, >> there is no named "PC facility" any more than there is a "BAL >> facility." It's just part of the processors. >> >> It's arguable that ASN translation is (usually) the part of the >> architecture that corresponds best to DAT in the context of PC and PR >> instruction processing. But not all PCs invoke ASN translation, and >> those that do do it a bit differently than how it is described in >> Chapter 3. >> >> But really, as Binyamin said, the excruciating details of what PC >> *does* are covered in the POPS, both under the PC instruction itself, >> and in Chapter 5 in the section "Stacking Process" under "Linkage >> Stack Operations". >> >> Tony H. >> >> - >> - For IBM-MAIN subscribe / signoff / archive access instructions, >> send email to lists...@listserv.ua.edu with the message: INFO >> IBM-MAIN >> > -- > Scott Ford > IDMWORKS > z/OS Development > -- Scott Ford IDMWORKS z/OS Development -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN
Re: Assembler :- PC Instruction
I doubt that PC was ever intended as a replacement for, e.g., BASR. How does its performance stack up against SVC? -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 From: IBM Mainframe Discussion List on behalf of Christopher Y. Blaicher Sent: Wednesday, August 28, 2019 12:19 PM To: IBM-MAIN@LISTSERV.UA.EDU Subject: Re: Assembler :- PC Instruction PC and BAKR, which is another stacking type instruction, are not cheap. You can do a BASR and STORAGE OBTAIN, STORAGE RELEASE and BR in less time than a BAKR. I do not know for sure, but I would guess that 99% of what PC, BAKR and PR do is millicode, and they do a lot. Chris Blaicher Technical Architect Syncsort, Inc. -Original Message- From: IBM Mainframe Discussion List [mailto:IBM-MAIN@LISTSERV.UA.EDU] On Behalf Of scott Ford Sent: Wednesday, August 28, 2019 11:21 AM To: IBM-MAIN@LISTSERV.UA.EDU Subject: Re: Assembler :- PC Instruction I feel it’s important how to use the instruction and it’s pros and cons. I am not sure how important speed of instructions or width , halfword or full word are that pressing of an issue with today’s processors, but that’s my opinion. Scott On Wed, Aug 28, 2019 at 11:18 AM scott Ford wrote: > Charles, > > Exactly, what is being done under the covers, i.e; microcode etc .. > > Scott > > On Wed, Aug 28, 2019 at 10:49 AM Tony Harminc wrote: > >> On Wed, 28 Aug 2019 at 09:59, Charles Mills wrote: >> >> > In answer to your question, I guess the answer is no. There is a >> > DAT >> "facility" (some of us remember when there was a DAT box!) but no, >> there is no named "PC facility" any more than there is a "BAL >> facility." It's just part of the processors. >> >> It's arguable that ASN translation is (usually) the part of the >> architecture that corresponds best to DAT in the context of PC and PR >> instruction processing. But not all PCs invoke ASN translation, and >> those that do do it a bit differently than how it is described in >> Chapter 3. >> >> But really, as Binyamin said, the excruciating details of what PC >> *does* are covered in the POPS, both under the PC instruction itself, >> and in Chapter 5 in the section "Stacking Process" under "Linkage >> Stack Operations". >> >> Tony H. >> >> - >> - For IBM-MAIN subscribe / signoff / archive access instructions, >> send email to lists...@listserv.ua.edu with the message: INFO >> IBM-MAIN >> > -- > Scott Ford > IDMWORKS > z/OS Development > -- Scott Ford IDMWORKS z/OS Development -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN
Re: Assembler :- PC Instruction
PC and BAKR, which is another stacking type instruction, are not cheap. You can do a BASR and STORAGE OBTAIN, STORAGE RELEASE and BR in less time than a BAKR. I do not know for sure, but I would guess that 99% of what PC, BAKR and PR do is millicode, and they do a lot. Chris Blaicher Technical Architect Syncsort, Inc. -Original Message- From: IBM Mainframe Discussion List [mailto:IBM-MAIN@LISTSERV.UA.EDU] On Behalf Of scott Ford Sent: Wednesday, August 28, 2019 11:21 AM To: IBM-MAIN@LISTSERV.UA.EDU Subject: Re: Assembler :- PC Instruction I feel it’s important how to use the instruction and it’s pros and cons. I am not sure how important speed of instructions or width , halfword or full word are that pressing of an issue with today’s processors, but that’s my opinion. Scott On Wed, Aug 28, 2019 at 11:18 AM scott Ford wrote: > Charles, > > Exactly, what is being done under the covers, i.e; microcode etc .. > > Scott > > On Wed, Aug 28, 2019 at 10:49 AM Tony Harminc wrote: > >> On Wed, 28 Aug 2019 at 09:59, Charles Mills wrote: >> >> > In answer to your question, I guess the answer is no. There is a >> > DAT >> "facility" (some of us remember when there was a DAT box!) but no, >> there is no named "PC facility" any more than there is a "BAL >> facility." It's just part of the processors. >> >> It's arguable that ASN translation is (usually) the part of the >> architecture that corresponds best to DAT in the context of PC and PR >> instruction processing. But not all PCs invoke ASN translation, and >> those that do do it a bit differently than how it is described in >> Chapter 3. >> >> But really, as Binyamin said, the excruciating details of what PC >> *does* are covered in the POPS, both under the PC instruction itself, >> and in Chapter 5 in the section "Stacking Process" under "Linkage >> Stack Operations". >> >> Tony H. >> >> - >> - For IBM-MAIN subscribe / signoff / archive access instructions, >> send email to lists...@listserv.ua.edu with the message: INFO >> IBM-MAIN >> > -- > Scott Ford > IDMWORKS > z/OS Development > -- Scott Ford IDMWORKS z/OS Development -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN
Re: Assembler :- PC Instruction
PoOps describes the DAT facility, but it doesn't, and shouldn't, describe who implements it. Like DAT, PC, PR et al are black boxes; you are supposed to program to the architecture, not to the implementation on any specific model. -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 From: IBM Mainframe Discussion List on behalf of SUBSCRIBE IBM-MAIN Anonymous Sent: Wednesday, August 28, 2019 3:35 AM To: IBM-MAIN@LISTSERV.UA.EDU Subject: Re: Assembler :- PC Instruction Thanks for your response. Yes I agree that PC doesn't involve any interruption. "Principles of operations" manual clearly explains the PC translation process but I wanted to know "Who" will perform this translation process? For example we have "Dynamic Address translation" facility to transform Virtual addresses, and is there any similar facility to perform PC translation process. -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN
Re: Assembler :- PC Instruction
I feel it’s important how to use the instruction and it’s pros and cons. I am not sure how important speed of instructions or width , halfword or full word are that pressing of an issue with today’s processors, but that’s my opinion. Scott On Wed, Aug 28, 2019 at 11:18 AM scott Ford wrote: > Charles, > > Exactly, what is being done under the covers, i.e; microcode etc .. > > Scott > > On Wed, Aug 28, 2019 at 10:49 AM Tony Harminc wrote: > >> On Wed, 28 Aug 2019 at 09:59, Charles Mills wrote: >> >> > In answer to your question, I guess the answer is no. There is a DAT >> "facility" (some of us remember when there was a DAT box!) but no, there is >> no named "PC facility" any more than there is a "BAL facility." It's just >> part of the processors. >> >> It's arguable that ASN translation is (usually) the part of the >> architecture that corresponds best to DAT in the context of PC and PR >> instruction processing. But not all PCs invoke ASN translation, and >> those that do do it a bit differently than how it is described in >> Chapter 3. >> >> But really, as Binyamin said, the excruciating details of what PC >> *does* are covered in the POPS, both under the PC instruction itself, >> and in Chapter 5 in the section "Stacking Process" under "Linkage >> Stack Operations". >> >> Tony H. >> >> -- >> For IBM-MAIN subscribe / signoff / archive access instructions, >> send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN >> > -- > Scott Ford > IDMWORKS > z/OS Development > -- Scott Ford IDMWORKS z/OS Development -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN
Re: Assembler :- PC Instruction
Charles, Exactly, what is being done under the covers, i.e; microcode etc .. Scott On Wed, Aug 28, 2019 at 10:49 AM Tony Harminc wrote: > On Wed, 28 Aug 2019 at 09:59, Charles Mills wrote: > > > In answer to your question, I guess the answer is no. There is a DAT > "facility" (some of us remember when there was a DAT box!) but no, there is > no named "PC facility" any more than there is a "BAL facility." It's just > part of the processors. > > It's arguable that ASN translation is (usually) the part of the > architecture that corresponds best to DAT in the context of PC and PR > instruction processing. But not all PCs invoke ASN translation, and > those that do do it a bit differently than how it is described in > Chapter 3. > > But really, as Binyamin said, the excruciating details of what PC > *does* are covered in the POPS, both under the PC instruction itself, > and in Chapter 5 in the section "Stacking Process" under "Linkage > Stack Operations". > > Tony H. > > -- > For IBM-MAIN subscribe / signoff / archive access instructions, > send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN > -- Scott Ford IDMWORKS z/OS Development -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN
Re: Assembler :- PC Instruction
On Wed, 28 Aug 2019 at 09:59, Charles Mills wrote: > In answer to your question, I guess the answer is no. There is a DAT > "facility" (some of us remember when there was a DAT box!) but no, there is > no named "PC facility" any more than there is a "BAL facility." It's just > part of the processors. It's arguable that ASN translation is (usually) the part of the architecture that corresponds best to DAT in the context of PC and PR instruction processing. But not all PCs invoke ASN translation, and those that do do it a bit differently than how it is described in Chapter 3. But really, as Binyamin said, the excruciating details of what PC *does* are covered in the POPS, both under the PC instruction itself, and in Chapter 5 in the section "Stacking Process" under "Linkage Stack Operations". Tony H. -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN
Re: Assembler :- PC Instruction
A PC is just, as the name implies, a 'CALL' instruction. Think of it as an advanced and somewhat different form of Branch and Link (BAL). A BAL sets the new instruction address; a PC may set the address, the AMODE, even the address space. The stuff described in the PoOp happens, just like it does for every other instruction. Exactly how it happens? Only the hardware folks at IBM know. Some combination of silicon and other facilities. In answer to your question, I guess the answer is no. There is a DAT "facility" (some of us remember when there was a DAT box!) but no, there is no named "PC facility" any more than there is a "BAL facility." It's just part of the processors. Charles -Original Message- From: IBM Mainframe Discussion List [mailto:IBM-MAIN@LISTSERV.UA.EDU] On Behalf Of SUBSCRIBE IBM-MAIN Anonymous Sent: Wednesday, August 28, 2019 12:36 AM To: IBM-MAIN@LISTSERV.UA.EDU Subject: Re: Assembler :- PC Instruction Thanks for your response. Yes I agree that PC doesn't involve any interruption. "Principles of operations" manual clearly explains the PC translation process but I wanted to know "Who" will perform this translation process? For example we have "Dynamic Address translation" facility to transform Virtual addresses, and is there any similar facility to perform PC translation process. -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN
Re: Assembler :- PC Instruction
On Wed, 28 Aug 2019 02:35:47 -0500 SUBSCRIBE IBM-MAIN Anonymous wrote: :>Thanks for your response. Yes I agree that PC doesn't involve any interruption. "Principles of operations" manual clearly explains the PC translation process but I wanted to know "Who" will perform this translation process? For example we have "Dynamic Address translation" facility to transform Virtual addresses, and is there any similar facility to perform PC translation process. I doubt that it is in the silicon, but it may be. Otherwise microcode. And probably hardware dependent. -- Binyamin Dissen http://www.dissensoftware.com Director, Dissen Software, Bar & Grill - Israel Should you use the mailblocks package and expect a response from me, you should preauthorize the dissensoftware.com domain. I very rarely bother responding to challenge/response systems, especially those from irresponsible companies. -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN
Re: Assembler :- PC Instruction
Thanks for your response. Yes I agree that PC doesn't involve any interruption. "Principles of operations" manual clearly explains the PC translation process but I wanted to know "Who" will perform this translation process? For example we have "Dynamic Address translation" facility to transform Virtual addresses, and is there any similar facility to perform PC translation process. -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN
Re: Assembler :- PC Instruction
Well . Actually most of a new PSW is loaded. The instruction address, AMODE and PSW key may be changed. The POPs describing the PC instruction goes into excruciating details on how it works. On Wed, 28 Aug 2019 07:03:38 + "Vernooij, Kees (ITOP NM) - KLM" wrote: :>A PC instruction is just an Instruction, not an Interrupt, so there is no Interrupt handler involved and no new PSW loaded. :> :>Kees. :> :> :>> -Original Message- :>> From: IBM Mainframe Discussion List [mailto:IBM-MAIN@LISTSERV.UA.EDU] On :>> Behalf Of SUBSCRIBE IBM-MAIN Anonymous :>> Sent: 28 August, 2019 8:36 :>> To: IBM-MAIN@LISTSERV.UA.EDU :>> Subject: Assembler :- PC Instruction :>> :>> I have a question on PC instruction for which I have been looking for an :>> answer for quite sometime now. According to "Priciples of operations" :>> manual, execution of an SVC instruction causes a new PSW to be loaded from :>> x'1C0' (SVC FLIH), and program interruption causes a new PSW loaded from :>> x'1D0' (Program Interruption FLIH). Now my question is what happens when a :>> "PC" instruction is executed. Does a new PSW gets loaded from a pre- :>> determined location (like SVC/program interrruption) or it's all handled :>> through some micro code? -- Binyamin Dissen http://www.dissensoftware.com Director, Dissen Software, Bar & Grill - Israel Should you use the mailblocks package and expect a response from me, you should preauthorize the dissensoftware.com domain. I very rarely bother responding to challenge/response systems, especially those from irresponsible companies. -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN
Re: Assembler :- PC Instruction
A PC instruction is just an Instruction, not an Interrupt, so there is no Interrupt handler involved and no new PSW loaded. Kees. > -Original Message- > From: IBM Mainframe Discussion List [mailto:IBM-MAIN@LISTSERV.UA.EDU] On > Behalf Of SUBSCRIBE IBM-MAIN Anonymous > Sent: 28 August, 2019 8:36 > To: IBM-MAIN@LISTSERV.UA.EDU > Subject: Assembler :- PC Instruction > > I have a question on PC instruction for which I have been looking for an > answer for quite sometime now. According to "Priciples of operations" > manual, execution of an SVC instruction causes a new PSW to be loaded from > x'1C0' (SVC FLIH), and program interruption causes a new PSW loaded from > x'1D0' (Program Interruption FLIH). Now my question is what happens when a > "PC" instruction is executed. Does a new PSW gets loaded from a pre- > determined location (like SVC/program interrruption) or it's all handled > through some micro code? > > -- > For IBM-MAIN subscribe / signoff / archive access instructions, > send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN For information, services and offers, please visit our web site: http://www.klm.com. This e-mail and any attachment may contain confidential and privileged material intended for the addressee only. If you are not the addressee, you are notified that no part of the e-mail or any attachment may be disclosed, copied or distributed, and that any other action related to this e-mail or attachment is strictly prohibited, and may be unlawful. If you have received this e-mail by error, please notify the sender immediately by return e-mail, and delete this message. Koninklijke Luchtvaart Maatschappij NV (KLM), its subsidiaries and/or its employees shall not be liable for the incorrect or incomplete transmission of this e-mail or any attachments, nor responsible for any delay in receipt. Koninklijke Luchtvaart Maatschappij N.V. (also known as KLM Royal Dutch Airlines) is registered in Amstelveen, The Netherlands, with registered number 33014286 -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN
Assembler :- PC Instruction
I have a question on PC instruction for which I have been looking for an answer for quite sometime now. According to "Priciples of operations" manual, execution of an SVC instruction causes a new PSW to be loaded from x'1C0' (SVC FLIH), and program interruption causes a new PSW loaded from x'1D0' (Program Interruption FLIH). Now my question is what happens when a "PC" instruction is executed. Does a new PSW gets loaded from a pre-determined location (like SVC/program interrruption) or it's all handled through some micro code? -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN
