Hello,
current xf86-video-intel git crashex X frequently on my machine (see kernel
log). Any Workarounds/Ideas?
Regards,
Nico
Oct 5 08:58:53 gonzo kernel: WARNING: at drivers/gpu/drm/i915/i915_drv.c:372
gen6_gt_force_wake_put+0x1f/0x45 [i915]()
Oct 5 08:58:53 gonzo kernel: Hardware name:
On Tue, Oct 04, 2011 at 10:13:47PM -0700, Kenneth Graunke wrote:
On 10/04/2011 01:30 AM, Daniel Vetter wrote:
On Mon, Oct 03, 2011 at 11:02:39PM -0700, Kenneth Graunke wrote:
STALL_AT_SCOREBOARD is much clearer than STALL_EN now that there are
several different kinds of stalls. Also,
On Wed, Oct 5, 2011 at 9:38 AM, Jesse Barnes jbar...@virtuousgeek.org wrote:
On Tue, 4 Oct 2011 18:50:18 -0700
Kay, Allen M allen.m@intel.com wrote:
I'm working on assigning Intel graphics to a guest OS in Xen/KVM
environment. Before assigning the device to the guest OS, I need to first
This set of patches lays the groundwork for supporting 3 pipes on IVB
hardware. We've only tested it so far with 2 HDMI plus 1 VGA (a
configuration that doesn't work), and are awaiting 3 DP port hardware
(the officially supported config) to complete our testing.
So this patchset is necessary but
Some more unsafe debugfs access are fixed with this patch. I tested all reads,
but didn't thoroughly test the writes.
Cc: Nicolas Kalkhof nkalk...@web.de
Signed-off-by: Ben Widawsky b...@bwidawsk.net
---
drivers/gpu/drm/i915/i915_debugfs.c | 57 +++
1 files
On Wed, 05 Oct 2011 19:43:53 +0100
Chris Wilson ch...@chris-wilson.co.uk wrote:
On Wed, 5 Oct 2011 10:25:18 -0700, Jesse Barnes jbar...@virtuousgeek.org
wrote:
Add a macro for accessing the two pipe PLLs and add a check to make sure
we don't access a non-existent one in the enable/disable
On Wed, 5 Oct 2011 11:26:26 -0700, Jesse Barnes jbar...@virtuousgeek.org
wrote:
Was just preserving the old code; I think you've fixed this issue
already in another patch (looks like it's another one that's been there
since we first brought up ILK?).
I think the only case where we select the
On Wed, 5 Oct 2011 10:25:21 -0700
Jesse Barnes jbar...@virtuousgeek.org wrote:
Handle PLL allocation and transcoder select bits on CPT+.
Updated patch that fixes the bug with VGA plus two HDMI. Was missing
the composite sync bits in the FDI TX side (setting them everywhere
here just to be
Docs say that the secure batchbuffer field for SNB B0 (products that
actually shipped) should be 0 when not using PPGTT. I'd guess this has
no positive or negative effect, but is just here to jive with the docs.
Cc: Daniel Vetter daniel.vet...@ffwll.ch
Signed-off-by: Ben Widawsky
On Wed, 5 Oct 2011 12:56:47 -0700, Jesse Barnes jbar...@virtuousgeek.org
wrote:
Unfortunately, (2) complicates our mode list output. If you query for
available modes, you'll definitely see some that you can't drive with 3
pipes enabled. I'm not sure if the best way to handle that...
All we
On Wed, 5 Oct 2011 13:01:56 -0700, Ben Widawsky b...@bwidawsk.net wrote:
Docs say that the secure batchbuffer field for SNB B0 (products that
actually shipped) should be 0 when not using PPGTT. I'd guess this has
no positive or negative effect, but is just here to jive with the docs.
How
On Wed, Oct 5, 2011 at 16:56, Jesse Barnes jbar...@virtuousgeek.org wrote:
On Wed, 5 Oct 2011 10:25:17 -0700
Jesse Barnes jbar...@virtuousgeek.org wrote:
This set of patches lays the groundwork for supporting 3 pipes on IVB
hardware. We've only tested it so far with 2 HDMI plus 1 VGA (a
On Wed, 05 Oct 2011 22:26:54 +0100
Chris Wilson ch...@chris-wilson.co.uk wrote:
On Wed, 5 Oct 2011 13:01:56 -0700, Ben Widawsky b...@bwidawsk.net wrote:
Docs say that the secure batchbuffer field for SNB B0 (products that
actually shipped) should be 0 when not using PPGTT. I'd guess this
On Wed, Oct 5, 2011 at 16:48, Jesse Barnes jbar...@virtuousgeek.org wrote:
On Wed, 5 Oct 2011 10:25:21 -0700
Jesse Barnes jbar...@virtuousgeek.org wrote:
Handle PLL allocation and transcoder select bits on CPT+.
Updated patch that fixes the bug with VGA plus two HDMI. Was missing
the
On Mon, Oct 03, 2011 at 11:02:39PM -0700, Kenneth Graunke wrote:
STALL_AT_SCOREBOARD is much clearer than STALL_EN now that there are
several different kinds of stalls. Also, INSTRUCTION_CACHE_FLUSH is a
lot easier to understand at a glance than the terse IS_FLUSH.
Signed-off-by: Kenneth
On Mon, 3 Oct 2011 23:02:40 -0700
Kenneth Graunke kenn...@whitecape.org wrote:
From: Jesse Barnes jbar...@virtuousgeek.org
Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org
Signed-off-by: Kenneth Graunke kenn...@whitecape.org
---
drivers/gpu/drm/i915/i915_reg.h |5 +
On Wed, 5 Oct 2011 15:57:13 -0700, Ben Widawsky b...@bwidawsk.net wrote:
I think we also want a TLB invalidate here, bit 18. This requires another
workaround before issuing this flush: We need 2 Store Data Commands (such as
MI_STORE_DATA_IMM or MI_STORE_DATA_INDEX) before sending PIPE_CONTROL
From: Jesse Barnes jbar...@virtuousgeek.org
Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org
Signed-off-by: Kenneth Graunke kenn...@whitecape.org
Signed-off-by: Ben Widawsky b...@bwidawsk.net
---
drivers/gpu/drm/i915/i915_reg.h |6 ++
drivers/gpu/drm/i915/intel_ringbuffer.c |
On Thu, Oct 06, 2011 at 12:36:03AM +0100, Chris Wilson wrote:
On Wed, 5 Oct 2011 15:57:13 -0700, Ben Widawsky b...@bwidawsk.net wrote:
I think we also want a TLB invalidate here, bit 18. This requires another
workaround before issuing this flush: We need 2 Store Data Commands (such as
On Wed, 5 Oct 2011 15:57:13 -0700, Ben Widawsky b...@bwidawsk.net wrote:
I think we also want a TLB invalidate here, bit 18. This requires another
workaround before issuing this flush: We need 2 Store Data Commands (such as
MI_STORE_DATA_IMM or MI_STORE_DATA_INDEX) before sending PIPE_CONTROL
Hi,
Here's a patch to introduce a DMI-based SSC frequency selection in
intel_bios.c. Instead of always selecting the alternate SSC
frequency as default during initialization, this patch lets some
systems have the non-alternate frequency by default.
Thanks,
Simon
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