At Tue, 15 Nov 2011 13:54:44 -0800,
Kamal Mostafa wrote:
On Tue, 2011-11-15 at 21:28 +0100, Takashi Iwai wrote:
My rough guess is the inconsistency of property taken during the
backlight disabled. How about the patch below (untested!) in addition
to the fix in 3.2?
Takashi
Yes
When the brightness property is inquired while the backlight is disabled,
the driver returns a wrong value (zero) because it probes the value after
the backlight was turned off. This caused a black screen even after the
backlight is enabled again. It should return the internal backlight_level
Dear Fengguang,
Am Mittwoch, den 16.11.2011, 00:57 +0800 schrieb Wu Fengguang:
The Intel HDMI chips (ironlake at least) are found to have ~250ms delay
between the ELD_Valid=1 hotplug event is send and the ELD buffer becomes
actually readable. During the time the ELD buffer is mysteriously all
Hi Keith,
That patch is still not in 3.2-rc2, drm-intel-fixes or drm-intel-next.
I've been using it successfully on i915 (both SSC-blacklisted and not)
and non-i915 machines; feel free to set the Tested-by and Reviewed-by tags.
Thanks,
--
Michel
On 11/09/2011 07:07 PM, Keith Packard wrote:
Keith,
Here are 3 fixes on HDMI/ELD audio.
The third one adds a -hot_remove hook to drm_connector_funcs. Please review.
[PATCH 1/3] drm/i915: fix ELD writing for SandyBridge
[PATCH 2/3] drm/i915: dont trigger hotplug events on unchanged ELD
[PATCH 3/3] drm/i915: hot removal notification to HDMI
The ELD may or may not change when switching the video mode.
If unchanged, don't trigger hot plug events to HDMI audio driver.
This avoids disturbing the user with repeated printks.
Reported-by: Nick Bowler nbow...@elliptictech.com
Signed-off-by: Wu Fengguang fengguang...@intel.com
---
SandyBridge should be using the same register addresses as IvyBridge.
Signed-off-by: Wu Fengguang fengguang...@intel.com
---
drivers/gpu/drm/i915/i915_reg.h |6 +++---
drivers/gpu/drm/i915/intel_display.c | 10 +-
2 files changed, 8 insertions(+), 8 deletions(-)
---
On monitor hot removal:
1) clear SDVO_AUDIO_ENABLE or DP_AUDIO_OUTPUT_ENABLE
2) clear ELD Valid bit
So that the audio driver will receive hot plug events and take action to
refresh its device state and ELD contents.
cc: Wang Zhenyu zhenyu.z.w...@intel.com
Signed-off-by: Wu Fengguang
Sorry forgot to remove this left over chunk...
Note that I've not yet got the hardware to test the DisplayPort part
of this patch, but should be able to do so this week.
--- linux.orig/drivers/gpu/drm/i915/intel_drv.h 2011-11-16
20:54:27.0 +0800
+++
On monitor hot removal:
1) clear SDVO_AUDIO_ENABLE or DP_AUDIO_OUTPUT_ENABLE
2) clear ELD Valid bit
So that the audio driver will receive hot plug events and take action to
refresh its device state and ELD contents.
cc: Wang Zhenyu zhenyu.z.w...@intel.com
Signed-off-by: Wu Fengguang
The drm core currently waits 5 seconds from userspace dropping a request
for vblanks to vblanks actually being disabled. This appears to be a
workaround for broken hardware, but results in a mostly idle desktop
generating a huge number of wakeups that are entirely unnecessary but which
consume
Right now if vblank_offdelay is 0, vblanks won't be disabled after the
last user. Fix that case up.
Signed-off-by: Matthew Garrett m...@redhat.com
---
drivers/gpu/drm/drm_irq.c |3 +--
1 files changed, 1 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/drm_irq.c
Sandybridge, at least, seems to manage without any vblank offdelay.
Dropping this reduces the number of wakeups on an otherwise idle system
dramatically.
Signed-off-by: Matthew Garrett m...@redhat.com
---
drivers/gpu/drm/i915/i915_dma.c |3 +++
1 files changed, 3 insertions(+), 0
On Wed, 2011-11-16 at 09:20 -0500, Matthew Garrett wrote:
The drm core currently waits 5 seconds from userspace dropping a request
for vblanks to vblanks actually being disabled. This appears to be a
workaround for broken hardware, but results in a mostly idle desktop
generating a huge number
Hi all,
I wonder if there is a way to disable or power off the built-in graphics
device that is integrated in chipset if it is not used for most of the
time, for instance, on servers. What I have tried is, experiment on Q45
chipset, set bit 3 and 4 of register 'deven' at offset 54-57h in the PCI
On Mon, Nov 14, 2011 at 21:39, Eugeni Dodonov eugeni.dodo...@intel.com wrote:
Semaphores seem to fix most of the hangs on SNB and IVB, and do not cause
any known regressions as of now.
Let's re-enable them by default to provide a wider testing and coverage.
Acked-by: Keith Packard
On Mon, Nov 14, 2011 at 21:39, Eugeni Dodonov eugeni.dodo...@intel.com wrote:
Most of the rc6-related hangs and major issues were addressed for the past
months.
Let's re-enable it by default to provide a more wider testing, and catch
the remaining problems.
According to tests, enablement of
At Wed, 16 Nov 2011 07:51:28 -0800,
Stephen Warren wrote:
250mS almost sounds like it's setting ELDV in the audio HW,
then going and reading the EDID, then writing the EDID to the audio HW;
perhaps the graphics driver is accidentally setting PRESENT+ELDV when it's
meant to be setting
On Mon, Nov 14, 2011 at 21:22, Jesse Barnes jbar...@virtuousgeek.org wrote:
The video sprites support various video surface formats natively and can
handle scaling as well. So add support for them using the new DRM core
sprite support functions.
v2: use drm specific fourcc header and defines
On Mon, Nov 14, 2011 at 21:22, Jesse Barnes jbar...@virtuousgeek.org wrote:
To save power when the sprite is full screen, we can disable the primary
plane on the same pipe. Track the sprite status and enable/disable the
primary opportunistically.
Signed-off-by: Jesse Barnes
Imo the
On Mon, Nov 14, 2011 at 21:22, Jesse Barnes jbar...@virtuousgeek.org wrote:
Add new ioctls for getting and setting the current destination color
key. This allows for simple overlay display control by matching a color
key value in the primary plane before blending the overlay on top.
At Wed, 16 Nov 2011 08:12:04 -0800,
Stephen Warren wrote:
Takashi Iwai wrote at Wednesday, November 16, 2011 8:58 AM:
At Wed, 16 Nov 2011 07:51:28 -0800, Stephen Warren wrote:
...
[ 424.263258] HDMI hot plug event: Codec=3 Pin=6 Presence_Detect=1
ELD_Valid=0
That line makes
On Wed, 16 Nov 2011 17:05:50 +0100
Daniel Vetter dan...@ffwll.ch wrote:
On Mon, Nov 14, 2011 at 21:22, Jesse Barnes jbar...@virtuousgeek.org wrote:
To save power when the sprite is full screen, we can disable the primary
plane on the same pipe. Track the sprite status and enable/disable the
On Wed, 16 Nov 2011 17:10:53 +0100
Daniel Vetter dan...@ffwll.ch wrote:
On Mon, Nov 14, 2011 at 21:22, Jesse Barnes jbar...@virtuousgeek.org wrote:
Add new ioctls for getting and setting the current destination color
key. This allows for simple overlay display control by matching a color
While refactoring of backlight control code in commit [a95735569:
drm/i915: Refactor panel backlight controls], the handling of the bit
0 of duty-cycle was gone except for pineview. This resulted in invalid
register values for old chips like 915GM. When the bit 0 is set, the
backlight is turned
On Wed, 16 Nov 2011 16:49:40 +0100, Daniel Vetter daniel.vet...@ffwll.ch
wrote:
So we need to check whether DMAR is enabled (on the
entire system, i.e. the variable exported for the ilk workaround is
not good enough)
Can you figure out what *would* be sufficient? Getting semaphores turned
on
On Wed, Nov 16, 2011 at 06:03:15PM +0100, Michel Dänzer wrote:
I thought the main reason for the delay wasn't broken hardware but to
avoid constantly ping-ponging the vblank IRQ between on and off with
apps which regularly neeed the vblank counter value, as that could make
the counter
2011/11/16 Matthew Garrett mj...@srcf.ucam.org:
On Wed, Nov 16, 2011 at 06:03:15PM +0100, Michel Dänzer wrote:
I thought the main reason for the delay wasn't broken hardware but to
avoid constantly ping-ponging the vblank IRQ between on and off with
apps which regularly neeed the vblank
On Wed, Nov 16, 2011 at 07:27:51PM +0100, Mario Kleiner wrote:
It's not broken hardware, but fast ping-ponging it on and off can
make the vblank counter and vblank timestamps unreliable for apps
that need high timing precision, especially for the ones that use
the OML_sync_control extensions
On Wed, Nov 16, 2011 at 15:24, Andrew Lutomirski l...@mit.edu wrote:
AFAICT my snb laptop has always been stable with semaphores and VT-d
enabled. Is this problem possibly restricted to just desktop
machines? I'm happy to test, since my box that can reproduce the hang
instantly is still
On Wed, 16 Nov 2011 17:05:37 -0200
Eugeni Dodonov eug...@dodonov.net wrote:
On Wed, Nov 16, 2011 at 15:24, Andrew Lutomirski l...@mit.edu wrote:
AFAICT my snb laptop has always been stable with semaphores and VT-d
enabled. Is this problem possibly restricted to just desktop
machines?
On Wed, Nov 16, 2011 at 18:16, Keith Packard kei...@keithp.com wrote:
On Wed, 16 Nov 2011 16:49:40 +0100, Daniel Vetter daniel.vet...@ffwll.ch
wrote:
So we need to check whether DMAR is enabled (on the
entire system, i.e. the variable exported for the ilk workaround is
not good enough)
On Wed, Nov 16, 2011 at 16:59, Andrew Lutomirski a...@luto.us wrote:
On Nov 16, 2011 7:54 AM, Daniel Vetter daniel.vet...@ffwll.ch wrote:
On Mon, Nov 14, 2011 at 21:39, Eugeni Dodonov eugeni.dodo...@intel.com
wrote:
Most of the rc6-related hangs and major issues were addressed for the
Not quite. On my i7 2620M (Lenovo T420) the gpu frequently hangs when decoding
videos (vaapi) and running OpenGL apps/games at the same time. Disabling iommu
makes my system relatively stable even with rc6 enabled. I haven't played with
the semaphores however.
-- Nic
-Ursprüngliche
On Wed, Nov 16, 2011 at 21:56, Nicolas Kalkhof nkalk...@web.de wrote:
Not quite. On my i7 2620M (Lenovo T420) the gpu frequently hangs when
decoding videos (vaapi) and running OpenGL apps/games at the same time.
Disabling iommu makes my system relatively stable even with rc6 enabled. I
On Wed, 16 Nov 2011 21:18:13 +0100, Daniel Vetter daniel.vet...@ffwll.ch
wrote:
Last time I've played around with all the combinations, only
intel_iommu=off was good enough to prevent the hang.
intel_iommu=igd_off still hangs (which is what the current value
exported by the dmar code dopends
On Wed, 16 Nov 2011 21:56:37 +0100 (CET), Nicolas Kalkhof nkalk...@web.de
wrote:
Not quite. On my i7 2620M (Lenovo T420) the gpu frequently hangs when
decoding videos (vaapi) and running OpenGL apps/games at the same
time. Disabling iommu makes my system relatively stable even with rc6
On Wed, Nov 16, 2011 at 11:51:28PM +0800, Stephen Warren wrote:
Wu Fengguang wrote at Tuesday, November 15, 2011 7:48 PM:
On Wed, Nov 16, 2011 at 02:25:00AM +0800, Stephen Warren wrote:
Wu Fengguang wrote at Tuesday, November 15, 2011 7:33 AM:
The Intel HDMI chips (ironlake at least) are
In a posting to intel-gfx on Mon Apr 12 10:12:12 PDT 2010, Jesse Barnes
gave several reasons why the Intel Mesa drivers team was not supporting
the Gallium drivers at that time. Here is an excerpt from that email:
Moving to Gallium would be a huge effort for us. We've invested a lot
into
Below is the dmesg representing a video mode set.
ELD writes from the graphics driver
[ 424.254958] [drm:intel_write_eld], ELD on [CONNECTOR:12:HDMI-A-2],
[ENCODER:11:TMDS-11]
[ 424.257670] [drm:ironlake_write_eld], ELD on pipe B
[ 424.259833]
A few months have passed, and we have accumulated a surprising number of
bug fixes. Oops! We would strongly encourage everyone to upgrade.
-Chris
Bugs fixed in this release (compared to 2.16.0)
---
* Video clobbering composite batch state
This allows to enable semaphores by default on devices which support them.
By default, let's enable them on IVB only for now. When DMAR issues on SNB
will be solved, we can enable them on SNB as well.
For IVB, it should fix many hangs and issues.
Bugzilla:
Semaphores cause issues when DMAR is enabled. So if we are set to per-chip
default, and we are on SNB, we can enable semaphores as long as SMAR is
disabled.
Signed-off-by: Eugeni Dodonov eugeni.dodo...@intel.com
---
drivers/gpu/drm/i915/i915_drv.c|2 ++
Most of the rc6-related hangs and major issues were addressed for the past
months.
Let's re-enable it by default to provide a more wider testing, and catch
the remaining problems.
According to tests, enablement of rc6 results in up to +50% improvements
in power usage and battery life, so it
The Ivybridge eDP control register looks like a cross between a
Cougarpoint PCH DP control register and a Sandybridge eDP control
register.
Where things trivially match, share the code. Where there are any
tricky bits, just split things out into two obviously separate code paths.
Signed-off-by:
On Wed, Nov 16, 2011 at 10:17:55PM -0200, Eugeni Dodonov wrote:
Most of the rc6-related hangs and major issues were addressed for the past
months.
Let's re-enable it by default to provide a more wider testing, and catch
the remaining problems.
According to tests, enablement of rc6 results
On Wed, Nov 16, 2011 at 10:17:54PM -0200, Eugeni Dodonov wrote:
Semaphores cause issues when DMAR is enabled. So if we are set to per-chip
default, and we are on SNB, we can enable semaphores as long as SMAR is
disabled.
Signed-off-by: Eugeni Dodonov eugeni.dodo...@intel.com
See my response
On Wed, 16 Nov 2011 15:04:35 +0800, Zhigang Gong zhigang.g...@linux.intel.com
wrote:
This patchset initially enable glamor with UXA. And two functions
,fill_spans and poly_fill_rects, go to the glamor path. I tested it
with render check, and it works fine.
I split your patches slightly
-Original Message-
From: Chris Wilson [mailto:ch...@chris-wilson.co.uk]
Sent: Thursday, November 17, 2011 9:14 AM
To: Zhigang Gong; intel-gfx@lists.freedesktop.org
Cc: zhigang.g...@linux.intel.com
Subject: Re: [PATCH 0/2] Introduce Glamor to UXA framework.
On Wed, 16 Nov 2011
On Wed, Nov 16, 2011 at 6:19 PM, Matthew Garrett mj...@srcf.ucam.org wrote:
On Thu, Nov 17, 2011 at 01:26:37AM +0100, Mario Kleiner wrote:
On Nov 16, 2011, at 7:48 PM, Matthew Garrett wrote:
For Radeon, I'd have thought you could handle this by scheduling
an irq
for the beginning of scanout
On Wed, 16 Nov 2011 22:11:06 -0800
keith.pack...@intel.com wrote:
On Wed, 16 Nov 2011 16:56:16 -0800, Ben Widawsky b...@bwidawsk.net wrote:
The variable you want is: !intel_iommu_gfx_mapped
From what Daniel Vetter said:
Last time I've played around with all the combinations, only
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