On Thu, 25 Sep 2014, clinton.a.tay...@intel.com wrote:
From: Clint Taylor clinton.a.tay...@intel.com
HDMI audio clock config was incorrectly choosing the default for
pixel doubled interlaced modes. The table was missing pixel clock
values 13.500 (27.000) and 13.513 (27.027). Luckily the
Bob Wang zhe1.w...@intel.com writes:
On 09/22/2014 04:11 PM, Mika Kuoppala wrote:
Damien Lespiau damien.lesp...@intel.com writes:
From: Zhe Wang zhe1.w...@intel.com
Enable multi-engine forcewake for Gen9.
v2: Rebase on top of nightly
Move the register range definitions to
On Wed, Sep 24, 2014 at 10:28:07PM +0200, Rafael J. Wysocki wrote:
OK, I guess this is as good as it gets.
What tree would you like it go through?
Since rest of the patches are dependent upon 1st patch which should go thru
your tree, we should merge this thru your tree
Thanks
--
~Vinod
On Wed, Sep 24, 2014 at 03:32:19PM -0500, Felipe Balbi wrote:
OK, I guess this is as good as it gets.
What tree would you like it go through?
Do we really need this new helper ? I mean, the very moment when we
decide to implement -runtime_idle() we will need to get rid of
On Thu, Sep 18, 2014 at 01:52:15PM +0200, Daniel Vetter wrote:
On Thu, Sep 18, 2014 at 07:03:32AM +0100, Chris Wilson wrote:
As we use WC updates of the PTE, we are responsible for notifying the
hardware when to flush its TLBs. Do so after we zap all the PTEs before
suspend (and the BIOS
As we use WC updates of the PTE, we are responsible for notifying the
hardware when to flush its TLBs. Do so after we zap all the PTEs before
suspend (and the BIOS tries to read our GTT).
Fixes a regression from
commit 828c79087cec61eaf4c76bb32c222fbe35ac3930
Author: Ben Widawsky
Bob Wang zhe1.w...@intel.com writes:
On 09/24/2014 02:36 PM, Mika Kuoppala wrote:
Damien Lespiau damien.lesp...@intel.com writes:
From: Zhe Wang zhe1.w...@intel.com
For MMIO registers which are shadowed, force wake is not needed to
write to these registers.
v2: Rebase on top of nightly
As we use WC updates of the PTE, we are responsible for notifying the
hardware when to flush its TLBs. Do so after we zap all the PTEs before
suspend (and the BIOS tries to read our GTT).
Fixes a regression from
commit 828c79087cec61eaf4c76bb32c222fbe35ac3930
Author: Ben Widawsky
From: Tvrtko Ursulin tvrtko.ursu...@intel.com
Write and reads following the block changed use engine specific use counters
and unless that is matched here force wake use counting goes bad. Same
force wake is attempted to be taken twice which leads to at least time outs.
Signed-off-by: Tvrtko
On Thu, Sep 25, 2014 at 11:17:00AM +0100, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin tvrtko.ursu...@intel.com
Write and reads following the block changed use engine specific use counters
and unless that is matched here force wake use counting goes bad. Same
force wake is attempted to be
Damien Lespiau damien.lesp...@intel.com writes:
On Thu, Sep 25, 2014 at 11:17:00AM +0100, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin tvrtko.ursu...@intel.com
Write and reads following the block changed use engine specific use counters
and unless that is matched here force wake use counting
On Mon, Sep 22, 2014 at 06:22:53PM +0200, Jacek Danecki wrote:
Current implementation of reading GPU timestamp is broken.
It returns lower 32 bits shifted by 32 bits ( instead of
).
Below change is adding possibility to read hi part of that register
Rodrigo Vivi rodrigo.v...@intel.com writes:
This WA affect BDW GT3 E and F steppings.
Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com
Reviewed-by: Mika Kuoppala mika.kuopp...@intel.com
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_ringbuffer.c | 6
On 09/25/2014 01:05 PM, Mika Kuoppala wrote:
Damien Lespiau damien.lesp...@intel.com writes:
On Thu, Sep 25, 2014 at 11:17:00AM +0100, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin tvrtko.ursu...@intel.com
Write and reads following the block changed use engine specific use counters
and unless
On Wednesday 24 September 2014 02:31 PM, Daniel Vetter wrote:
On Wed, Sep 24, 2014 at 02:16:49PM +0530, Gaurav K Singh wrote:
Hi,
These set of patches build on top of the existing DSI Video mode support to
enable dual link MIPI panels with high resolutions. These patches have been
tested on a
On Wednesday 24 September 2014 03:02 PM, Jani Nikula wrote:
On Wed, 24 Sep 2014, Gaurav K Singh gaurav.k.si...@intel.com wrote:
Signed-off-by: Gaurav K Singh gaurav.k.si...@intel.com
Signed-off-by: Shobhit Kumar shobhit.ku...@intel.com
---
drivers/gpu/drm/i915/intel_dsi_cmd.c | 35
On 09/25/14 14:26, Chris Wilson wrote:
The problem is that beignet already works around the broken hw read
whereas mesa does not.
There is workaround in mesa already:
static uint64_t
ilo_get_timestamp(struct pipe_screen *screen)
{
struct ilo_screen *is = ilo_screen(screen);
union {
On Thu, Sep 25, 2014 at 03:00:53PM +0200, Jacek Danecki wrote:
On 09/25/14 14:26, Chris Wilson wrote:
If we apply the fix in the kernel we break the
one user of it in beignet but fix all the existing users of mesa.
Are you talking about fix in kernel which will provide 36 bits GPU
On Thu, Sep 25, 2014 at 01:43:31PM +0100, Tvrtko Ursulin wrote:
On 09/25/2014 01:05 PM, Mika Kuoppala wrote:
Damien Lespiau damien.lesp...@intel.com writes:
On Thu, Sep 25, 2014 at 11:17:00AM +0100, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin tvrtko.ursu...@intel.com
Write and reads
On Thu, 25 Sep 2014, Shobhit Kumar shobhit.ku...@linux.intel.com wrote:
On Wednesday 24 September 2014 03:02 PM, Jani Nikula wrote:
On Wed, 24 Sep 2014, Gaurav K Singh gaurav.k.si...@intel.com wrote:
+ do {
Please never use a do-while when a regular for loop will do.
Hmm, ok but reasoning
Volkin, Bradley D bradley.d.vol...@intel.com writes:
On Wed, Sep 24, 2014 at 05:50:30AM -0700, Mika Kuoppala wrote:
In null/golden context there are multiple state commands where
the actual state is always zero. For more compact batch representation
add a macro which just emits command and
On Thursday 25 September 2014 07:09 PM, Jani Nikula wrote:
On Thu, 25 Sep 2014, Shobhit Kumar shobhit.ku...@linux.intel.com wrote:
On Wednesday 24 September 2014 03:02 PM, Jani Nikula wrote:
On Wed, 24 Sep 2014, Gaurav K Singh gaurav.k.si...@intel.com wrote:
+ do {
Please never use a
On Thursday 25 September 2014 05:15:35 Aaron Lu wrote:
Hi Hans,
Thanks for following up and explaining the situation to Pali.
On 09/25/2014 02:21 AM, Pali Rohár wrote:
On Wednesday 24 September 2014 16:34:21 Hans de Goede wrote:
Ok, so the dell-laptop interface is just an obsolete
On Tue, 23 Sep 2014 17:50:29 -0300
Paulo Zanoni przan...@gmail.com wrote:
2014-09-04 8:27 GMT-03:00 Damien Lespiau damien.lesp...@intel.com:
From: Jesse Barnes jbar...@virtuousgeek.org
This moved around on SKL, so we need to make sure we read/write the
correct regs.
Signed-off-by:
On Thu, Sep 25, 2014 at 07:48:34AM -0700, Jesse Barnes wrote:
Damien, did you want to make these changes as part of your re-post or
should I send an updated patch to replace this one?
I wasn't planning to go through this one but let the author works for
his commit :)
--
Damien
From: Daniele Ceraolo Spurio daniele.ceraolospu...@intel.com
These tracepoints are useful for observing the creation and
destruction of Full PPGTTs.
Signed-off-by: Daniele Ceraolo Spurio daniele.ceraolospu...@intel.com
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 4
Looks good
Reviewed-by: Arthur Runyan arthur.j.run...@intel.com
Cc: Arthur Runyan arthur.j.run...@intel.com
Cc: Paulo Zanoni paulo.r.zan...@intel.com
Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com
---
drivers/gpu/drm/i915/intel_ddi.c | 4 ++--
1 file changed, 2 insertions(+), 2
On Thu, Sep 25, 2014 at 01:27:18PM +0530, Vinod Koul wrote:
On Wed, Sep 24, 2014 at 03:32:19PM -0500, Felipe Balbi wrote:
OK, I guess this is as good as it gets.
What tree would you like it go through?
Do we really need this new helper ? I mean, the very moment when we
On Wed, Sep 24, 2014 at 10:28:07PM +0200, Rafael J. Wysocki wrote:
On Wednesday, September 24, 2014 09:44:50 PM Vinod Koul wrote:
This patch series adds a simple macro pm_runtime_last_busy_and_autosuspend()
which invokes pm_runtime_mark_last_busy() and pm_runtime_put_autosuspend()
On Thu, Sep 25, 2014 at 09:22:01AM -0500, Felipe Balbi wrote:
On Thu, Sep 25, 2014 at 01:27:18PM +0530, Vinod Koul wrote:
On Wed, Sep 24, 2014 at 03:32:19PM -0500, Felipe Balbi wrote:
OK, I guess this is as good as it gets.
What tree would you like it go through?
Hi all,
I've a 1440p display with a non-sufficient/corrupt EDID. I'm running
3.17.0-997-lowlatency #201409192205 from
http://kernel.ubuntu.com/~kernel-ppa/mainline/drm-intel-next/ and this
intel driver on Ubuntu 12.04 LTS, on a Thinkpad T420:
Module intel: vendor=X.Org Foundation
[ 9.541]
On Wed, Sep 24, 2014 at 10:46:17PM +0200, Rafael J. Wysocki wrote:
On Wednesday, September 24, 2014 03:15:58 PM Felipe Balbi wrote:
On Wed, Sep 24, 2014 at 10:28:07PM +0200, Rafael J. Wysocki wrote:
On Wednesday, September 24, 2014 09:44:50 PM Vinod Koul wrote:
This patch series adds a
From: Clint Taylor clinton.a.tay...@intel.com
HDMI audio clock config was incorrectly choosing the default for
pixel doubled interlaced modes. The table was missing pixel clock
values 13.500 (27.000) and 13.513 (27.027). Luckily the default N
value for 25.200 is the same N value for both 27MHz
You updated FDI entry 6 here, but Predator r74080 is just DP entry 6. I'll
find out if FDI needs a similar change.
Cc: Arthur Runyan arthur.j.run...@intel.com
Cc: Paulo Zanoni paulo.r.zan...@intel.com
Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com
---
drivers/gpu/drm/i915/intel_ddi.c | 2
BDW display - DP buffer translation values changed to give better margin.
Further change to entry 6; set dword 0 bit 31=1.
Both changes were approved already but this one didn't landed BSpec yet
this is why it is in a separated patch. Making reviewer's life easier.
Also alowing separated tests
That was a fast fix. Looks good now.
Reviewed-by: Arthur Runyan arthur.j.run...@intel.com
v2: Arthur noticed I was changing the wrong bit.
Cc: Arthur Runyan arthur.j.run...@intel.com
Cc: Paulo Zanoni paulo.r.zan...@intel.com
Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com
---
From: Clint Taylor clinton.a.tay...@intel.com
Haswell and later silicon has added a new pixel replication register
to the pipe timings for each transcoder. Now in addition to the
DPLL_A_MD register for the pixel clock double, we also need to write
to the TRANS_MULT_n (0x6002c) register to double
2014-09-24 19:16 GMT-03:00 Rodrigo Vivi rodrigo.v...@intel.com:
Let's make sure PSR is propperly disabled before to re-enabled it.
According to Spec, after disabled PSR CTL, the Idle state might occur
up to 24ms, that is one full frame time (1/refresh rate),
plus SRD exit training time (max
2014-09-24 20:50 GMT-03:00 Rodrigo Vivi rodrigo.v...@intel.com:
The sw cache clean on BDW is a tempoorary workaround because we cannot
set cache clean on blt ring with risk of hungs. So we are doing the cache
clean on sw.
However we are doing much more than needed. Not only when using blt
On Thu, Sep 25, 2014 at 10:36 AM, Paulo Zanoni przan...@gmail.com wrote:
2014-09-24 19:16 GMT-03:00 Rodrigo Vivi rodrigo.v...@intel.com:
Let's make sure PSR is propperly disabled before to re-enabled it.
According to Spec, after disabled PSR CTL, the Idle state might occur
up to 24ms,
This moved around on SKL, so we need to make sure we read/write the
correct regs.
v2: fixup WIN_POS offsets (Paulo)
zero out WIN_POS reg at disable time (Paulo)
Signed-off-by: Jesse Barnes jbar...@virtuougseek.org
Signed-off-by: Damien Lespiau damien.lesp...@intel.com
---
2014-09-25 14:58 GMT-03:00 Jesse Barnes jbar...@virtuousgeek.org:
This moved around on SKL, so we need to make sure we read/write the
correct regs.
v2: fixup WIN_POS offsets (Paulo)
zero out WIN_POS reg at disable time (Paulo)
Reviewed-by: Paulo Zanoni paulo.r.zan...@intel.com
-Original Message-
From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com]
Sent: Tuesday, September 23, 2014 12:31 AM
To: Shah, Suketu J
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH] drm/i915: WaRsClearFWBitsAtReset - WA for
blitter, render and media forcewake
As far as I can tell, the patch series (1-3) looks good. I was wondering how
the copyright header will be handled. Is that to be added manually later on?
Thanks,
Armin
-Original Message-
From: Mika Kuoppala [mailto:mika.kuopp...@linux.intel.com]
Sent: Wednesday, September 24, 2014
On Thursday, September 25, 2014 04:27:58 PM Wolfram Sang wrote:
--Bn2rw/3z4jIqBvZU
Content-Type: text/plain; charset=us-ascii
Content-Disposition: inline
Content-Transfer-Encoding: quoted-printable
On Thu, Sep 25, 2014 at 09:22:01AM -0500, Felipe Balbi wrote:
On Thu, Sep 25, 2014 at
On Thursday, September 25, 2014 11:15:35 AM Aaron Lu wrote:
Hi Hans,
Thanks for following up and explaining the situation to Pali.
On 09/25/2014 02:21 AM, Pali Rohár wrote:
On Wednesday 24 September 2014 16:34:21 Hans de Goede wrote:
Ok, so the dell-laptop interface is just an obsolete
On 09/26/2014 03:58 AM, Rafael J. Wysocki wrote:
On Thursday, September 25, 2014 11:15:35 AM Aaron Lu wrote:
Hi Hans,
Thanks for following up and explaining the situation to Pali.
On 09/25/2014 02:21 AM, Pali Rohár wrote:
On Wednesday 24 September 2014 16:34:21 Hans de Goede wrote:
Ok, so
Some of the Thinkpads' firmware will issue a backlight change request
through i915 operation region unconditionally on AC plug/unplug, the
backlight level used is arbitrary and thus should be ignored. This is
handled by commit 0b9f7d93ca61 (ACPI / i915: ignore firmware requests
for backlight
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