On Wed, 03 Dec 2014, Stephen Rothwell s...@canb.auug.org.au wrote:
Hi Dave,
Today's linux-next merge of the drm tree got a conflict in
drivers/gpu/drm/i915/intel_display.c between commit b68362278af9
(drm/i915: More cautious with pch fifo underruns) from the
drm-intel-fixes tree and commit
Hi Jani,
On Wed, 03 Dec 2014 10:24:12 +0200 Jani Nikula jani.nik...@intel.com wrote:
On Wed, 03 Dec 2014, Stephen Rothwell s...@canb.auug.org.au wrote:
Today's linux-next merge of the drm tree got a conflict in
drivers/gpu/drm/i915/intel_display.c between commit b68362278af9
(drm/i915:
On Tue, Dec 02, 2014 at 10:44:28AM -0800, Rodrigo Vivi wrote:
On Thu, Aug 7, 2014 at 12:49 AM, Zhipeng Gong zhipeng.g...@intel.com wrote:
Signed-off-by: Zhipeng Gong zhipeng.g...@intel.com
---
lib/ioctl_wrappers.c | 16
lib/ioctl_wrappers.h | 1 +
2 files changed, 17
On Tue, Dec 02, 2014 at 11:10:24AM -0800, Michael H. Nguyen wrote:
On 12/02/2014 01:45 AM, Daniel Vetter wrote:
On Mon, Dec 01, 2014 at 02:39:51PM -0800, Michael H. Nguyen wrote:
On 11/26/2014 11:44 PM, Chris Wilson wrote:
On Wed, Nov 26, 2014 at 01:53:34PM -0800,
On Tue, Dec 02, 2014 at 01:57:32PM -0800, Michael H. Nguyen wrote:
On 12/02/2014 03:13 AM, Chris Wilson wrote:
On Mon, Dec 01, 2014 at 02:39:51PM -0800, Michael H. Nguyen wrote:
Re: madvise on creation
Were you referring to this?
from
On Tue, Dec 02, 2014 at 08:54:13AM -0800, John Stultz wrote:
On Tue, Dec 2, 2014 at 8:35 AM, Chris Wilson ch...@chris-wilson.co.uk wrote:
On Tue, Dec 02, 2014 at 04:36:22PM +0100, Daniel Vetter wrote:
+static inline unsigned long nsecs_to_jiffies_timeout(const u64 m)
+{
+ u64 usecs =
On Wed, Dec 03, 2014 at 10:17:32AM +0100, Daniel Vetter wrote:
On Tue, Dec 02, 2014 at 01:57:32PM -0800, Michael H. Nguyen wrote:
On 12/02/2014 03:13 AM, Chris Wilson wrote:
On Mon, Dec 01, 2014 at 02:39:51PM -0800, Michael H. Nguyen wrote:
Re: madvise on creation
Were you
Reviewed-by: Ander Conselvan de Oliveira conselv...@gmail.com
On 12/02/2014 05:45 PM, Matt Roper wrote:
All plane update functions need to unpin the old framebuffer when
flipping to a new one. Pull this logic into a separate function to ease
the integration with atomic plane helpers.
v2:
On 12/02/2014 06:26 PM, Matt Roper wrote:
If we extend the commit_plane handlers for each plane type to be able to
handle fb=0, then we can easily implement plane disable via the
update_plane handler. The cursor plane already works this way, and this
is the direction we need to go to integrate
Daniel Vetter wrote:
On Tue, Dec 02, 2014 at 01:43:59PM +0100, Alexey Orishko wrote:
One more question slightly out off topic:
- could I use i915 driver with other Intel Atom CPUs, such as D2550
and Avoton C2550?
Anything newer than what you have right now likely means gma500 (which is
On Tue, Dec 2, 2014 at 8:35 AM, Chris Wilson ch...@chris-wilson.co.uk wrote:
On Tue, Dec 02, 2014 at 04:36:22PM +0100, Daniel Vetter wrote:
+static inline unsigned long nsecs_to_jiffies_timeout(const u64 m)
+{
+ u64 usecs = div_u64(m + 999, 1000);
+ unsigned long j =
On Wed, 2014-12-03 at 10:22 +0100, Daniel Vetter wrote:
On Tue, Dec 02, 2014 at 08:54:13AM -0800, John Stultz wrote:
On Tue, Dec 2, 2014 at 8:35 AM, Chris Wilson ch...@chris-wilson.co.uk
wrote:
On Tue, Dec 02, 2014 at 04:36:22PM +0100, Daniel Vetter wrote:
+static inline unsigned long
On Tue, 2014-11-25 at 12:30 +0100, Daniel Vetter wrote:
On Tue, Nov 25, 2014 at 02:28:52PM +0530, akash.g...@intel.com wrote:
From: Akash Goel akash.g...@intel.com
A new subtest added to validate the new version of gem_mmap ioctl,
for creating the wc mappings, on yet to be supported
On Wed, Dec 03, 2014 at 09:31:37AM +, Chris Wilson wrote:
On Wed, Dec 03, 2014 at 10:17:32AM +0100, Daniel Vetter wrote:
On Tue, Dec 02, 2014 at 01:57:32PM -0800, Michael H. Nguyen wrote:
On 12/02/2014 03:13 AM, Chris Wilson wrote:
On Mon, Dec 01, 2014 at 02:39:51PM -0800,
On Tue, Dec 02, 2014 at 04:46:38PM +, Chris Wilson wrote:
On Tue, Dec 02, 2014 at 04:19:43PM +0100, Daniel Vetter wrote:
/* Generate a semi-unique error code. The code is not meant to have
meaning, The
@@ -1085,7 +1083,6 @@ static void i915_gem_capture_vm(struct
drm_i915_private
On Tue, Dec 02, 2014 at 05:15:37PM +, Thomas Wood wrote:
diff --git a/lib/igt_core.h b/lib/igt_core.h
index a258348..5c5ee25 100644
--- a/lib/igt_core.h
+++ b/lib/igt_core.h
@@ -512,16 +512,20 @@ bool igt_run_in_simulation(void);
void igt_skip_on_simulation(void);
/* structured
On Wed, Dec 03, 2014 at 07:11:17PM +0800, Zhenyu Wang wrote:
This makes fill function more general to prepare for other
fill method using GPGPU pipeline.
Signed-off-by: Zhenyu Wang zhen...@linux.intel.com
Series lgtm, please push.
-Daniel
---
lib/intel_batchbuffer.c | 4 ++--
On Tue, Dec 02, 2014 at 08:54:13AM -0800, John Stultz wrote:
On Tue, Dec 2, 2014 at 8:35 AM, Chris Wilson ch...@chris-wilson.co.uk wrote:
On Tue, Dec 02, 2014 at 04:36:22PM +0100, Daniel Vetter wrote:
+static inline unsigned long nsecs_to_jiffies_timeout(const u64 m)
+{
+ u64 usecs =
Hi,
while checking the reported bug about VT switch hang on openSUSE 13.2,
I also could reproduce a similar issue as reported: namely, X hangs
when repeatedly switching VT quickly.
For example, running the following on KDE results in the stall of X.
% for i in $(seq 1 100); do chvt 1;
Install the exit handler to reset connector states whenever
kmstest_force_connector is called, so that the connector states are
always reset even if a test fails.
Signed-off-by: Thomas Wood thomas.w...@intel.com
---
lib/igt_kms.c | 14 +++---
1 file changed, 7 insertions(+), 7
When playing around with debugfs and a HSW machine I noticed that we
were displaying some garbled value in i915_ddb_info. This debugfs file
is only meaningful for gen9+, so don't display anything on earlier
platforms.
Signed-off-by: Damien Lespiau damien.lesp...@intel.com
---
On Wed, Dec 03, 2014 at 02:13:58PM +, Damien Lespiau wrote:
+/* To be used in a similar way to mmap_gtt */
+drm_public int
+drm_intel_gem_bo_map_wc(drm_intel_bo *bo) {
+ drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo-bufmgr;
+ drm_intel_bo_gem *bo_gem =
On Tue, Oct 28, 2014 at 06:39:27PM +0530, akash.g...@intel.com wrote:
@@ -1126,6 +1136,8 @@ static void
drm_intel_gem_bo_purge_vma_cache(drm_intel_bufmgr_gem *bufmgr_gem)
/* We may need to evict a few entries in order to create new mmaps */
limit = bufmgr_gem-vma_max -
On Wed, Dec 03, 2014 at 03:45:35PM +0100, Takashi Iwai wrote:
Hi,
while checking the reported bug about VT switch hang on openSUSE 13.2,
I also could reproduce a similar issue as reported: namely, X hangs
when repeatedly switching VT quickly.
For example, running the following on KDE
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV 364/364
On Wed, Dec 3, 2014 at 6:30 AM, Daniel Vetter dan...@ffwll.ch wrote:
On Tue, Dec 02, 2014 at 08:54:13AM -0800, John Stultz wrote:
On Tue, Dec 2, 2014 at 8:35 AM, Chris Wilson ch...@chris-wilson.co.uk
wrote:
On Tue, Dec 02, 2014 at 04:36:22PM +0100, Daniel Vetter wrote:
+static inline
From: Tvrtko Ursulin tvrtko.ursu...@intel.com
A short section describing background, implementation and intended usage.
For: VIZ-4544
Signed-off-by: Tvrtko Ursulin tvrtko.ursu...@intel.com
---
Documentation/DocBook/drm.tmpl | 5 +++
drivers/gpu/drm/i915/i915_gem_gtt.c | 61
From: Tvrtko Ursulin tvrtko.ursu...@intel.com
This series continues what was previously a single patch called drm/i915:
Infrastructure for supporting different GGTT views per object.
To start with we break the assumption GGTT VMA is at the head of the list to
smoke out any potential hidden
From: Tvrtko Ursulin tvrtko.ursu...@intel.com
Multiple GGTT VMAs per object will be introduced in the near future which will
make it impossible to guarantee normal GGTT view is at the head of the list.
Purpose of this patch is to break this assumption straight away so any
potential hidden
From: Tvrtko Ursulin tvrtko.ursu...@intel.com
Things like reliable GGTT mappings and mirrored 2d-on-3d display will need
to map objects into the same address space multiple times.
Added a GGTT view concept and linked it with the VMA to distinguish between
multiple instances per address space.
At Wed, 3 Dec 2014 18:31:45 +,
Chris Wilson wrote:
On Wed, Dec 03, 2014 at 03:45:35PM +0100, Takashi Iwai wrote:
Hi,
while checking the reported bug about VT switch hang on openSUSE 13.2,
I also could reproduce a similar issue as reported: namely, X hangs
when repeatedly
This simplifies the sync code quite a bit. I don't think we'll be able
to get away with using the core fence code's seqno support, since we'll
be moving away from simple seqno comparisions with the scheduler and
preemption, but the additional code is pretty minimal anyway, and lets
us add
Expose an ioctl to create Android fences based on the Android sync point
infrastructure (which in turn is based on DMA-buf fences). Just a
sketch at this point, no testing has been done.
There are a couple of goals here:
1) allow applications and libraries to create fences without an
Still have a few remaining todo items, but I'd like some feedback on these
before adding a bunch of stuff on top.
Rough todo list:
- support for other rings
- support for display
- tests
- userspace usage (I have a Mesa patch that needs a refresh, but it's
trivial, the interesting bit
From: Clint Taylor clinton.a.tay...@intel.com
Added PIPE C register support for CHV audio programming.
Signed-off-by: Clint Taylor clinton.a.tay...@intel.com
---
drivers/gpu/drm/i915/i915_reg.h | 18 --
1 file changed, 12 insertions(+), 6 deletions(-)
diff --git
From: Maarten Lankhorst maarten.lankho...@canonical.com
This allows users of dma fences to create a android fence.
Cc: Daniel Vetter dan...@ffwll.ch
Cc: Jesse Barnes jbar...@virtuousgeek.org
Signed-off-by: Maarten Lankhorst maarten.lankho...@canonical.com
---
drivers/staging/android/sync.c | 13
Let's be optimistic that for future platforms this will remain the same
and reorg a bit.
This reorg in if blocks instead of switch make life easier for future
platform support addition.
Cc: Damien Lespiau damien.lesp...@intel.com
Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com
---
Let's be optimistic that for future platforms this will remain the same
and reorg a bit.
This reorg in if blocks instead of switch make life easier for future
platform support addition.
Cc: Damien Lespiau damien.lesp...@intel.com
Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com
---
This entire series has no functional change on current supported platforms and
it isn't based on any spec.
This is just a reorg that will help on future.
It is true that removing BUG() for unsupported platforms we miss the warn when
enabling new platforms.
But most of the time we just do what
Let's be optimistic that for future platforms memory management doesn't change
that much and reuse gen8 function for PPGTT init.
Cc: Damien Lespiau damien.lesp...@intel.com
Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 4 +---
1 file changed, 1
Let's be optimistic that for future platforms this will remain the same
and reorg a bit.
This reorg in if blocks instead of switch make life easier for future
platform support addition.
Cc: Damien Lespiau damien.lesp...@intel.com
Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com
---
Let's be optimistic that for future platforms this will remain the same
and reorg a bit.
This reorg in if blocks instead of switch make life easier for future
platform support addition.
Cc: Damien Lespiau damien.lesp...@intel.com
Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com
---
These w/a were recently identified while debugging another issue,
+WaClearFlowControlGpgpuContextSave:chv
+Wa4x4STCOptimizationDisable:chv
For: VIZ-4090
Change-Id: I08d2176dec609396c3a7c2e48b2413e233799fc4
Signed-off-by: Arun Siluvery arun.siluv...@linux.intel.com
---
On Wed, Dec 03, 2014 at 10:10:30AM -0800, clinton.a.tay...@intel.com wrote:
From: Clint Taylor clinton.a.tay...@intel.com
Added PIPE C register support for CHV audio programming.
nak. The offset between the pipes looks constant so it should work
just fine with _PIPE().
Signed-off-by:
On 03-12-14 20:49, Jesse Barnes wrote:
Expose an ioctl to create Android fences based on the Android sync point
infrastructure (which in turn is based on DMA-buf fences). Just a
sketch at this point, no testing has been done.
There are a couple of goals here:
1) allow applications and
On 12/03/2014 01:01 PM, Ville Syrjälä wrote:
On Wed, Dec 03, 2014 at 10:10:30AM -0800, clinton.a.tay...@intel.com wrote:
From: Clint Taylor clinton.a.tay...@intel.com
Added PIPE C register support for CHV audio programming.
nak. The offset between the pipes looks constant so it should work
On Wed, Dec 03, 2014 at 05:33:24PM +, Damien Lespiau wrote:
When playing around with debugfs and a HSW machine I noticed that we
were displaying some garbled value in i915_ddb_info. This debugfs file
is only meaningful for gen9+, so don't display anything on earlier
platforms.
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV 364/364
Hi all,
We are pleased to announce the first release of KVMGT project. KVMGT is the
implementation of Intel GVT-g technology, a full GPU virtualization solution.
Under Intel GVT-g, a virtual GPU instance is maintained for each VM, with part
of performance critical resources directly
Hi all,
We're pleased to announce a public release to Intel Graphics Virtualization
Technology (Intel GVT-g, formerly known as XenGT). Intel GVT-g is a complete
vGPU solution with mediated pass-through, supported today on 4th generation
Intel Core(TM) processors with Intel Graphics
On 2014.12.03 15:26:13 +0100, Daniel Vetter wrote:
On Wed, Dec 03, 2014 at 07:11:17PM +0800, Zhenyu Wang wrote:
This makes fill function more general to prepare for other
fill method using GPGPU pipeline.
Signed-off-by: Zhenyu Wang zhen...@linux.intel.com
Series lgtm, please push.
From: Akash Goel akash.g...@intel.com
A new subtest added to validate the new version of gem_mmap ioctl,
for creating the wc mappings, on yet to be supported flags.
Older kernel is also checked against the flags field, which should
be treated as a don't care by it.
v2: Removed the flags checking
Instead of pipe configuration reg, cck reg to be used for checking whether
DSI Pll is getting locked or not.
Signed-off-by: Gaurav K Singh gaurav.k.si...@intel.com
Signed-off-by: Shobhit Kumar shobhit.ku...@intel.com
---
drivers/gpu/drm/i915/intel_dsi_pll.c |5 +++--
1 file changed, 3
We need to program both port registers during dual link enable path.
v2: Address review comments by Jani
- Used a for loop instead of do-while loop.
v3: Used for_each_dsi_port macro instead of for loop
Signed-off-by: Gaurav K Singh gaurav.k.si...@intel.com
Signed-off-by: Shobhit Kumar
For dual link MIPI Panels, each port needs half of pixel clock. Pixel overlap
can be enabled if needed by panel, then in that case, pixel clock will be
increased for extra pixels.
v2 : Address review comments by Jani
- Removed the bit mask used for -dual_link
- Used DSI instead of MIPI
This patch is in preparation for the DSI dual link
port enable and disable related changes.
Signed-off-by: Gaurav K Singh gaurav.k.si...@intel.com
Signed-off-by: Shobhit Kumar shobhit.ku...@intel.com
---
drivers/gpu/drm/i915/intel_dsi.c | 43 --
1 file
For Dual Link MIPI Panels, both Port A and Port C should be enabled
during the MIPI encoder enabling sequence. Similarly, during the
disabling sequence, both ports needs to be disabled.
v2: Used for_each_dsi_port macro instead of for loop
v3: Used intel_dsi-ports instead of dual_link var for
For dual link MIPI panels, SHUTDOWN packet needs to send to both Ports
A C during MIPI encoder disabling sequence. Similarly, TURN ON packet
to be sent to both Ports during MIPI encoder enabling sequence.
v2: Address review comments by Jani
- Used a for loop instead of do-while loop.
v3:
Hi,
These set of patches build on top of the existing DSI Video mode support to
enable dual link MIPI panels with high resolutions. These patches have been
tested on a 25x16 panel and works well.
v2: Commit message added to all patches. All review comments of Jani, Nikula
have been addressed in
hactive, hfp, hbp, hsync needs to be halved for dual link MIPI Panels.
Accordingly timing related mmio regs needs to be programmed for both MIPI Ports.
v2: Address review comments by Jani
- Used a for loop instead of do-while loop
v3: Used for_each_dsi_port macro instead of for loop
This patch is in preparation of DSI dual link panels. For dual link
panels, few packets needs to be sent to Port A or Port C or both. Based
on the portno from MIPI Sequence Block#53, these sequences needs to be
sent accordingly.
v2: Addressed review comments by Jani
- port variables named
For Dual link MIPI Panels, dsipll clock for both DSI0 and DSI1 needs to be
enabled.
v2: Address review comments by Jani
- Added wait time for PLL to be locked.
v3: separate patch created for cck read for checking PLL to be locked
Signed-off-by: Gaurav K Singh gaurav.k.si...@intel.com
We need to program both port registers during dual link disable path.
v2: Address review comments by Jani
- Used a for loop instead of do-while loop.
v3: Used for_each_dsi_port macro instead of for loop
Signed-off-by: Gaurav K Singh gaurav.k.si...@intel.com
Signed-off-by: Shobhit Kumar
On 12/1/2014 7:17 PM, Jani Nikula wrote:
On Sat, 29 Nov 2014, Gaurav K Singh gaurav.k.si...@intel.com wrote:
Hi,
These set of patches build on top of the existing DSI Video mode support to
enable dual link MIPI panels with high resolutions. These patches have been
tested on a 25x16 panel and
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV 364/364
On Wed, 03 Dec 2014, Rodrigo Vivi rodrigo.v...@intel.com wrote:
Let's be optimistic that for future platforms this will remain the same
and reorg a bit.
This reorg in if blocks instead of switch make life easier for future
platform support addition.
Cc: Damien Lespiau
66 matches
Mail list logo
