From: Ville Syrjälä ville.syrj...@linux.intel.com
Ignore the current state of the pipe and just check crtc_state-enable
and the number of FDI lanes required. This means we don't accidentally
mistake the FDI lanes as being available of one of the pipes just
happens to be disabled at the time of
From: Ville Syrjälä ville.syrj...@linux.intel.com
So these on top of Ander's latest FDI bifurcation patch [1] should hopefully
result in something sane. Didn't test them though, but assuming Ander
has that test somewhere maybe some of the problematic cases I identified [2]
could be checked with
On Wed, Mar 11, 2015 at 11:37:54AM +, Conselvan De Oliveira, Ander wrote:
On Wed, 2015-03-11 at 13:35 +0200, Ander Conselvan de Oliveira wrote:
Remove the global modeset resource function that would disable the
bifurcation bit, and instead enable/disable it when enabling the pch
On 3/9/2015 10:57 AM, Jani Nikula wrote:
On Thu, 19 Feb 2015, Todd Previte tprev...@gmail.com wrote:
This patch is the amalgamation of 7 patches from the V2 series. These
patches all involve the implementation of the debugfs mechanism for
handling Displayport compliance testing. The following
On Tue, Feb 03, 2015 at 01:36:00PM +, Damien Lespiau wrote:
On Tue, Feb 03, 2015 at 02:34:05PM +0200, Jani Nikula wrote:
Spell all the PCI IDs out to be able to quickly grep for the IDs. No
functional changes.
Signed-off-by: Jani Nikula jani.nik...@intel.com
---
I tested
From: Ville Syrjälä ville.syrj...@linux.intel.com
The logic in the FDI lane checks is very hard for my poor brain to
grasp. Rewrite it in a more straightforward way.
Cc: Ander Conselvan de Oliveira ander.conselvan.de.olive...@intel.com
Cc: Daniel Vetter dan...@ffwll.ch
Signed-off-by: Ville
This provides a nice boost to mesa in swap bound scenarios (as mesa
throttles itself to the previous frame and given the scenario that will
complete shortly). It will also provide a good boost to systems running
with semaphores disabled and so frequently waiting on the GPU as it
switches rings. In
On Tue, Mar 10, 2015 at 12:32:43PM +, Tvrtko Ursulin wrote:
On 03/10/2015 12:19 PM, Chris Wilson wrote:
On Tue, Mar 10, 2015 at 12:02:28PM +, Tvrtko Ursulin wrote:
@@ -13707,13 +13709,18 @@ void intel_modeset_gem_init(struct drm_device
*dev)
On Wed, Mar 11, 2015 at 02:19:38PM +0200, Ville Syrjälä wrote:
On Wed, Mar 11, 2015 at 11:24:34AM +0100, Daniel Vetter wrote:
On Wed, Mar 11, 2015 at 12:05:39PM +0200, Ville Syrjälä wrote:
On Wed, Mar 11, 2015 at 10:52:29AM +0100, Daniel Vetter wrote:
On Tue, Mar 10, 2015 at 07:57:13PM
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 5926
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV -3 281/281
On 03/11/2015 09:14 AM, Daniel Vetter wrote:
On Wed, Mar 11, 2015 at 02:53:39PM +, John Harrison wrote:
On 05/03/2015 14:49, Daniel Vetter wrote:
On Thu, Mar 05, 2015 at 01:57:31PM +, john.c.harri...@intel.com wrote:
From: John Harrison john.c.harri...@intel.com
The LRC submission
On Wed, Mar 11, 2015 at 10:30:13AM +, Chris Wilson wrote:
On Wed, Mar 11, 2015 at 11:13:59AM +0100, Daniel Vetter wrote:
Also do you have microbenchmark numbers for something midly ridiculous
like a loop of very short batches (enough ofc to cause a bit of delay) and
immediately stalling
On Wed, Mar 11, 2015 at 02:53:39PM +, John Harrison wrote:
On 05/03/2015 14:49, Daniel Vetter wrote:
On Thu, Mar 05, 2015 at 01:57:31PM +, john.c.harri...@intel.com wrote:
From: John Harrison john.c.harri...@intel.com
The LRC submission code requires a request for tracking purposes.
On Fri, Mar 06, 2015 at 11:07:21AM +0530, akash.g...@intel.com wrote:
From: Akash Goel akash.g...@intel.com
Added support for SKL in the i915_frequency_info debugfs function
v2:
- corrected the handling of reqf (Damien)
- Reorderd the platform check for cagf (Ville)
Signed-off-by:
On 03/05/2015 09:37 PM, akash.g...@intel.com wrote:
From: Akash Goel akash.g...@intel.com
Enable the RPS interrupts programming(enable/disable/reset) for GEN9,
as missing changes to enable the RPS support on GEN9 have been added.
Signed-off-by: Akash Goel akash.g...@intel.com
---
On Wed, Mar 11, 2015 at 06:58:12PM +0200, Ville Syrjälä wrote:
On Wed, Mar 11, 2015 at 11:37:54AM +, Conselvan De Oliveira, Ander wrote:
On Wed, 2015-03-11 at 13:35 +0200, Ander Conselvan de Oliveira wrote:
Remove the global modeset resource function that would disable the
bifurcation
On Wed, Mar 11, 2015 at 12:27:59PM -0700, Jesse Barnes wrote:
On 03/05/2015 09:37 PM, akash.g...@intel.com wrote:
From: Akash Goel akash.g...@intel.com
On SKL, GT frequency is programmed in units of 16.66 MHZ units compared
to 50 MHZ for older platforms. Also the time value specified for
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 5933
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV -3 281/281
On 11/03/2015 16:44, Jesse Barnes wrote:
On 03/11/2015 09:14 AM, Daniel Vetter wrote:
On Wed, Mar 11, 2015 at 02:53:39PM +, John Harrison wrote:
On 05/03/2015 14:49, Daniel Vetter wrote:
On Thu, Mar 05, 2015 at 01:57:31PM +, john.c.harri...@intel.com wrote:
From: John Harrison
From: Ville Syrjälä ville.syrj...@linux.intel.com
We accidentally pass 'pipe' instead of 'port' to CHV_PLL_DW8() and
with PIPE_C we end up at register offset 0x8320 which isn't the
0x8020 we wanted. Fix it.
The problem was fortunately caught by the sanity check in vlv_dpio_read():
WARNING: CPU:
On Wed, Mar 11, 2015 at 03:29:19PM +, Chris Wilson wrote:
+ while (!need_resched()) {
+ if (i915_gem_request_completed(req, true)) {
+ ret = 0;
+ goto out;
+ }
+
+ if (timeout time_after_eq(jiffies,
On 03/09/2015 02:04 PM, Ville Syrjälä wrote:
On Mon, Mar 09, 2015 at 12:07:31PM -0700, Jesse Barnes wrote:
On 03/09/2015 10:29 AM, Daniel Vetter wrote:
On Mon, Mar 09, 2015 at 08:34:49AM -0700, Jesse Barnes wrote:
On 03/06/2015 08:34 AM, Daniel Vetter wrote:
On Thu, Mar 05, 2015 at 11:22:19AM
On Fri, Mar 06, 2015 at 11:07:14AM +0530, akash.g...@intel.com wrote:
From: Akash Goel akash.g...@intel.com
For SKL, register definition for RPNSWREQ (A008), RPSTAT1(A01C)
have changed slightly. Also on SKL, frequency is specified in
units of 16.66 MHZ, compared to 50 MHZ for most of the
On Fri, Mar 06, 2015 at 11:07:16AM +0530, akash.g...@intel.com wrote:
From: Akash Goel akash.g...@intel.com
On SKL the frequency is specified in units of 16.66 MHZ, barring the
RP_STATE_CAP(0x5998) register, which still reports frequency in units
of 50 MHZ. So an extra conversion is required
On 03/05/2015 09:37 PM, akash.g...@intel.com wrote:
From: Akash Goel akash.g...@intel.com
Earlier Turbo interrupts were not being processed for SKL,
as something was amiss in turbo programming for SKL.
Now missing changes have been added, so enabling the Turbo
interrupt processing for SKL.
On 03/05/2015 09:37 PM, akash.g...@intel.com wrote:
From: Akash Goel akash.g...@intel.com
On SKL, GT frequency is programmed in units of 16.66 MHZ units compared
to 50 MHZ for older platforms. Also the time value specified for Up/Down EI
Up/Down thresholds are expressed in units of 1.33 us,
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 5931
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV -7 281/281
On Wed, Mar 11, 2015 at 11:37:23AM -0700, Jesse Barnes wrote:
On 03/09/2015 02:04 PM, Ville Syrjälä wrote:
On Mon, Mar 09, 2015 at 12:07:31PM -0700, Jesse Barnes wrote:
On 03/09/2015 10:29 AM, Daniel Vetter wrote:
On Mon, Mar 09, 2015 at 08:34:49AM -0700, Jesse Barnes wrote:
On 03/06/2015
On Wed, Mar 11, 2015 at 09:10:29PM +0200, Ville Syrjälä wrote:
On Wed, Mar 11, 2015 at 11:37:23AM -0700, Jesse Barnes wrote:
On 03/09/2015 02:04 PM, Ville Syrjälä wrote:
On Mon, Mar 09, 2015 at 12:07:31PM -0700, Jesse Barnes wrote:
On 03/09/2015 10:29 AM, Daniel Vetter wrote:
On Mon,
On Tue, Mar 10, 2015 at 01:06:44PM -0700, Jeff McGee wrote:
On Tue, Mar 10, 2015 at 07:47:03PM +0100, Daniel Vetter wrote:
On Tue, Mar 10, 2015 at 01:58:52PM -0400, Rob Clark wrote:
On Tue, Mar 10, 2015 at 12:59 PM, Jeff McGee jeff.mc...@intel.com wrote:
On Tue, Mar 10, 2015 at
Without this Dave's 32bit rhel compiler is annoyed. Don't ask me about
the exact rules for this stuff though, but this should be safe.
Reported-by: Dave Airlie airl...@gmail.com
Signed-off-by: Daniel Vetter daniel.vet...@intel.com
---
drivers/gpu/drm/i915/i915_vgpu.h | 2 +-
1 file changed, 1
I have no idea about the exact rules, but this angered Dave's 32bit
rhel gcc.
Reported-by: Dave Airlie airl...@gmail.com
Signed-off-by: Daniel Vetter daniel.vet...@intel.com
---
include/uapi/drm/drm_fourcc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
On 2015.03.06 09:44:07 +, Chris Wilson wrote:
Userspace can pass in an offset that it presumes the object is located
at. The kernel will then do its utmost to fit the object into that
location. The assumption is that userspace is handling its own object
locations (for example along with
+
+#define fourcc_mod_code(vendor, val) \
+ u64)DRM_FORMAT_MOD_VENDOR_## vendor) 56) | (val
0x00ffL))
eh, yeah no,
/home/airlied/kernel/drm-2.6/drivers/gpu/drm/i915/intel_pm.c: In
function ‘skl_wm_method2’:
+/*
+ * The following structure pages are defined in GEN MMIO space
+ * for virtualization. (One page for now)
+ */
+#define VGT_MAGIC 0x4776544776544776 /* 'vGTvGTvG' */
one of my dusty 32-bit compilers dislikes this,
CC [M] drivers/gpu/drm/i915/i915_vgpu.o
On Wed, Mar 11, 2015 at 11:00:32AM +0100, Daniel Vetter wrote:
On Tue, Mar 10, 2015 at 01:15:29PM +0200, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
When the sprite is covering the entire pipe (and color keying is not
enabled) we currently try
On Tue, Mar 10, 2015 at 04:14:14PM +, Chris Wilson wrote:
On Tue, Mar 10, 2015 at 04:06:19PM +, Chris Wilson wrote:
@@ -1235,12 +1257,20 @@ int __i915_wait_request(struct drm_i915_gem_request
*req,
if (ring-id == RCS INTEL_INFO(dev)-gen = 6)
On Wed, Mar 11, 2015 at 12:05:39PM +0200, Ville Syrjälä wrote:
On Wed, Mar 11, 2015 at 10:52:29AM +0100, Daniel Vetter wrote:
On Tue, Mar 10, 2015 at 07:57:13PM +0200, Ville Syrjälä wrote:
On Tue, Mar 10, 2015 at 10:01:51AM -0700, Matt Roper wrote:
On Tue, Mar 10, 2015 at 01:15:24PM
Remove the global modeset resource function that would disable the
bifurcation bit, and instead enable/disable it when enabling the pch
transcoder. The mode set consistency check should prevent us from
disabling the bit if pipe C is enabled so the change should be safe.
Note that this doens't
On Wed, 2015-03-11 at 13:35 +0200, Ander Conselvan de Oliveira wrote:
Remove the global modeset resource function that would disable the
bifurcation bit, and instead enable/disable it when enabling the pch
transcoder. The mode set consistency check should prevent us from
disabling the bit if
The tests exercise different combinations of enabling pipe B with modes
that require more than 2 lanes and then enabling pipe C.
v2: Added a couple more tests for different pipe transitions. (Ander)
Use custom modes to make the test reliable. (Daniel)
---
tests/Makefile.sources| 1 +
So that it is possible to use a custom mode with the simplified mode set API.
---
lib/igt_kms.c | 9 +
lib/igt_kms.h | 4
2 files changed, 13 insertions(+)
diff --git a/lib/igt_kms.c b/lib/igt_kms.c
index 26e4913..0dccd2d 100644
--- a/lib/igt_kms.c
+++ b/lib/igt_kms.c
@@ -895,6
On Wed, Mar 11, 2015 at 10:39:31AM +0530, sonika wrote:
On Tuesday 10 March 2015 04:45 PM, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
In preparation to movable/resizable primary planes pass the clipped
plane size to .update_primary_plane().
On Tue, Mar 10, 2015 at 07:48:39PM +0200, Ville Syrjälä wrote:
On Tue, Mar 10, 2015 at 10:01:47AM -0700, Matt Roper wrote:
On Tue, Mar 10, 2015 at 01:15:23PM +0200, ville.syrj...@linux.intel.com
wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
plane-fb is not as reliable as
On Wed, Mar 11, 2015 at 11:13:59AM +0100, Daniel Vetter wrote:
On Tue, Mar 10, 2015 at 04:14:14PM +, Chris Wilson wrote:
On Tue, Mar 10, 2015 at 04:06:19PM +, Chris Wilson wrote:
@@ -1235,12 +1257,20 @@ int __i915_wait_request(struct
drm_i915_gem_request *req,
if (ring-id ==
On Wednesday 11 March 2015 02:57 PM, Ville Syrjälä wrote:
On Wed, Mar 11, 2015 at 10:39:31AM +0530, sonika wrote:
On Tuesday 10 March 2015 04:45 PM, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
In preparation to movable/resizable primary planes pass
On Tue, Mar 10, 2015 at 01:57:09PM -0700, Matt Roper wrote:
On Tue, Mar 10, 2015 at 07:59:15PM +0200, Ville Syrjälä wrote:
On Tue, Mar 10, 2015 at 10:10:40AM -0700, Matt Roper wrote:
On Tue, Mar 10, 2015 at 01:15:25PM +0200, ville.syrj...@linux.intel.com
wrote:
From: Ville Syrjälä
On Tue, Mar 10, 2015 at 07:59:15PM +0200, Ville Syrjälä wrote:
On Tue, Mar 10, 2015 at 10:10:40AM -0700, Matt Roper wrote:
On Tue, Mar 10, 2015 at 01:15:25PM +0200, ville.syrj...@linux.intel.com
wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
In preparation to
On Wed, Mar 11, 2015 at 12:09:24PM +0200, Ville Syrjälä wrote:
On Wed, Mar 11, 2015 at 11:00:32AM +0100, Daniel Vetter wrote:
On Tue, Mar 10, 2015 at 01:15:29PM +0200, ville.syrj...@linux.intel.com
wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
When the sprite is covering
On Tue, Mar 10, 2015 at 07:57:13PM +0200, Ville Syrjälä wrote:
On Tue, Mar 10, 2015 at 10:01:51AM -0700, Matt Roper wrote:
On Tue, Mar 10, 2015 at 01:15:24PM +0200, ville.syrj...@linux.intel.com
wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
-static void
On Tue, Mar 10, 2015 at 02:50:16PM -0700, Jesse Barnes wrote:
On 03/10/2015 08:02 AM, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
Use the FW_WM() macro from the VLV wm code to polish up the wm
code for older gmch platforms.
Cc: Daniel
On Wed, Mar 11, 2015 at 01:35:43PM +0200, Ander Conselvan de Oliveira wrote:
Remove the global modeset resource function that would disable the
bifurcation bit, and instead enable/disable it when enabling the pch
transcoder. The mode set consistency check should prevent us from
disabling the
On Wed, 2015-03-11 at 15:10 +0200, Ville Syrjälä wrote:
On Wed, Mar 11, 2015 at 01:35:43PM +0200, Ander Conselvan de Oliveira wrote:
Remove the global modeset resource function that would disable the
bifurcation bit, and instead enable/disable it when enabling the pch
transcoder. The mode
On Wed, Mar 11, 2015 at 01:33:00PM +0200, Ander Conselvan de Oliveira wrote:
So that it is possible to use a custom mode with the simplified mode set API.
Maybe just igt_output_set_mode()?
--
Damien
---
lib/igt_kms.c | 9 +
lib/igt_kms.h | 4
2 files changed, 13
On Wed, Mar 11, 2015 at 11:24:34AM +0100, Daniel Vetter wrote:
On Wed, Mar 11, 2015 at 12:05:39PM +0200, Ville Syrjälä wrote:
On Wed, Mar 11, 2015 at 10:52:29AM +0100, Daniel Vetter wrote:
On Tue, Mar 10, 2015 at 07:57:13PM +0200, Ville Syrjälä wrote:
On Tue, Mar 10, 2015 at 10:01:51AM
On Wed, Mar 11, 2015 at 01:35:43PM +0200, Ander Conselvan de Oliveira wrote:
Remove the global modeset resource function that would disable the
bifurcation bit, and instead enable/disable it when enabling the pch
transcoder. The mode set consistency check should prevent us from
disabling the
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 5934
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV -9 281/281
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 5936
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV -15
On 3/11/2015 1:52 PM, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
We accidentally pass 'pipe' instead of 'port' to CHV_PLL_DW8() and
with PIPE_C we end up at register offset 0x8320 which isn't the
0x8020 we wanted. Fix it.
The problem was fortunately
On Wednesday 11 March 2015 07:36 PM, Chris Wilson wrote:
On Wed, Mar 11, 2015 at 07:23:48PM +0530, Deepak S wrote:
On Thursday 26 February 2015 09:42 PM, Chris Wilson wrote:
On Thu, Feb 26, 2015 at 08:46:56PM +0530, deepa...@linux.intel.com wrote:
From: Deepak S deepa...@linux.intel.com
On 05/03/2015 14:49, Daniel Vetter wrote:
On Thu, Mar 05, 2015 at 01:57:31PM +, john.c.harri...@intel.com wrote:
From: John Harrison john.c.harri...@intel.com
The LRC submission code requires a request for tracking purposes. It does not
actually require that request to 'complete' it simply
On Thursday 26 February 2015 09:12 PM, Deepak S wrote:
On Thursday 26 February 2015 09:13 PM, Ville Syrjälä wrote:
On Thu, Feb 26, 2015 at 08:46:54PM +0530, deepa...@linux.intel.com
wrote:
From: Deepak S deepa...@linux.intel.com
On CHV, PUNIT team confirmed that 'VLV_GFX_CLK_STATUS_BIT' is
[cc'ing lists]
On Tue, Mar 10, 2015 at 07:17:22PM +0100, Krzysztof Kolasa wrote:
System ( 32bit, Intel 945GM ) hangs after some short time, oops:
[ cut here ]
kernel BUG at drivers/gpu/drm/drm_mm.c:305!
invalid opcode: [#1] SMP
Modules linked in: arc4 md4
On Wed, Mar 11, 2015 at 07:07:12PM +0530, Deepak S wrote:
On Friday 06 March 2015 10:10 PM, Daniel Vetter wrote:
On Thu, Mar 05, 2015 at 09:27:59PM +0530, deepa...@linux.intel.com wrote:
From: Deepak S deepa...@linux.intel.com
In normal cases, RC6 promotion timer is 1700us/500us. This
On Wednesday 11 March 2015 07:26 PM, Chris Wilson wrote:
On Wed, Mar 11, 2015 at 07:07:12PM +0530, Deepak S wrote:
On Friday 06 March 2015 10:10 PM, Daniel Vetter wrote:
On Thu, Mar 05, 2015 at 09:27:59PM +0530, deepa...@linux.intel.com wrote:
From: Deepak S deepa...@linux.intel.com
In
On Wed, 2015-03-11 at 13:26 +, Damien Lespiau wrote:
On Wed, Mar 11, 2015 at 01:33:00PM +0200, Ander Conselvan de Oliveira wrote:
So that it is possible to use a custom mode with the simplified mode set
API.
Maybe just igt_output_set_mode()?
That works too. I used override since
On Thursday 26 February 2015 09:42 PM, Chris Wilson wrote:
On Thu, Feb 26, 2015 at 08:46:56PM +0530, deepa...@linux.intel.com wrote:
From: Deepak S deepa...@linux.intel.com
After feedback from the hardware team, now we set the GPU min freq to RPe.
If we drop the freq to RPn, we found that
On Wed, Mar 11, 2015 at 07:23:48PM +0530, Deepak S wrote:
On Thursday 26 February 2015 09:42 PM, Chris Wilson wrote:
On Thu, Feb 26, 2015 at 08:46:56PM +0530, deepa...@linux.intel.com wrote:
From: Deepak S deepa...@linux.intel.com
After feedback from the hardware team, now we set the GPU
On Wed, Mar 11, 2015 at 03:48:00PM +0200, Ander Conselvan De Oliveira wrote:
On Wed, 2015-03-11 at 13:26 +, Damien Lespiau wrote:
On Wed, Mar 11, 2015 at 01:33:00PM +0200, Ander Conselvan de Oliveira wrote:
So that it is possible to use a custom mode with the simplified mode set
API.
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 5937
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV -4 281/281
On 2/25/2015 5:34 AM, Jani Nikula wrote:
Occasionally it would be interesting to read some of the DPCD registers
for debug purposes, without having to resort to logging. Add an i915
specific i915_dpcd debugfs file for DP and eDP connectors to dump parts
of the DPCD. Currently the DPCD addresses
LGTM,
Reviewed-by: Zhigang Gong zhigang.g...@linux.intel.com
Thanks.
-Original Message-
From: Beignet [mailto:beignet-boun...@lists.freedesktop.org] On Behalf Of
jeff.mc...@intel.com
Sent: Tuesday, March 10, 2015 7:36 AM
To: beig...@lists.freedesktop.org
Cc:
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