On Fri, Mar 13, 2015 at 11:19 PM, Paul Moore p...@paul-moore.com wrote:
Ever since v3.17 I've had a problem with displayport audio on my
system, but until lately I haven't had a chance to bisect the problem.
After a few rounds I've isolated the buggy commit to 0e32b39c
(drm/i915: add DP 1.2
This patch fix spelling typo in intel_runtime_pm.c
Signed-off-by: Masanari Iida standby2...@gmail.com
---
drivers/gpu/drm/i915/intel_runtime_pm.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
With the advent of mmap(wc), we have a path to write directly into
active GPU buffers. When combined with async updates (i.e. avoiding the
explicit domain management along with the memory barriers and GPU
stalls) we start to see the GPU read the wrong values from memory - i.e.
we have insufficient
On Mon, 11 May 2015, Jani Nikula jani.nik...@linux.intel.com wrote:
On Fri, 08 May 2015, Paul Moore p...@paul-moore.com wrote:
On Fri, Mar 13, 2015 at 11:19 PM, Paul Moore p...@paul-moore.com wrote:
Ever since v3.17 I've had a problem with displayport audio on my
system, but until lately I
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 6351
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV
This patch fixes a timing issue that causes a GPU hang when the system
comes out of power saving.
During pm_resume, We are submitting batchbuffers before enabling
Interrupts this is causing us to miss the context switch interrupt,
and in consequence intel_execlists_handle_ctx_events is not
On Fri, 08 May 2015, Paul Moore p...@paul-moore.com wrote:
On Fri, Mar 13, 2015 at 11:19 PM, Paul Moore p...@paul-moore.com wrote:
Ever since v3.17 I've had a problem with displayport audio on my
system, but until lately I haven't had a chance to bisect the problem.
After a few rounds I've
On Thu, May 07, 2015 at 08:37:40AM -0700, Jesse Barnes wrote:
On 05/06/2015 07:48 AM, Patrik Jakobsson wrote:
This patch set aims to make strace more useful when tracing i915 ioctls.
The ioctl type is first checked for being drm and then the driver
backing the opened device is identified by
On Mon, May 11, 2015 at 12:17:09AM +0530, Ankitprasad Sharma wrote:
On Fri, 2015-05-08 at 09:16 +0200, Daniel Vetter wrote:
On Fri, May 08, 2015 at 10:54:26AM +0530, Ankitprasad Sharma wrote:
On Thu, 2015-05-07 at 08:52 +0200, Daniel Vetter wrote:
On Wed, May 06, 2015 at 03:51:52PM
On Mon, May 11, 2015 at 08:51:36AM +0100, Chris Wilson wrote:
With the advent of mmap(wc), we have a path to write directly into
active GPU buffers. When combined with async updates (i.e. avoiding the
explicit domain management along with the memory barriers and GPU
stalls) we start to see the
On Mon, May 11, 2015 at 12:34:37PM +0200, Daniel Vetter wrote:
On Mon, May 11, 2015 at 08:51:36AM +0100, Chris Wilson wrote:
With the advent of mmap(wc), we have a path to write directly into
active GPU buffers. When combined with async updates (i.e. avoiding the
explicit domain management
On Mon, 11 May 2015, David Weinehall david.weineh...@linux.intel.com wrote:
On Wed, May 06, 2015 at 03:33:44PM +0300, Jani Nikula wrote:
Do no expose invalid gmbus pins as i2c devices to userspace.
Do not, perchance?
Indeed, and copy-pasted to both...
Jani.
Kind regards, David
--
Jani
BXT supports following intermediate link rates for edp:
2.16GHz, 2.43GHz, 3.24GHz, 4.32GHz.
Adding support for programming the intermediate rates.
v2: Adding clock in bxt_clk_div struct and then look for the entry with
required rate (Ville)
v3: 'clock' has the selected value, no need to use
Ensures that the batch buffer is executed by the resource streamer
Signed-off-by: Abdiel Janulgue abdiel.janul...@linux.intel.com
---
drivers/gpu/drm/i915/i915_gem_execbuffer.c | 15 +++
drivers/gpu/drm/i915/intel_ringbuffer.h| 1 +
include/uapi/drm/i915_drm.h|
This is a re-spin of my resource streamer patchset from a year ago.
The resource streamer is a hw-feature that helps in reducing commands
submitted by the CPU.
We have finally have the Mesa optimization that requires the use of
this interface.
Abdiel Janulgue (2):
drm/i915/hsw/bdw: Expose
On Fri, May 08, 2015 at 12:57:01PM -0400, Steven Rostedt wrote:
On Fri, 8 May 2015 12:18:10 -0400
Steven Rostedt rost...@goodmis.org wrote:
On Fri, 8 May 2015 12:08:31 -0400
Steven Rostedt rost...@goodmis.org wrote:
Maybe it's my bios still (it is an older box). I'll just block
On Mon, May 11, 2015 at 12:01:10PM +0300, Abdiel Janulgue wrote:
This is a re-spin of my resource streamer patchset from a year ago.
The resource streamer is a hw-feature that helps in reducing commands
submitted by the CPU.
Did you check that the contexts we allocate are large enough to hold
On 05/09/2015 04:22 AM, Chandra Konduru wrote:
In skylake update plane functions, intel_tile_height() is called with
bits_per_pixel instead of pixel_format. Correcting it.
Signed-off-by: Chandra Konduru chandra.kond...@intel.com
---
drivers/gpu/drm/i915/intel_display.c |2 +-
On Fri, May 08, 2015 at 07:13:34AM -0700, Todd Previte wrote:
The kerneldoc for this newly added parameter was missing from the
original patch. This patch adds the appropriate kerneldoc entry.
Signed-off-by: Todd Previte tprev...@gmail.com
Patch was a bit too late before I've done the
On Mon, May 11, 2015 at 01:21:43PM +0530, Sonika Jindal wrote:
BXT supports following intermediate link rates for edp:
2.16GHz, 2.43GHz, 3.24GHz, 4.32GHz.
Adding support for programming the intermediate rates.
v2: Adding clock in bxt_clk_div struct and then look for the entry with
required
On Sat, May 09, 2015 at 02:05:55AM +0100, Damien Lespiau wrote:
As we're doing throughout the code, being optimistic that platform n + 1
will mostly reuse the same things as platform n allows us to minimize
the enabling work needed.
This time, it's about the number of WM levels.
Hi,
On 05/08/2015 09:40 PM, Chandra Konduru wrote:
This patch is adding NV12 support to skylake primary plane
programming. It is covering linear/X/Y/Yf tiling formats
for 0 and 180 rotations.
For 90/270 rotation, Y and UV subplanes should be treated
as separate surfaces and GTT remapping
On Fri, May 08, 2015 at 08:22:46PM -0700, Chandra Konduru wrote:
In skylake update plane functions, intel_tile_height() is called with
bits_per_pixel instead of pixel_format. Correcting it.
Signed-off-by: Chandra Konduru chandra.kond...@intel.com
Queued for -next, thanks for the patch.
---
On Mon, May 11, 2015 at 10:19:58AM +0200, Daniel Martin wrote:
On 8 May 2015 at 17:13, Jani Nikula jani.nik...@linux.intel.com wrote:
On Fri, 08 May 2015, Daniel Martin consume.no...@gmail.com wrote:
On 8 May 2015 at 11:26, Daniel Martin consume.no...@gmail.com wrote:
Hi,
I've just
- Original Message -
From: Jani Nikula jani.nik...@linux.intel.com
To: Paul Moore p...@paul-moore.com, Dave Airlie airl...@redhat.com,
intel-gfx@lists.freedesktop.org
Cc: Daniel Gultsch dan...@gultsch.de, linux-ker...@vger.kernel.org
Sent: Monday, 11 May, 2015 6:01:49 PM
Subject:
With the recent modeset internal rework, we wind up setting crtc_state-enable
to false, but leave crtc_state-active as true following a
drmModeSetCrtc(fb=0), which is incorrect. This mismatch gets caught by
drm_atomic_crtc_check() and causes subsequent atomic operations (such as plane
updates
On Mon, May 11, 2015 at 10:45:15AM +0200, Maarten Lankhorst wrote:
With the recent modeset internal rework, we wind up setting crtc_state-enable
to false, but leave crtc_state-active as true following a
drmModeSetCrtc(fb=0), which is incorrect. This mismatch gets caught by
On Wed, 6 May 2015 16:48:01 +0200
Patrik Jakobsson patrik.jakobs...@linux.intel.com wrote:
This patch set aims to make strace more useful when tracing i915 ioctls.
The ioctl type is first checked for being drm and then the driver
backing the opened device is identified by looking at sysfs.
On Sun, May 10, 2015 at 01:00:23AM +0900, Masanari Iida wrote:
This patch fix spelling typo in intel_runtime_pm.c
Signed-off-by: Masanari Iida standby2...@gmail.com
Queued for -next, thanks for the patch.
-Daniel
---
drivers/gpu/drm/i915/intel_runtime_pm.c | 4 ++--
1 file changed, 2
On Fri, May 08, 2015 at 06:23:45PM +0100, Damien Lespiau wrote:
On Mon, Apr 27, 2015 at 03:47:37PM -0700, Chandra Konduru wrote:
Skylake nv12 format requires dbuf (aka. ddb) calculations
and programming for each of y and uv sub-planes. Made minor
changes to reuse current dbuf calculations
On Fri, May 08, 2015 at 01:02:36PM +0100, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin tvrtko.ursu...@intel.com
Signed-off-by: Tvrtko Ursulin tvrtko.ursu...@intel.com
Queued for -next, thanks for the patch.
-Daniel
---
drivers/gpu/drm/i915/intel_drv.h | 3 ---
1 file changed, 3
On Mon, May 11, 2015 at 08:50:45AM +0100, Peter Antoine wrote:
This patch fixes a timing issue that causes a GPU hang when the system
comes out of power saving.
During pm_resume, We are submitting batchbuffers before enabling
Interrupts this is causing us to miss the context switch
On Mon, May 11, 2015 at 11:54:11AM +0100, Tvrtko Ursulin wrote:
Hi,
On 05/01/2015 04:43 AM, Chandra Konduru wrote:
This patch adds NV12 as supported format to
intel_framebuffer_init and performs various checks.
Signed-off-by: Chandra Konduru chandra.kond...@intel.com
Testcase:
On 11/05/15 08:50, Peter Antoine wrote:
This patch fixes a timing issue that causes a GPU hang when the system
comes out of power saving.
During pm_resume, We are submitting batchbuffers before enabling
Interrupts this is causing us to miss the context switch interrupt,
and in consequence
On Wed, May 06, 2015 at 03:33:44PM +0300, Jani Nikula wrote:
Do no expose invalid gmbus pins as i2c devices to userspace.
Do not, perchance?
Kind regards, David
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
On Sat, May 09, 2015 at 11:04:28AM +0530, Deepak S wrote:
On Friday 08 May 2015 10:09 PM, Ville Syrjälä wrote:
On Fri, May 08, 2015 at 08:43:12PM +0530, deepa...@linux.intel.com wrote:
From: Deepak S deepa...@linux.intel.com
After feedback from the hardware team, now we set the GPU
Adds support for executing the resource streamer on BDW
Signed-off-by: Abdiel Janulgue abdiel.janul...@linux.intel.com
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_ringbuffer.c | 6 --
2 files changed, 5 insertions(+), 2 deletions(-)
diff --git
On Fri, May 08, 2015 at 06:23:45PM +0100, Damien Lespiau wrote:
On Mon, Apr 27, 2015 at 03:47:37PM -0700, Chandra Konduru wrote:
Skylake nv12 format requires dbuf (aka. ddb) calculations
and programming for each of y and uv sub-planes. Made minor
changes to reuse current dbuf calculations
On Sat, May 09, 2015 at 06:15:46PM +0530, deepa...@linux.intel.com wrote:
From: Deepak S deepa...@linux.intel.com
After feedback from the hardware team, now we set the GPU min/idel freq to
RPe.
Punit is expecting us to operate GPU between Rpe Rp0. If we drop the
frequency to RPn, punit is
Hi,
On 05/01/2015 04:43 AM, Chandra Konduru wrote:
This patch adds NV12 as supported format to
intel_framebuffer_init and performs various checks.
Signed-off-by: Chandra Konduru chandra.kond...@intel.com
Testcase: igt/kms_nv12
---
drivers/gpu/drm/i915/intel_display.c | 27
This patch fixed a timing issue that causes a GPU hang when a the system
comes out of power saving.
During pm_resume, We are submitting batchbuffers before enabling
Interrupts this is causing us to miss the context switch interrupt,
and in consequence intel_execlists_handle_ctx_events is not
On Sat, May 09, 2015 at 11:05:27AM +0530, Deepak S wrote:
On Friday 08 May 2015 09:35 PM, Ville Syrjälä wrote:
On Fri, May 08, 2015 at 08:19:12PM +0530, Deepak S wrote:
On Friday 10 April 2015 08:51 PM, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä
This patch fixed a timing issue that causes a GPU hang when a the system
comes out of power saving.
During pm_resume, We are submitting batchbuffers before enabling
Interrupts this is causing us to miss the context switch interrupt,
and in consequence intel_execlists_handle_ctx_events is not
On Mon, May 11, 2015 at 12:05:27PM +0100, Peter Antoine wrote:
This patch fixed a timing issue that causes a GPU hang when a the system
comes out of power saving.
During pm_resume, We are submitting batchbuffers before enabling
Interrupts this is causing us to miss the context switch
On Mon, May 11, 2015 at 08:50:45AM +0100, Peter Antoine wrote:
This patch fixes a timing issue that causes a GPU hang when the system
comes out of power saving.
During pm_resume, We are submitting batchbuffers before enabling
Interrupts this is causing us to miss the context switch
Hi,
On 05/09/2015 05:32 AM, Chandra Konduru wrote:
From: chandra konduru chandra.kond...@intel.com
This patch adds kms_nv12 test case. It covers testing NV12 in
all supported linear/tile-X/tile-Y/tile-Yf tile formats in
0 and 180 orientations. For each tiling format, it tests
various
On Fri, May 08, 2015 at 08:22:47PM -0700, Chandra Konduru wrote:
Adding NV12 90/270 rotation support for primary and sprite planes.
Signed-off-by: Chandra Konduru chandra.kond...@intel.com
---
drivers/gpu/drm/i915/intel_display.c | 23 ---
On 11 May 2015 at 12:35, Daniel Vetter dan...@ffwll.ch wrote:
On Mon, May 11, 2015 at 10:19:58AM +0200, Daniel Martin wrote:
Just tested
b5a0fd0 drm-intel-nightly: 2015y-05m-11d-06h-03m-04s UTC
integration manifest
The problem still exists.
Yeah that one is busted unfortunately. I've
On Mon, May 11, 2015 at 12:50:36PM +0200, Gabriel Laskar wrote:
On Wed, 6 May 2015 16:48:01 +0200
Patrik Jakobsson patrik.jakobs...@linux.intel.com wrote:
This patch set aims to make strace more useful when tracing i915 ioctls.
The ioctl type is first checked for being drm and then the
Those messages where missing a new line at the end. Take the opportunity
to re-format the messages to fit in the 80 chars limit.
Signed-off-by: Damien Lespiau damien.lesp...@intel.com
---
lib/igt_aux.c | 12
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/lib/igt_aux.c
Removed some occurences, roughly based on where the errors of
removing crtc-config occured. Because it's used a lot in this
file the changes are done in passes.
Signed-off-by: Maarten Lankhorst maarten.lankho...@linux.intel.com
---
drivers/gpu/drm/i915/intel_display.c | 205
From: Ander Conselvan de Oliveira ander.conselvan.de.olive...@intel.com
A follow up patch will make intel_modeset_compute_config() deal with
multiple crtcs, so move crtc specific stuff into the lower level crtc
specific function.
Signed-off-by: Maarten Lankhorst maarten.lankho...@linux.intel.com
crtc-config is gone, swap swap swap. :D
Signed-off-by: Maarten Lankhorst maarten.lankho...@linux.intel.com
---
drivers/gpu/drm/i915/intel_atomic.c | 36 ++--
drivers/gpu/drm/i915/intel_display.c | 7 +--
2 files changed, 7 insertions(+), 36 deletions(-)
This is now unused, goodbye. :-)
Signed-off-by: Maarten Lankhorst maarten.lankho...@linux.intel.com
---
drivers/gpu/drm/i915/intel_display.c | 2 --
drivers/gpu/drm/i915/intel_drv.h | 1 -
2 files changed, 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
Now that the dpll updates are (mostly) atomic, the .off() code is no longer
used,
and there are no more callers for intel_put_shared_dpll. Move all the updates
done in intel_crtc_disable to intel_modeset_update_state, one less special case
to worry about.
Changes since v1:
- Move
This prevents unnecessarily updating power domains, while still
enabling all power domains on initial setup.
Signed-off-by: Maarten Lankhorst maarten.lankho...@linux.intel.com
---
drivers/gpu/drm/i915/intel_display.c | 52
1 file changed, 41 insertions(+), 11
Drivers may need to store the state of shared resources, such as PLLs
or FIFO space, into the atomic state. Allow this by making it possible
to subclass drm_atomic_state.
Cc: dri-de...@lists.freedesktop.org
Acked-by: Ander Conselvan de Oliveira ander.conselvan.de.olive...@intel.com
Signed-off-by:
On 5/7/2015 1:07 PM, Jani Nikula wrote:
On Thu, 07 May 2015, Vandana Kannan vandana.kan...@intel.com wrote:
Changes for BXT - added a IS_BROXTON check to use the macro related to PPS
registers for BXT.
BXT does not have PP_DIV register. Making changes to handle this.
Second set of PPS
On Mon, May 11, 2015 at 12:34:37PM +0200, Daniel Vetter wrote:
On Mon, May 11, 2015 at 08:51:36AM +0100, Chris Wilson wrote:
With the advent of mmap(wc), we have a path to write directly into
active GPU buffers. When combined with async updates (i.e. avoiding the
explicit domain management
This removes a lot of users for crtc-config.
Signed-off-by: Maarten Lankhorst maarten.lankho...@linux.intel.com
---
drivers/gpu/drm/i915/intel_crt.c | 21 ++
drivers/gpu/drm/i915/intel_ddi.c | 78 +---
drivers/gpu/drm/i915/intel_display.c | 36
This should be safe.
Signed-off-by: Maarten Lankhorst maarten.lankho...@linux.intel.com
---
drivers/gpu/drm/i915/intel_display.c | 82 ++--
1 file changed, 41 insertions(+), 41 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
Signed-off-by: Maarten Lankhorst maarten.lankho...@linux.intel.com
---
drivers/gpu/drm/i915/intel_ddi.c | 15 ---
1 file changed, 8 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index c5a9e36d6a0e..388f02a8e6e1 100644
Signed-off-by: Maarten Lankhorst maarten.lankho...@linux.intel.com
---
drivers/gpu/drm/i915/intel_psr.c | 25 ++---
1 file changed, 14 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index
No longer any different from state-enable.
v2: Keep track of enabled crtc's for calling intel_crtc_restore_mode.
Signed-off-by: Maarten Lankhorst maarten.lankho...@linux.intel.com
---
drivers/gpu/drm/i915/intel_display.c | 63 +++-
From: Ander Conselvan de Oliveira ander.conselvan.de.olive...@intel.com
This lets us change the force restore path in setup_hw_state() to use a
single call to intel_mode_set() to restore all the previous user
requested state.
Signed-off-by: Ander Conselvan de Oliveira
Signed-off-by: Maarten Lankhorst maarten.lankho...@linux.intel.com
---
drivers/gpu/drm/i915/intel_audio.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_audio.c
b/drivers/gpu/drm/i915/intel_audio.c
index c4312177b0ee..dd74fd3157ee 100644
---
Signed-off-by: Maarten Lankhorst maarten.lankho...@linux.intel.com
---
drivers/gpu/drm/i915/i915_debugfs.c | 18 --
drivers/gpu/drm/i915/intel_display.c | 68 +---
drivers/gpu/drm/i915/intel_drv.h | 1 -
3 files changed, 39 insertions(+), 48
Signed-off-by: Maarten Lankhorst maarten.lankho...@linux.intel.com
---
drivers/gpu/drm/i915/intel_hdmi.c | 58 +++
1 file changed, 35 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c
b/drivers/gpu/drm/i915/intel_hdmi.c
index
Signed-off-by: Maarten Lankhorst maarten.lankho...@linux.intel.com
---
drivers/gpu/drm/i915/intel_dp_mst.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c
b/drivers/gpu/drm/i915/intel_dp_mst.c
index 4992c8025520..4ecbc58c4e04 100644
This kills off most of the transitional helpers and uses atomic plane updates
in the modeset path to update everything.
Getting rid of the transitional plane helpers meant that planes had to be added
in the crtc check function. On modeset a connector can be moved to a different
crtc, and this is
Convert the rest of the file, but remove crtc-config in a separate
commit to hopefully allow easier bisecting.
Signed-off-by: Maarten Lankhorst maarten.lankho...@linux.intel.com
---
drivers/gpu/drm/i915/intel_display.c | 351 ++-
drivers/gpu/drm/i915/intel_dp.c
Signed-off-by: Maarten Lankhorst maarten.lankho...@linux.intel.com
---
drivers/gpu/drm/i915/i915_drv.h | 3 +-
drivers/gpu/drm/i915/intel_display.c | 207 ++-
drivers/gpu/drm/i915/intel_dp.c | 2 +
drivers/gpu/drm/i915/intel_drv.h | 10 +-
Don't walk the crtc_state twice if there's no need for it.
Signed-off-by: Maarten Lankhorst maarten.lankho...@linux.intel.com
---
drivers/gpu/drm/i915/intel_display.c | 13 +++--
1 file changed, 7 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
From: Ander Conselvan de Oliveira ander.conselvan.de.olive...@intel.com
It makes more sense there, since these are computation steps that can
fail.
Signed-off-by: Maarten Lankhorst maarten.lankho...@linux.intel.com
---
drivers/gpu/drm/i915/intel_display.c | 70
Signed-off-by: Maarten Lankhorst maarten.lankho...@linux.intel.com
---
drivers/gpu/drm/i915/intel_pm.c | 96 -
1 file changed, 46 insertions(+), 50 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index
Signed-off-by: Maarten Lankhorst maarten.lankho...@linux.intel.com
---
drivers/gpu/drm/i915/intel_dp.c | 33 ++---
1 file changed, 18 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index
This patch makes this happen by consolidating all modeset paths
and getting rid of most transitional state.
This happens first by unifying all paths so all code that
disables a crtc goes through either intel_crtc_toggle or
__intel_set_mode. After that's done crtc_state-active is
updated in
Assume the function is locked with drm_modeset_lock_all for now.
Signed-off-by: Maarten Lankhorst maarten.lankho...@linux.intel.com
---
drivers/gpu/drm/i915/i915_irq.c | 2 +-
drivers/gpu/drm/i915/intel_display.c | 79 ++--
2 files changed, 50 insertions(+),
Signed-off-by: Maarten Lankhorst maarten.lankho...@linux.intel.com
---
drivers/gpu/drm/i915/intel_overlay.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_overlay.c
b/drivers/gpu/drm/i915/intel_overlay.c
index 5fd2d5ac02e2..fa0ff6974dcc
Signed-off-by: Maarten Lankhorst maarten.lankho...@linux.intel.com
---
drivers/gpu/drm/i915/intel_fbc.c | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c
index 6abb83432d4d..098461ce1fe4 100644
---
No need to repeatedly call update_watermarks, or update_fbc.
For update_watermarks once should be enough after disabling crtc's
and swapping the state.
Down to a single call to update_watermarks in .crtc_enable
Signed-off-by: Maarten Lankhorst maarten.lankho...@linux.intel.com
---
Must start somewhere to get rid of crtc-config.
Signed-off-by: Maarten Lankhorst maarten.lankho...@linux.intel.com
---
drivers/gpu/drm/i915/i915_irq.c | 13 ++---
drivers/gpu/drm/i915/intel_display.c | 6 ++
2 files changed, 12 insertions(+), 7 deletions(-)
diff --git
Done as a separate commit to allow better bisecting.
Signed-off-by: Maarten Lankhorst maarten.lankho...@linux.intel.com
---
drivers/gpu/drm/i915/intel_display.c | 50 +---
1 file changed, 7 insertions(+), 43 deletions(-)
diff --git
Another abuser gone.
Signed-off-by: Maarten Lankhorst maarten.lankho...@linux.intel.com
---
drivers/gpu/drm/i915/i915_debugfs.c | 42 -
1 file changed, 27 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
Signed-off-by: Maarten Lankhorst maarten.lankho...@linux.intel.com
---
drivers/gpu/drm/i915/intel_fbdev.c | 19 +++
1 file changed, 11 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_fbdev.c
b/drivers/gpu/drm/i915/intel_fbdev.c
index
Signed-off-by: Maarten Lankhorst maarten.lankho...@linux.intel.com
---
drivers/gpu/drm/i915/intel_display.c | 15 ---
drivers/gpu/drm/i915/intel_drv.h | 5 -
2 files changed, 4 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
Signed-off-by: Maarten Lankhorst maarten.lankho...@linux.intel.com
---
drivers/gpu/drm/i915/intel_dsi.c | 14 --
1 file changed, 8 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 3f28b046751b..ec5f4509dc87 100644
From: Ander Conselvan de Oliveira ander.conselvan.de.olive...@intel.com
The last remaining portion that required the modeset_crtc argument is
converted to deal with all crtcs in the state that need_modeset(). By
doing that, __intel_set_mode() is generic enough, behaving like a commit
function for
Small behavioral change: DPLL_DVO_2X_MODE may stay enabled during modeset
for I830 if new state requires it, instead of being disabled and enabled
again.
Signed-off-by: Maarten Lankhorst maarten.lankho...@linux.intel.com
---
drivers/gpu/drm/i915/intel_display.c | 140
From: Ander Conselvan de Oliveira ander.conselvan.de.olive...@intel.com
Compute new pipe_configs for all crtcs in the atomic state. The commit
part of the mode set (__intel_set_mode()) is already enabled to support
multiple pipes, the only thing missing was calculating a new pipe_config
for every
Signed-off-by: Maarten Lankhorst maarten.lankho...@linux.intel.com
---
drivers/gpu/drm/i915/intel_display.c | 16 +---
drivers/gpu/drm/i915/intel_drv.h | 6 --
2 files changed, 5 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
Signed-off-by: Maarten Lankhorst maarten.lankho...@linux.intel.com
---
drivers/gpu/drm/i915/intel_sdvo.c | 19 +++
1 file changed, 11 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_sdvo.c
b/drivers/gpu/drm/i915/intel_sdvo.c
index 6a68098f8b08..93b31d66a1ab
From: Ander Conselvan de Oliveira ander.conselvan.de.olive...@intel.com
Signed-off-by: Maarten Lankhorst maarten.lankho...@linux.intel.com
---
drivers/gpu/drm/i915/i915_drv.h | 1 -
drivers/gpu/drm/i915/intel_atomic.c | 49
drivers/gpu/drm/i915/intel_display.c | 111
Signed-off-by: Maarten Lankhorst maarten.lankho...@linux.intel.com
---
drivers/gpu/drm/i915/intel_atomic.c | 10 +++---
drivers/gpu/drm/i915/intel_sprite.c | 4 ++--
2 files changed, 5 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_atomic.c
Signed-off-by: Maarten Lankhorst maarten.lankho...@linux.intel.com
---
drivers/gpu/drm/i915/intel_display.c | 109 +--
drivers/gpu/drm/i915/intel_drv.h | 2 +
2 files changed, 81 insertions(+), 30 deletions(-)
diff --git
On 5/7/2015 2:57 PM, Imre Deak wrote:
On to, 2015-05-07 at 12:00 +0530, Vandana Kannan wrote:
BUN 1: prop_coeff, int_coeff, tdctargetcnt programming updated and tied to
VCO frequencies. Program i_lockthresh in PORT_PLL_9.
VCO calculated based on the formula:
Desired Output = Port bit rate in
If an batch ends while the IRQs are not turned on the notification can
go missing and the GPU can hang. So generate a warning in this case.
Signed-off-by: Peter Antoine peter.anto...@intel.com
---
drivers/gpu/drm/i915/intel_lrc.c | 6 ++
1 file changed, 6 insertions(+)
diff --git
On Mon, 11 May 2015 15:54:24 +0200
Patrik Jakobsson patrik.jakobs...@linux.intel.com wrote:
On Mon, May 11, 2015 at 12:50:36PM +0200, Gabriel Laskar wrote:
On Wed, 6 May 2015 16:48:01 +0200
Patrik Jakobsson patrik.jakobs...@linux.intel.com wrote:
This patch set aims to make strace
On Mon, May 11, 2015 at 04:24:44PM +0200, Maarten Lankhorst wrote:
Assume the function is locked with drm_modeset_lock_all for now.
s/toggle/control/ in the commit message.
And a bit of blabla would be good to explain why we need to make a
mass-replacement of state-enable to state-active here
From: Gaurav K Singh gaurav.k.si...@intel.com
For MIPI panels requiring higher DSI clk, values needs to be added
in lfsr_converts table for getting the correct values of pll ctrl
and dividor values which gets programmed in cck regs, otherwise DSI
PLL does not get locked leading to no display on
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