On Wed, Jul 08, 2015 at 10:40:18AM +0530, Jindal, Sonika wrote:
On 7/7/2015 6:51 PM, Ville Syrjälä wrote:
On Tue, Jul 07, 2015 at 02:22:20PM +0530, Sonika Jindal wrote:
Writing to PCH_PORT_HOTPLUG for each interrupt is not required.
Handle it only if hpd has actually occurred like we
On Tue, Jul 07, 2015 at 08:23:46PM +, Vivi, Rodrigo wrote:
On Tue, 2015-07-07 at 13:24 +0200, Daniel Vetter wrote:
On Mon, Jul 06, 2015 at 11:19:03PM +, Vivi, Rodrigo wrote:
On Mon, 2015-07-06 at 19:56 +0200, Daniel Vetter wrote:
On Mon, Jul 06, 2015 at 02:11:55PM -0300, Paulo
On Tue, Jul 07, 2015 at 04:02:32PM +0200, Maarten Lankhorst wrote:
Op 07-07-15 om 13:16 schreef Daniel Vetter:
On Tue, Jul 07, 2015 at 09:08:18AM +0200, Maarten Lankhorst wrote:
Make sure the primary plane is set up correctly. This is done by
setting plane_state-src and plane_state-crtc.
On Wed, Jul 01, 2015 at 05:23:51PM +0200, Daniel Vetter wrote:
On Wed, Jul 1, 2015 at 2:21 PM, David Weinehall
david.weineh...@linux.intel.com wrote:
On Tue, Jun 30, 2015 at 03:01:06PM +0100, Chris Wilson wrote:
On Tue, Jun 30, 2015 at 04:36:55PM +0300, David Weinehall wrote:
On Tue, Jun
On 7/7/2015 5:50 PM, Sivakumar Thulasimani wrote:
On 7/7/2015 5:24 PM, Ville Syrjälä wrote:
On Tue, Jul 07, 2015 at 02:37:46PM +0300, Ville Syrjälä wrote:
On Tue, Jul 07, 2015 at 04:45:11PM +0530, Sivakumar Thulasimani wrote:
On 7/7/2015 4:40 PM, Ville Syrjälä wrote:
On Tue, Jul 07, 2015
Op 08-07-15 om 11:27 schreef Daniel Vetter:
On Tue, Jul 07, 2015 at 04:02:32PM +0200, Maarten Lankhorst wrote:
Op 07-07-15 om 13:16 schreef Daniel Vetter:
On Tue, Jul 07, 2015 at 09:08:18AM +0200, Maarten Lankhorst wrote:
Make sure the primary plane is set up correctly. This is done by
On 7/7/2015 9:08 PM, Chris Wilson wrote:
On Tue, Jul 07, 2015 at 04:44:30PM +0100, Michel Thierry wrote:
On 7/7/2015 4:27 PM, Chris Wilson wrote:
On Tue, Jul 07, 2015 at 04:14:59PM +0100, Michel Thierry wrote:
In a 48b world, users can try to allocate buffers bigger than 4GB; in
these cases
On Wed, Jul 08, 2015 at 05:50:05PM +0530, Sivakumar Thulasimani wrote:
On 7/7/2015 5:50 PM, Sivakumar Thulasimani wrote:
On 7/7/2015 5:24 PM, Ville Syrjälä wrote:
On Tue, Jul 07, 2015 at 02:37:46PM +0300, Ville Syrjälä wrote:
On Tue, Jul 07, 2015 at 04:45:11PM +0530, Sivakumar
Writing to PCH_PORT_HOTPLUG for each interrupt is not required.
Handle it only if hpd has actually occurred like we handle other
interrupts.
v2: Make few variables local to if block (Ville)
v3: Add check for ibx/cpt both (Ville).
While at it, remove the redundant check for hotplug_trigger from
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 6745
-Summary-
Platform Delta drm-intel-nightly Series Applied
ILK -9
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 6740
-Summary-
Platform Delta drm-intel-nightly Series Applied
ILK
Op 08-07-15 om 11:09 schreef Daniel Vetter:
On Wed, Jul 08, 2015 at 10:38:33AM +0200, Maarten Lankhorst wrote:
Op 07-07-15 om 12:11 schreef Daniel Vetter:
On Tue, Jul 07, 2015 at 09:08:17AM +0200, Maarten Lankhorst wrote:
@@ -12392,27 +12379,124 @@ static bool intel_fuzzy_clock_check(int
On Tue, Jul 07, 2015 at 04:28:56PM -0700, Rodrigo Vivi wrote:
fbdev_set_par is called when fbcon is taking over control, but
frontbuffer was being invalidated only on the first time when
moving obj to GTT domain.
However on the following calls write domain was already GTT
so invalidate was
Op 07-07-15 om 11:15 schreef Daniel Vetter:
Since
commit 8c7b5ccb729870e606321b3703e2c2e698c49a95
Author: Ander Conselvan de Oliveira ander.conselvan.de.olive...@intel.com
Date: Tue Apr 21 17:13:19 2015 +0300
drm/i915: Use atomic helpers for computing changed flags
we compute the
On Wed, Jul 08, 2015 at 10:00:22AM +0200, Maarten Lankhorst wrote:
Op 07-07-15 om 18:43 schreef Daniel Vetter:
On Tue, Jul 07, 2015 at 05:08:34PM +0200, Maarten Lankhorst wrote:
Op 07-07-15 om 14:10 schreef Daniel Vetter:
On Tue, Jul 07, 2015 at 12:20:10PM +0200, Maarten Lankhorst wrote:
On Wed, Jul 08, 2015 at 11:18:27AM +0200, Maarten Lankhorst wrote:
Op 08-07-15 om 11:09 schreef Daniel Vetter:
On Wed, Jul 08, 2015 at 10:38:33AM +0200, Maarten Lankhorst wrote:
Op 07-07-15 om 12:11 schreef Daniel Vetter:
On Tue, Jul 07, 2015 at 09:08:17AM +0200, Maarten Lankhorst wrote:
On Wed, Jul 08, 2015 at 10:45:23AM +0100, Tvrtko Ursulin wrote:
On 07/08/2015 10:32 AM, Daniel Vetter wrote:
On Mon, Jul 06, 2015 at 04:19:01PM +0100, Chris Wilson wrote:
On Mon, Jul 06, 2015 at 03:15:01PM +0100, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin tvrtko.ursu...@intel.com
When
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 6744
-Summary-
Platform Delta drm-intel-nightly Series Applied
ILK
Op 07-07-15 om 12:11 schreef Daniel Vetter:
On Tue, Jul 07, 2015 at 09:08:17AM +0200, Maarten Lankhorst wrote:
Instead of doing ad-hoc checks we already have a way of checking
if the state is compatible or not. Use this to force a modeset.
Only during modesets, or with
wa_ctx_emit() depends on the name of a local variable; if the name of that
variable is changed then we get compile errors. In this case it is unlikely
to be changed as this macro is only used in this set of functions but
Kernel coding guidelines doesn't recommend doing this. It was my mistake
as I
On Wed 08-07-15 09:32:18, Daniel Vetter wrote:
[...]
Ok that's starting to get nasty. Can you please test what happens when you
boot with drm.vblankoffdelay=0 and whether drm.vblankoffdelay=1000 has an
effect on reproduction rate? No debug output needed.
No difference. See the kernel log from
Op 07-07-15 om 18:43 schreef Daniel Vetter:
On Tue, Jul 07, 2015 at 05:08:34PM +0200, Maarten Lankhorst wrote:
Op 07-07-15 om 14:10 schreef Daniel Vetter:
On Tue, Jul 07, 2015 at 12:20:10PM +0200, Maarten Lankhorst wrote:
Op 07-07-15 om 11:18 schreef Daniel Vetter:
On Tue, Jul 07, 2015 at
On Tue, Jul 07, 2015 at 04:28:53PM -0700, Rodrigo Vivi wrote:
Let's do a frontbuffer flush on dirty fb.
To be used for DIRTYFB drm ioctl.
This patch solves the biggest PSR known issue, that is
missed screen updates during boot, mainly when there is a splash
screen involved like Plymouth.
On 07/08/2015 10:32 AM, Daniel Vetter wrote:
On Mon, Jul 06, 2015 at 04:19:01PM +0100, Chris Wilson wrote:
On Mon, Jul 06, 2015 at 03:15:01PM +0100, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin tvrtko.ursu...@intel.com
When rotated and partial views were added no one spotted the resume
path
Op 08-07-15 om 10:12 schreef Patrik Jakobsson:
On Tue, Jul 07, 2015 at 04:14:01PM +0200, Maarten Lankhorst wrote:
Op 07-07-15 om 14:39 schreef Patrik Jakobsson:
On Tue, Jul 07, 2015 at 12:22:12PM +0200, Maarten Lankhorst wrote:
Op 07-07-15 om 11:18 schreef Daniel Vetter:
On Tue, Jul 07, 2015
On Mon, Jul 06, 2015 at 04:19:01PM +0100, Chris Wilson wrote:
On Mon, Jul 06, 2015 at 03:15:01PM +0100, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin tvrtko.ursu...@intel.com
When rotated and partial views were added no one spotted the resume
path which assumes only one GGTT VMA per object
On Wed, Jul 08, 2015 at 11:38:02AM +0200, Daniel Vetter wrote:
On Tue, Jul 07, 2015 at 03:26:06PM -0300, Paulo Zanoni wrote:
From: Paulo Zanoni paulo.r.zan...@intel.com
The poor in_dbg_master() check was the only one without a reason
string. Give it a reason string so it won't feel
On Tue, Jul 07, 2015 at 04:14:01PM +0200, Maarten Lankhorst wrote:
Op 07-07-15 om 14:39 schreef Patrik Jakobsson:
On Tue, Jul 07, 2015 at 12:22:12PM +0200, Maarten Lankhorst wrote:
Op 07-07-15 om 11:18 schreef Daniel Vetter:
On Tue, Jul 07, 2015 at 09:08:14AM +0200, Maarten Lankhorst wrote:
On Wed, Jul 08, 2015 at 10:38:33AM +0200, Maarten Lankhorst wrote:
Op 07-07-15 om 12:11 schreef Daniel Vetter:
On Tue, Jul 07, 2015 at 09:08:17AM +0200, Maarten Lankhorst wrote:
@@ -12392,27 +12379,124 @@ static bool intel_fuzzy_clock_check(int clock1,
int clock2)
On 7/6/2015 5:14 PM, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
Since
commit e62925567c7926e78bc8ca976cde5c28ea265a49
Author: Vandana Kannan vandana.kan...@intel.com
Date: Wed Jul 1 17:02:57 2015 +0530
drm/i915/bxt: BUNs related to
On Tue, Jul 07, 2015 at 08:53:23PM +0100, Chris Wilson wrote:
On Tue, Jul 07, 2015 at 03:26:02PM -0300, Paulo Zanoni wrote:
From: Paulo Zanoni paulo.r.zan...@intel.com
Before I continue sending fixes, let's just do some small adjustments to the
codebase. I really think these changes make
On 07/08/2015 07:51 AM, ankitprasad.r.sha...@intel.com wrote:
From: Rodrigo Vivi rodrigo.vivi at intel.com
When constructing a batchbuffer, it is sometimes crucial to know the
largest hole into which we can fit a fenceable buffer (for example when
handling very large objects on gen2 and gen3).
2015-07-07 20:28 GMT-03:00 Rodrigo Vivi rodrigo.v...@intel.com:
This will be useful to PSR and FBC once we start making
dirty fb calls to also flush frontbuffer.
Cc: Daniel Vetter daniel.vet...@ffwll.ch
Cc: Paulo Zanoni paulo.r.zan...@intel.com
Reviewed-by: Paulo Zanoni
Hi,
On 07/08/2015 07:51 AM, ankitprasad.r.sha...@intel.com wrote:
From: Ankitprasad Sharma ankitprasad.r.sha...@intel.com
This patch extends the GET_APERTURE ioctl to add support
for getting total size and available size of the stolen region
as well as single largest block available in the
On Wed, Jul 08, 2015 at 02:28:33PM +0100, Chris Wilson wrote:
On Wed, Jul 08, 2015 at 02:13:43PM +0100, Tvrtko Ursulin wrote:
Hi,
On 07/08/2015 07:51 AM, ankitprasad.r.sha...@intel.com wrote:
From: Rodrigo Vivi rodrigo.vivi at intel.com
When constructing a batchbuffer, it is
Chris Wilson ch...@chris-wilson.co.uk writes:
On Wed, Jul 08, 2015 at 03:50:06PM +0300, Francisco Jerez wrote:
Chris Wilson ch...@chris-wilson.co.uk writes:
On Tue, Jul 07, 2015 at 10:13:01PM +0300, Francisco Jerez wrote:
From: Peter Antoine peter.anto...@intel.com
This change adds
2015-07-08 6:47 GMT-03:00 Daniel Vetter dan...@ffwll.ch:
On Tue, Jul 07, 2015 at 04:28:53PM -0700, Rodrigo Vivi wrote:
Let's do a frontbuffer flush on dirty fb.
To be used for DIRTYFB drm ioctl.
Just a notice: this commit will also be useful for FBC, so I hope that
marking the commit title as
Chris Wilson ch...@chris-wilson.co.uk writes:
On Tue, Jul 07, 2015 at 10:13:01PM +0300, Francisco Jerez wrote:
From: Peter Antoine peter.anto...@intel.com
This change adds the programming of the MOCS registers to the gen 9+
platforms. This change set programs the MOCS register values to a
On Wed, Jul 08, 2015 at 02:13:43PM +0100, Tvrtko Ursulin wrote:
Hi,
On 07/08/2015 07:51 AM, ankitprasad.r.sha...@intel.com wrote:
From: Rodrigo Vivi rodrigo.vivi at intel.com
When constructing a batchbuffer, it is sometimes crucial to know the
largest hole into which we can fit a
On 07/08/2015 02:28 PM, Chris Wilson wrote:
On Wed, Jul 08, 2015 at 02:13:43PM +0100, Tvrtko Ursulin wrote:
Hi,
On 07/08/2015 07:51 AM, ankitprasad.r.sha...@intel.com wrote:
From: Rodrigo Vivi rodrigo.vivi at intel.com
When constructing a batchbuffer, it is sometimes crucial to know the
Hi,
On 07/08/2015 07:51 AM, ankitprasad.r.sha...@intel.com wrote:
From: Rodrigo Vivi rodrigo.vivi at intel.com
When constructing a batchbuffer, it is sometimes crucial to know the
largest hole into which we can fit a fenceable buffer (for example when
handling very large objects on gen2 and
On 7/7/2015 5:01 PM, Daniel Vetter wrote:
On Tue, Jul 07, 2015 at 04:10:49PM +0530, Sivakumar Thulasimani wrote:
From: Thulasimani,Sivakumar sivakumar.thulasim...@intel.com
Update the hotplug documentation to explain that hotplug storm
is not expected for Display port panels and hence is not
On Wed, Jul 08, 2015 at 03:50:06PM +0300, Francisco Jerez wrote:
Chris Wilson ch...@chris-wilson.co.uk writes:
On Tue, Jul 07, 2015 at 10:13:01PM +0300, Francisco Jerez wrote:
From: Peter Antoine peter.anto...@intel.com
This change adds the programming of the MOCS registers to the gen
Watermark calculations depend on the intel_crtc-active flag to be set
properly. Suspend/resume is broken on SKL and we also get DDB mismatches
without this patch.
The regression was introduced in:
commit eddfcbcdc27fbecb33bff098967bbdd7ca75bfa6
Author: Maarten Lankhorst
On Wed, Jul 08, 2015 at 02:36:08PM +0100, Tvrtko Ursulin wrote:
On 07/08/2015 02:28 PM, Chris Wilson wrote:
On Wed, Jul 08, 2015 at 02:13:43PM +0100, Tvrtko Ursulin wrote:
Hi,
On 07/08/2015 07:51 AM, ankitprasad.r.sha...@intel.com wrote:
From: Rodrigo Vivi rodrigo.vivi at intel.com
On Wed, Jul 08, 2015 at 12:24:07PM +0200, Maarten Lankhorst wrote:
Op 07-07-15 om 11:15 schreef Daniel Vetter:
Since
commit 8c7b5ccb729870e606321b3703e2c2e698c49a95
Author: Ander Conselvan de Oliveira ander.conselvan.de.olive...@intel.com
Date: Tue Apr 21 17:13:19 2015 +0300
2015-07-07 20:28 GMT-03:00 Rodrigo Vivi rodrigo.v...@intel.com:
Since flush actually means invalidate + flush we need to force psr
exit on PSR flush.
On Core platforms there is no way to do the sw tracking so we
There is no way to do the _HW_ tracking?
simulate it by fully disable psr and
v1: As per review comments from Daniel, replaced async firmware
loading with request_firmware() which will load the dmc firmware and
once firmware is loaded, dc5/dc6 register programming can be done
in the same thread.
Signed-off-by: Animesh Manna animesh.ma...@intel.com
---
On 07/08/2015 02:53 PM, Chris Wilson wrote:
On Wed, Jul 08, 2015 at 02:36:08PM +0100, Tvrtko Ursulin wrote:
On 07/08/2015 02:28 PM, Chris Wilson wrote:
On Wed, Jul 08, 2015 at 02:13:43PM +0100, Tvrtko Ursulin wrote:
Hi,
On 07/08/2015 07:51 AM, ankitprasad.r.sha...@intel.com wrote:
From:
v1: As per review comments from Daniel, removed the csr-lock
and csr-state which was used before in dmc firmware loading.
Planning to have a single async task which will responsible
for firmware loading and register programming for dc5/dc6,
so removed csr-lock and csr-state from intel_csr
v1: As per review comments from Daniel, prevented entering in
dc5/dc6 while firmware loading in process. Now register programming
for dc5/dc6 always will happen followed by firmware loading. Added
a async work which is responsible for both loading the firmware
and register programming for dc5/dc6.
As during disabling dc6 no need to check for csr firmware
loading status, so removed the assert call.(Requested by Damien.)
Signed-off-by: Animesh Manna animesh.ma...@intel.com
---
drivers/gpu/drm/i915/intel_runtime_pm.c | 1 -
1 file changed, 1 deletion(-)
diff --git
Signed-off-by: Animesh Manna animesh.ma...@intel.com
---
drivers/gpu/drm/i915/intel_csr.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_csr.c b/drivers/gpu/drm/i915/intel_csr.c
index d600640..f515d54 100644
--- a/drivers/gpu/drm/i915/intel_csr.c
Firmware loading can be optimized by setting the dmc_present flag
for the first time and later internallly stored firmware data
can be used.
Signed-off-by: Animesh Manna animesh.ma...@intel.com
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/intel_csr.c | 24
v1: Based on review comments from Daniel following changes are done.
- More focus is given for better synchronization.
- Replaced async firmware loading by using request_firmawre() call.
- Prevented entering in dc5/dc6 while firmware loading in process.
Now register programming for dc5/dc6 always
On Wed, Jul 08, 2015 at 05:51:22PM +0300, Francisco Jerez wrote:
Just a few style nits, didn't look at the actual contents...
snip
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 2a29bcc..9b17260 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++
On Wed, Jul 08, 2015 at 10:41:58AM -0300, Paulo Zanoni wrote:
2015-07-07 20:28 GMT-03:00 Rodrigo Vivi rodrigo.v...@intel.com:
This will be useful to PSR and FBC once we start making
dirty fb calls to also flush frontbuffer.
Cc: Daniel Vetter daniel.vet...@ffwll.ch
Cc: Paulo Zanoni
On Wed, Jul 08, 2015 at 03:24:08PM +0100, Tvrtko Ursulin wrote:
On 07/08/2015 02:53 PM, Chris Wilson wrote:
On Wed, Jul 08, 2015 at 02:36:08PM +0100, Tvrtko Ursulin wrote:
On 07/08/2015 02:28 PM, Chris Wilson wrote:
On Wed, Jul 08, 2015 at 02:13:43PM +0100, Tvrtko Ursulin wrote:
Hi,
2015-07-07 20:28 GMT-03:00 Rodrigo Vivi rodrigo.v...@intel.com:
Idle frames the number of identical frames needed
before panel can enter PSR.
There are some panels that requires up to minimum of 4 idle
frames available on the market. For these cases usually
VBT should be used to configure
-Original Message-
From: Chris Wilson [mailto:ch...@chris-wilson.co.uk]
Sent: Saturday, July 4, 2015 1:24 PM
To: Kristian Høgsberg
Cc: Daniel, Thomas; Belgaumkar, Vinay; intel-gfx@lists.freedesktop.org; Michal
Winiarsky; Goel, Akash
Subject: Re: [Intel-gfx] [PATCH v4] drm/i915: Add
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 6749
-Summary-
Platform Delta drm-intel-nightly Series Applied
ILK
On Wed, Jul 08, 2015 at 05:07:47PM +0530, Sonika Jindal wrote:
Writing to PCH_PORT_HOTPLUG for each interrupt is not required.
Handle it only if hpd has actually occurred like we handle other
interrupts.
v2: Make few variables local to if block (Ville)
v3: Add check for ibx/cpt both (Ville).
On Wed, Jul 08, 2015 at 12:22:58PM +0100, Michel Thierry wrote:
On 7/7/2015 9:08 PM, Chris Wilson wrote:
On Tue, Jul 07, 2015 at 04:44:30PM +0100, Michel Thierry wrote:
On 7/7/2015 4:27 PM, Chris Wilson wrote:
On Tue, Jul 07, 2015 at 04:14:59PM +0100, Michel Thierry wrote:
In a 48b world,
2015-07-07 20:28 GMT-03:00 Rodrigo Vivi rodrigo.v...@intel.com:
By Spec we should only mask memup and hotplug detection
for hardware tracking cases. However we always masked
LPSP because with power well always enabled on audio
PSR was never being activated and residency was always
zeroed.
From: Peter Antoine peter.anto...@intel.com
This change adds the programming of the MOCS registers to the gen 9+
platforms. The set of MOCS configuration entries introduced by this
patch is intended to be minimal but sufficient to cover the needs of
current userspace - i.e. a good set of
The hang checker needs to inspect whether or not the ring request list is empty
as well as if the given engine has reached or passed the most recently
submitted request. The problem with this is that the hang checker cannot grab
the struct_mutex, which is required in order to safely inspect
On 07/07/2015 20:13, Francisco Jerez wrote:
From: Peter Antoine peter.anto...@intel.com
This change adds the programming of the MOCS registers to the gen 9+
platforms. This change set programs the MOCS register values to a set
of values that are defined to be optimal.
It creates a fixed
On Wed, Jul 08, 2015 at 06:54:06PM +0530, Sivakumar Thulasimani wrote:
On 7/7/2015 5:01 PM, Daniel Vetter wrote:
On Tue, Jul 07, 2015 at 04:10:49PM +0530, Sivakumar Thulasimani wrote:
From: Thulasimani,Sivakumar sivakumar.thulasim...@intel.com
Update the hotplug documentation to explain
On Wed, Jul 08, 2015 at 03:04:45PM +, Daniel, Thomas wrote:
-Original Message-
From: Chris Wilson [mailto:ch...@chris-wilson.co.uk]
Sent: Saturday, July 4, 2015 1:24 PM
To: Kristian Høgsberg
Cc: Daniel, Thomas; Belgaumkar, Vinay; intel-gfx@lists.freedesktop.org;
Michal
We have 3 types of DMA mappings for GEM objects:
1. physically contiguous for stolen and for objects needing contiguous
memory
2. DMA-buf mappings imported via a DMA-buf attach operation
3. SG DMA mappings for shmem backed and userptr objects
For 1. and 2. the lifetime of the DMA mapping
Clearing the watermarks for all pipes/planes when updating the
watermarks for a single CRTC change seems like the wrong thing to
do here. As is, this code will update any pipe/plane watermarks
that need updating and leave the remaining set to zero. Later, the
watermark checks in check_wm_state()
After the previous patch this flag will check always clear, as it's
never set for shmem backed and userptr objects, so we can remove it.
Signed-off-by: Imre Deak imre.d...@intel.com
---
drivers/gpu/drm/i915/i915_drv.h| 2 --
drivers/gpu/drm/i915/i915_gem.c| 3 ---
Op 08-07-15 om 10:55 schreef Daniel Vetter:
On Wed, Jul 08, 2015 at 10:00:22AM +0200, Maarten Lankhorst wrote:
Op 07-07-15 om 18:43 schreef Daniel Vetter:
On Tue, Jul 07, 2015 at 05:08:34PM +0200, Maarten Lankhorst wrote:
Op 07-07-15 om 14:10 schreef Daniel Vetter:
On Tue, Jul 07, 2015 at
On Tue, Jul 07, 2015 at 03:26:06PM -0300, Paulo Zanoni wrote:
From: Paulo Zanoni paulo.r.zan...@intel.com
The poor in_dbg_master() check was the only one without a reason
string. Give it a reason string so it won't feel excluded.
Signed-off-by: Paulo Zanoni paulo.r.zan...@intel.com
---
On Wed, Jul 08, 2015 at 10:27:05AM +0100, Arun Siluvery wrote:
wa_ctx_emit() depends on the name of a local variable; if the name of that
variable is changed then we get compile errors. In this case it is unlikely
to be changed as this macro is only used in this set of functions but
Kernel
Op 08-07-15 om 19:52 schreef Daniel Vetter:
On Wed, Jul 08, 2015 at 06:35:47PM +0200, Maarten Lankhorst wrote:
Op 08-07-15 om 10:55 schreef Daniel Vetter:
On Wed, Jul 08, 2015 at 10:00:22AM +0200, Maarten Lankhorst wrote:
Op 07-07-15 om 18:43 schreef Daniel Vetter:
On Tue, Jul 07, 2015 at
On 08/07/15 17:40, Yu Dai wrote:
On 07/03/2015 07:09 AM, Mika Kuoppala wrote:
Pass around requests to carry context deeper in callchain.
Signed-off-by: Mika Kuoppala mika.kuopp...@intel.com
---
drivers/gpu/drm/i915/intel_lrc.c | 14 ++
1 file changed, 6 insertions(+), 8
On Wed, Jul 08, 2015 at 07:18:58PM +0300, Imre Deak wrote:
We have 3 types of DMA mappings for GEM objects:
1. physically contiguous for stolen and for objects needing contiguous
memory
2. DMA-buf mappings imported via a DMA-buf attach operation
3. SG DMA mappings for shmem backed and
On 07/03/2015 07:09 AM, Mika Kuoppala wrote:
Pass around requests to carry context deeper in callchain.
Signed-off-by: Mika Kuoppala mika.kuopp...@intel.com
---
drivers/gpu/drm/i915/intel_lrc.c | 14 ++
1 file changed, 6 insertions(+), 8 deletions(-)
diff --git
tree: git://anongit.freedesktop.org/drm-intel drm-intel-next-queued
head: de152b627eb3018de91ec5c5a50b38e17d80a88b
commit: de152b627eb3018de91ec5c5a50b38e17d80a88b [378/378] drm/i915: Add origin
to frontbuffer tracking flush
reproduce: make htmldocs
All warnings (new ones prefixed by ):
On Wed, Jul 08, 2015 at 05:42:17PM +0100, Michel Thierry wrote:
WARN_ON(vma-node.size != obj-base.size) ? Feel free to get the casting
right - I suck at implicit C integer conversion rules ...
-Daniel
Thanks, if there's no objections, I'll change it to:
if (WARN_ON(vma-node.size !=
On 7/8/2015 4:22 PM, Daniel Vetter wrote:
On Wed, Jul 08, 2015 at 12:22:58PM +0100, Michel Thierry wrote:
On 7/7/2015 9:08 PM, Chris Wilson wrote:
On Tue, Jul 07, 2015 at 04:44:30PM +0100, Michel Thierry wrote:
On 7/7/2015 4:27 PM, Chris Wilson wrote:
On Tue, Jul 07, 2015 at 04:14:59PM
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 6751
-Summary-
Platform Delta drm-intel-nightly Series Applied
ILK
On Wed, Jul 08, 2015 at 07:18:59PM +0300, Imre Deak wrote:
After the previous patch this flag will check always clear, as it's
never set for shmem backed and userptr objects, so we can remove it.
Signed-off-by: Imre Deak imre.d...@intel.com
Mentioned a trivial obj-get_page bugfix for
On Wed Jul 08 2015 at 18:04:44 +0100, Dave Gordon wrote:
On 08/07/15 17:40, Yu Dai wrote:
On 07/03/2015 07:09 AM, Mika Kuoppala wrote:
Pass around requests to carry context deeper in callchain.
Signed-off-by: Mika Kuoppala mika.kuopp...@intel.com
---
drivers/gpu/drm/i915/intel_lrc.c | 14
2015-07-07 20:28 GMT-03:00 Rodrigo Vivi rodrigo.v...@intel.com:
This fbdev restore mode was another corner case that was now
calling frontbuffer flip and flush and making we miss
screen updates with PSR enabled.
So let's also add the invalidate hack here while we don't have
a reliable dirty
On Wed, Jul 08, 2015 at 06:35:47PM +0200, Maarten Lankhorst wrote:
Op 08-07-15 om 10:55 schreef Daniel Vetter:
On Wed, Jul 08, 2015 at 10:00:22AM +0200, Maarten Lankhorst wrote:
Op 07-07-15 om 18:43 schreef Daniel Vetter:
On Tue, Jul 07, 2015 at 05:08:34PM +0200, Maarten Lankhorst wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
Currently we relesar the lane soft reset before lane stagger settings
have been programmed. I believe that means we don't actually do lane
staggering. So move the soft reset deassert to happen after lane
staggering has been programmed.
The one
From: Ville Syrjälä ville.syrj...@linux.intel.com
Add some checks that the state of the DPIO lanes is more or less what we
expect based on the overrides.
The hardware only provides two bits per channel indicating whether all
or some of the lanes are powered down, so we can't do an exact check.
On Wed, Jul 08, 2015 at 08:25:07PM +0200, Maarten Lankhorst wrote:
Op 08-07-15 om 19:52 schreef Daniel Vetter:
On Wed, Jul 08, 2015 at 06:35:47PM +0200, Maarten Lankhorst wrote:
Op 08-07-15 om 10:55 schreef Daniel Vetter:
On Wed, Jul 08, 2015 at 10:00:22AM +0200, Maarten Lankhorst wrote:
From: Paulo Zanoni paulo.r.zan...@intel.com
Serve these while the others are still baking.
Paulo Zanoni (6):
drm/i915: make sure we're not changing the FBC CFB with FBC enabled
drm/i915: fix the FBC work allocation failure path
drm/i915: fix FBC for cases where crtc-base.y is non-zero
From: Paulo Zanoni paulo.r.zan...@intel.com
We used to have this bug in the past, but now that we properly track
the size of the CFB, we don't have it anymore. Still, add the WARN
just to make sure we don't go back to the bad state.
Signed-off-by: Paulo Zanoni paulo.r.zan...@intel.com
---
From: Paulo Zanoni paulo.r.zan...@intel.com
We were forgetting to set fbc.crtc, fbc.fb_id and fbc.y when the
kzalloc call failed. Luckily, this is not a very common case, I hope.
Signed-off-by: Paulo Zanoni paulo.r.zan...@intel.com
---
drivers/gpu/drm/i915/intel_fbc.c | 27
From: Paulo Zanoni paulo.r.zan...@intel.com
The doc is pretty clear that this register should be set to 0 on SNB.
We already write y_offset to DPFC_CPU_FENCE_OFFSET a few lines below.
Signed-off-by: Paulo Zanoni paulo.r.zan...@intel.com
---
drivers/gpu/drm/i915/intel_fbc.c | 7 ++-
1 file
From: Paulo Zanoni paulo.r.zan...@intel.com
I only tested this on BDW, but since the register description is the
same ever since gen4, let's assume that all gens take the same
register format. If that's not true, then hopefully someone will
bisect a bug to this patch and we'll fix it.
Notice
From: Paulo Zanoni paulo.r.zan...@intel.com
I could only find the restrictions for HSW+, but I think it's safe to
assume that the older platforms also can't support the configurations
HSW can't support. The older platforms probably have additional
restrictions, so we need to figure out those and
From: Paulo Zanoni paulo.r.zan...@intel.com
Keep searching in case the candidate has a NULL primary fb. This is
only relevant for the platforms that don't have the pipe_a_only
restriction.
Signed-off-by: Paulo Zanoni paulo.r.zan...@intel.com
---
drivers/gpu/drm/i915/intel_fbc.c | 6 ++
1
From: Paulo Zanoni paulo.r.zan...@intel.com
Reported by the kbuild test robot.
Regression introduced by:
commit de152b627eb3018de91ec5c5a50b38e17d80a88b
Author: Rodrigo Vivi rodrigo.v...@intel.com
Date: Tue Jul 7 16:28:51 2015 -0700
drm/i915: Add origin to frontbuffer tracking flush
(I
From: Paulo Zanoni paulo.r.zan...@intel.com
Reported by the kbuild test robot.
Regression introduced by:
commit fdbff9282c0f5f61ffc87d57461b04d943250910
Author: Daniel Vetter daniel.vet...@ffwll.ch
Date: Thu Jun 18 11:23:24 2015 +0200
drm/i915: Clear fb_tracking.busy_bits also for
From: Paulo Zanoni paulo.r.zan...@intel.com
So make it static.
Signed-off-by: Paulo Zanoni paulo.r.zan...@intel.com
---
drivers/gpu/drm/i915/intel_drv.h | 3 ---
drivers/gpu/drm/i915/intel_frontbuffer.c | 6 +++---
2 files changed, 3 insertions(+), 6 deletions(-)
diff --git
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