Re: [Intel-gfx] [PATCH 3/3] drm/i915: Remove unused "valid" parameter from pte_encode

On ti, 2016-10-04 at 15:54 +0200, Michał Winiarski wrote: > We're no longer using any invalid PTEs - everything that's not used > should be pointing to scratch. > > Cc: Chris Wilson > Cc: Joonas Lahtinen > Cc: Michel Thierry

Re: [Intel-gfx] [PATCH 1/3] drm/i915/gtt: Split gen8_ppgtt_clear_pte_range

I wonder if GCC is doing the right thing, do we have some benchmark for this, Chris, Mika? The code is much more readable in my eyes after the changes. On ti, 2016-10-04 at 15:54 +0200, Michał Winiarski wrote: > +static void gen8_ppgtt_clear_pt(struct i915_address_space *vm, > +

Re: [Intel-gfx] [PATCH v3] drm/i915/bxt: Broxton decoupled MMIO

Thanks Chris for the review. Will fix these and resend. ~Praveen On Wednesday 05 October 2016 01:26 AM, Chris Wilson wrote: On Tue, Oct 04, 2016 at 09:16:06PM +0530, Praveen Paneri wrote: +#define HAS_DECOUPLED_MMIO(dev) (INTEL_INFO(dev)->has_decoupled_mmio \ + &&

[Intel-gfx] No HW acceleration for HDPI scaling

Hello, I've recently tried to combine HD display with laptop HDPI display (1920x1200 + 3200x1800) I've tried to follow this instruction https://wiki.archlinux.org/index.php/HiDPI#Side_display And final script looks like this xrandr --output DP1 --scale 2x2 --mode 1920x1200 --fb 3840x4200 --pos

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [CI,1/8] drm/i915: Share the computation of ring size for RING_CTL register

== Series Details == Series: series starting with [CI,1/8] drm/i915: Share the computation of ring size for RING_CTL register URL : https://patchwork.freedesktop.org/series/13295/ State : success == Summary == Series 13295v1 Series without cover letter

[Intel-gfx] [CI 2/8] drm/i915/execlists: Reinitialise context image after GPU hang

On Braswell, at least, we observe that the context image is written in multiple phases. The first phase is to clear the register state, and subsequently rewrite it. A GPU reset at the right moment can interrupt the context update leaving it corrupt, and our update of the RING_HEAD is not

[Intel-gfx] [CI 5/8] drm/i915: Double check hangcheck.seqno after reset

Check that there was not a late recovery between us declaring the GPU hung and processing the reset. If the GPU did recover by itself, let the request remain on the active list and see if it hangs again! Signed-off-by: Chris Wilson Cc: Mika Kuoppala

[Intel-gfx] [CI 7/8] drm/i915: Show RING registers through debugfs

Knowing where the RINGs are pointing is extremely useful in diagnosing if the engines are executing the ringbuffers you expect - and igt may be suppressing the usual method of looking in the GPU error state. Signed-off-by: Chris Wilson Cc: Mika Kuoppala

[Intel-gfx] [CI 8/8] drm/i915: Show waiters in i915_hangcheck_info

It is convenient to know what processes are waiting when looking at hangcheck status in debugfs. Signed-off-by: Chris Wilson Reviewed-by: Mika Kuoppala --- drivers/gpu/drm/i915/i915_debugfs.c | 12 1 file changed, 12 insertions(+)

[Intel-gfx] [CI 3/8] drm/i915/execlists: Move clearing submission count from reset to init

After a GPU reset, we want to replay our queue of requests. However, the GPU reset clobbered the state and we only fixup the state for the guilty request - and engines deemed innocent we try to leave untouched so that we recover as completely as possible. However, we need to clear the sw tracking

[Intel-gfx] [CI 1/8] drm/i915: Share the computation of ring size for RING_CTL register

Since both legacy and execlists want to populate the RING_CTL register, share the computation of the right bits for the ring->size. We can then stop masking errors and explicitly forbid them during creation! Signed-off-by: Chris Wilson Cc: Mika Kuoppala

[Intel-gfx] [CI 6/8] drm/i915: Show bounds of active request in the ring on GPU hang

Include the position of the active request in the ring, and display that alongside the current RING registers (on a GPU hang). Signed-off-by: Chris Wilson Cc: Mika Kuoppala Reviewed-by: Mika Kuoppala ---

[Intel-gfx] [CI 4/8] drm/i915: Disable irqs across GPU reset

Whilst we reset the GPU, we want to prevent execlists from submitting new work (which it does via an interrupt handler). To achieve this we disable the irq (and drain the irq tasklet) around the reset. When we enable it again afters, the interrupt queue should be empty and we can reinitialise from

Re: [Intel-gfx] [PATCH v3] drm/i915/bxt: Broxton decoupled MMIO

On Tue, Oct 04, 2016 at 09:16:06PM +0530, Praveen Paneri wrote: > +#define HAS_DECOUPLED_MMIO(dev) (INTEL_INFO(dev)->has_decoupled_mmio \ > + && IS_BXT_REVID(dev, BXT_REVID_C0, REVID_FOREVER)) Edit dev_priv->info.has_decoupled_mmio on init. > +static void

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gen9: fix DDB partitioning for multi-screen cases

== Series Details == Series: drm/i915/gen9: fix DDB partitioning for multi-screen cases URL : https://patchwork.freedesktop.org/series/13293/ State : success == Summary == Series 13293v1 drm/i915/gen9: fix DDB partitioning for multi-screen cases

Re: [Intel-gfx] [PATCH] drm/i915/gen9: fix DDB partitioning for multi-screen cases

Em Ter, 2016-10-04 às 14:37 -0300, Paulo Zanoni escreveu: > With the previous code we were only recomputing the DDB partitioning > for the CRTCs included in the atomic commit, so any other active > CRTCs > would end up having their DDB registers zeroed. In this patch we make > sure that the

Re: [Intel-gfx] [PATCH v3] drm/i915/bxt: Broxton decoupled MMIO

Is this still an embargoed feature? why? With Apollolake out there we need to work to get permission to upstream this feature already and post it to intel-gfx@lists.freedesktop.org in order to get this merged upstream. A decoupled version for BXT stayed in the internal for so long time and

[Intel-gfx] [PATCH] drm/i915/gen9: fix DDB partitioning for multi-screen cases

With the previous code we were only recomputing the DDB partitioning for the CRTCs included in the atomic commit, so any other active CRTCs would end up having their DDB registers zeroed. In this patch we make sure that the computed state starts as a copy of the current partitioning, and then we

[Intel-gfx] ✗ Fi.CI.BAT: warning for drm/i915/bxt: Broxton decoupled MMIO (rev3)

== Series Details == Series: drm/i915/bxt: Broxton decoupled MMIO (rev3) URL : https://patchwork.freedesktop.org/series/12028/ State : warning == Summary == Series 12028v3 drm/i915/bxt: Broxton decoupled MMIO https://patchwork.freedesktop.org/api/1.0/series/12028/revisions/3/mbox/ Test

[Intel-gfx] [PATCH v3] drm/i915/bxt: Broxton decoupled MMIO

Decoupled MMIO is an alternative way to access forcewake domain registers, which requires less cycles for a single read/write and avoids frequent software forcewake. This certainly gives advantage over the forcewake as this new mechanism “decouples” CPU cycles and allow them to complete even when

[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/3] drm/i915/gtt: Split gen8_ppgtt_clear_pte_range

== Series Details == Series: series starting with [1/3] drm/i915/gtt: Split gen8_ppgtt_clear_pte_range URL : https://patchwork.freedesktop.org/series/13282/ State : failure == Summary == Series 13282v1 Series without cover letter

[Intel-gfx] [PATCH] aubdump: add --command option to stream aubdump to another program

This comes handy if you want to look at your application output without having to save it into a file. For example, use this with aubinator from Mesa : $ intel_aubdump -c '/path/to/aubinator --gen=hsw' my_gl_app Signed-off-by: Lionel Landwerlin Cc: Kristian

Re: [Intel-gfx] [PATCH 1/2] drm/i915: Reduce trickery in DEV_INFO_FOR_EACH_FLAG

On Tue, 04 Oct 2016, Joonas Lahtinen wrote: > Get rid of SEP_SEMICOLON and SEP_BLANK in DEV_INFO_FOR_EACH_FLAG. > > Signed-off-by: Joonas Lahtinen > --- > drivers/gpu/drm/i915/i915_debugfs.c | 6 +- >

[Intel-gfx] [PATCH 2/3] drm/i915/gtt: Free unused lower-level page tables

Since "Dynamic page table allocations" were introduced, our page tables can grow (being dynamically allocated) with address space range usage. Unfortunately, their lifetime is bound to vm. This is not a huge problem when we're not using softpin - drm_mm is creating an upper bound on used range by

[Intel-gfx] [PATCH 1/3] drm/i915/gtt: Split gen8_ppgtt_clear_pte_range

Let's use more top-down approach, where each gen8_ppgtt_clear_* function is responsible for clearing the struct passed as an argument and calling relevant clear_range functions on lower-level tables. Doing this rather than operating on PTE ranges makes the implementation of shrinking page tables

[Intel-gfx] [PATCH 3/3] drm/i915: Remove unused "valid" parameter from pte_encode

We're no longer using any invalid PTEs - everything that's not used should be pointing to scratch. Cc: Chris Wilson Cc: Joonas Lahtinen Cc: Michel Thierry Cc: Mika Kuoppala

[Intel-gfx] ✗ Fi.CI.BAT: warning for series starting with [1/2] drm/i915: Reduce trickery in DEV_INFO_FOR_EACH_FLAG

== Series Details == Series: series starting with [1/2] drm/i915: Reduce trickery in DEV_INFO_FOR_EACH_FLAG URL : https://patchwork.freedesktop.org/series/13278/ State : warning == Summary == Series 13278v1 Series without cover letter

Re: [Intel-gfx] [PATCH 2/2] drm/i915: Sort DEV_INFO_FOR_EACH_FLAG

On Tue, Oct 04, 2016 at 03:42:58PM +0300, Joonas Lahtinen wrote: > Sort DEV_INFO_FOR_EACH_FLAG to alphabetical order (except is_*). > > Signed-off-by: Joonas Lahtinen Ok. Looks like it should be easier to read. Reviewed-by: Chris Wilson

Re: [Intel-gfx] [PATCH] drm/i915: make skl_ddb_add_affected_planes static

Reviewed-by: Lyude On Tue, 2016-10-04 at 12:29 +0300, Jani Nikula wrote: > Fix sparse warning: > > drivers/gpu/drm/i915/intel_pm.c:3970:1: warning: symbol > 'skl_ddb_add_affected_planes' was not declared. Should it be static? > > Fixes: 7f60e200e254 ("drm/i915/gen9: only add

[Intel-gfx] ✗ Fi.CI.BAT: warning for Shared DPLL kernel doc and improvements

== Series Details == Series: Shared DPLL kernel doc and improvements URL : https://patchwork.freedesktop.org/series/13277/ State : warning == Summary == Series 13277v1 Shared DPLL kernel doc and improvements https://patchwork.freedesktop.org/api/1.0/series/13277/revisions/1/mbox/ Test

Re: [Intel-gfx] [PATCH 1/2] drm/i915: Reduce trickery in DEV_INFO_FOR_EACH_FLAG

On Tue, Oct 04, 2016 at 03:42:57PM +0300, Joonas Lahtinen wrote: > #define PRINT_S(name) "%s" > -#define SEP_EMPTY > -#define PRINT_FLAG(name) info->name ? #name "," : "" > -#define SEP_COMMA , > +#define PRINT_FLAG(name) info->name ? #name "," : "", > DRM_DEBUG_DRIVER("i915 device info:

Re: [Intel-gfx] [PATCH 8/8] drm/i915: Show waiters in i915_hangcheck_info

Chris Wilson writes: > Signed-off-by: Chris Wilson With commit message stating the obvious added, Reviewed-by: Mika Kuoppala > --- > drivers/gpu/drm/i915/i915_debugfs.c | 12 > 1 file changed, 12

Re: [Intel-gfx] [PATCH 7/8] drm/i915: Show RING registers through debugfs

On Tue, Oct 04, 2016 at 03:35:20PM +0300, Mika Kuoppala wrote: > Chris Wilson writes: > > + rcu_read_unlock(); > > + > > + addr = intel_engine_get_active_head(engine); > > + seq_printf(m, "\tACTHD: 0x%08x_%08x\n", > > +

Re: [Intel-gfx] [PATCH 8/8] drm/i915: Show waiters in i915_hangcheck_info

On Tue, Oct 04, 2016 at 03:41:24PM +0300, Mika Kuoppala wrote: > Chris Wilson writes: > > The commit message is missing. > > > Signed-off-by: Chris Wilson > > --- > > drivers/gpu/drm/i915/i915_debugfs.c | 12 > > 1 file changed,

Re: [Intel-gfx] [PATCH 1/8] drm/i915: Share the computation of ring size for RING_CTL register

Chris Wilson writes: > On Mon, Oct 03, 2016 at 01:52:39PM +0100, Chris Wilson wrote: >> Since both legacy and execlists want to poopulate the RING_CTL register, >> share the computation of the right bits for the ring->size. We can then >> stop masking errors and

[Intel-gfx] [PATCH 2/2] drm/i915: Sort DEV_INFO_FOR_EACH_FLAG

Sort DEV_INFO_FOR_EACH_FLAG to alphabetical order (except is_*). Signed-off-by: Joonas Lahtinen --- drivers/gpu/drm/i915/i915_drv.h | 36 ++-- 1 file changed, 18 insertions(+), 18 deletions(-) diff --git

[Intel-gfx] [PATCH 1/2] drm/i915: Reduce trickery in DEV_INFO_FOR_EACH_FLAG

Get rid of SEP_SEMICOLON and SEP_BLANK in DEV_INFO_FOR_EACH_FLAG. Signed-off-by: Joonas Lahtinen --- drivers/gpu/drm/i915/i915_debugfs.c | 6 +- drivers/gpu/drm/i915/i915_drv.h | 98 +++-

Re: [Intel-gfx] [PATCH 8/8] drm/i915: Show waiters in i915_hangcheck_info

Chris Wilson writes: The commit message is missing. > Signed-off-by: Chris Wilson > --- > drivers/gpu/drm/i915/i915_debugfs.c | 12 > 1 file changed, 12 insertions(+) > > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c >

Re: [Intel-gfx] [PATCH 7/8] drm/i915: Show RING registers through debugfs

Chris Wilson writes: > Knowing where the RINGs are pointing is extremely useful in diagnosing > if the engines are executing the ringbuffers you expect - and igt may be > suppressing the usual method of looking in the GPU error state. > > Signed-off-by: Chris Wilson

[Intel-gfx] [PATCH 7/7] drm/i915: Add entrypoints for mapping dplls to encoders and crtcs

Abstract the platform specific bits of mapping the dplls under a platform independ entrypoints so the differences between platforms are contained in the dpll code. I.e., it removes IS_PLATFORM() macros from other parts of the code. Signed-off-by: Ander Conselvan de Oliveira

[Intel-gfx] [PATCH 4/7] drm/i915: Rename intel_shared_dpll->mode_set() to prepare()

The hook is called from intel_prepare_shared_dpll(). The name doesn't make sense after all the changes to modeset code. So just call it prepare. Signed-off-by: Ander Conselvan de Oliveira Reviewed-by: Durgadoss R ---

[Intel-gfx] [PATCH 6/7] drm/i915: Add dpll entrypoint for dumping hw state

Remove the IS_PLATFORM() macros from intel_dump_pipe_config() and split that logic in platform specific implementations inside the dpll code, accessed through a platform independent interface. Signed-off-by: Ander Conselvan de Oliveira ---

[Intel-gfx] [PATCH 5/7] drm/i915: Update kerneldoc for intel_dpll_mgr.c

The documentation for most of the non-static members and structs were missing. Fix that. v2: Fix typos (Durga) v3: Rebase. Fix make docs warnings. Document more. Signed-off-by: Ander Conselvan de Oliveira --- Documentation/gpu/i915.rst

[Intel-gfx] [PATCH 2/7] drm/i915: Rename intel_shared_dpll_commit() to _swap_state()

The function intel_shared_dpll_commit() performs the equivalent of drm_atomic_helper_swap_state() for the shared dpll state, which is not handled by the helpers. So rename it for consistency. v2: Fix typo in the commit message. (Durga) v3: Rebase. Signed-off-by: Ander Conselvan de Oliveira

[Intel-gfx] [PATCH 3/7] drm/i915: Rename intel_shared_dpll_config to intel_shared_dpll_state

Struct intel_shared_dpll_config is used to hold the state of the DPLL in the "atomic" sense, so call it state like everything else atomic. Signed-off-by: Ander Conselvan de Oliveira --- drivers/gpu/drm/i915/i915_debugfs.c | 12 +++

[Intel-gfx] [PATCH 0/7] Shared DPLL kernel doc and improvements

Hi, This is a resend of some previous patches adding documentation to the shared dpll stuff, which I didn't merge since the first patch still lacks review, plus some more changes on top to make the interface more self contained. Thanks, Ander Ander Conselvan de Oliveira (7): drm/i915:

[Intel-gfx] [PATCH 1/7] drm/i915: Introduce intel_release_shared_dpll()

While the details of getting a shared dpll are wrapped by intel_get_shared_dpll(), the release was still hand rolled into the modeset code. Fix that by creating an entry point for releasing the pll and move that code there. v2: Take old_dpll from crtc->state instead of crtc_state. (CI)

Re: [Intel-gfx] [PATCH 6/8] drm/i915: Show bounds of active request in the ring on GPU hang

Chris Wilson writes: > Include the position of the active request in the ring, and display that > alongside the current RING registers (on a GPU hang). > > Signed-off-by: Chris Wilson Reviewed-by: Mika Kuoppala >

[Intel-gfx] ✗ Fi.CI.BAT: warning for series starting with [RESEND,1/2] drm/i915: workaround sparse warning on variable length arrays

== Series Details == Series: series starting with [RESEND,1/2] drm/i915: workaround sparse warning on variable length arrays URL : https://patchwork.freedesktop.org/series/13269/ State : warning == Summary == Series 13269v1 Series without cover letter

Re: [Intel-gfx] [PATCH] drm/i915: make skl_ddb_add_affected_planes static

On Tue, 04 Oct 2016, Joonas Lahtinen wrote: > On ti, 2016-10-04 at 12:29 +0300, Jani Nikula wrote: >> Fix sparse warning: >> >> drivers/gpu/drm/i915/intel_pm.c:3970:1: warning: symbol >> 'skl_ddb_add_affected_planes' was not declared. Should it be static? >> >>

Re: [Intel-gfx] [PATCH] drm/i915: make skl_ddb_add_affected_planes static

On ti, 2016-10-04 at 12:29 +0300, Jani Nikula wrote: > Fix sparse warning: > > drivers/gpu/drm/i915/intel_pm.c:3970:1: warning: symbol > 'skl_ddb_add_affected_planes' was not declared. Should it be static? > > Fixes: 7f60e200e254 ("drm/i915/gen9: only add the planes actually affected by > ddb

[Intel-gfx] ✗ Fi.CI.BAT: warning for drm/i915: make skl_ddb_add_affected_planes static

== Series Details == Series: drm/i915: make skl_ddb_add_affected_planes static URL : https://patchwork.freedesktop.org/series/13267/ State : warning == Summary == Series 13267v1 drm/i915: make skl_ddb_add_affected_planes static

Re: [Intel-gfx] ✗ Fi.CI.BAT: warning for Forcewake binary search & code shrink (rev6)

On 04/10/2016 10:37, Joonas Lahtinen wrote: On ti, 2016-10-04 at 10:18 +0100, Tvrtko Ursulin wrote: Joonas what do you think, worth merging on balance? +1 on merging. Pushed to dinq, first one from the new office. :) Thanks for the review guys! Regards, Tvrtko

Re: [Intel-gfx] [PATCH RESEND 2/2] drm/i915: silence io mapping/unmapping sparse warnings on different address spaces

On ti, 2016-10-04 at 12:54 +0300, Jani Nikula wrote: > drivers/gpu/drm/i915/i915_gem_execbuffer.c:432:52: warning: incorrect type in > argument 1 (different address spaces) > drivers/gpu/drm/i915/i915_gem_execbuffer.c:432:52:expected void [noderef] > *vaddr >

Re: [Intel-gfx] [PATCH RESEND 1/2] drm/i915: workaround sparse warning on variable length arrays

On Tue, 04 Oct 2016, Joonas Lahtinen wrote: > On ti, 2016-10-04 at 12:54 +0300, Jani Nikula wrote: >> @@ -192,7 +192,7 @@ static void broadwell_sseu_info_init(struct >> drm_i915_private *dev_priv) >>  struct sseu_dev_info *sseu = _device_info(dev_priv)->sseu;

Re: [Intel-gfx] [PATCH RESEND 1/2] drm/i915: workaround sparse warning on variable length arrays

On ti, 2016-10-04 at 12:54 +0300, Jani Nikula wrote: > @@ -192,7 +192,7 @@ static void broadwell_sseu_info_init(struct > drm_i915_private *dev_priv) >   struct sseu_dev_info *sseu = _device_info(dev_priv)->sseu; >   const int s_max = 3, ss_max = 3, eu_max = 8; Does sparse shut up if you

[Intel-gfx] [PATCH RESEND 2/2] drm/i915: silence io mapping/unmapping sparse warnings on different address spaces

drivers/gpu/drm/i915/i915_gem_execbuffer.c:432:52: warning: incorrect type in argument 1 (different address spaces) drivers/gpu/drm/i915/i915_gem_execbuffer.c:432:52:expected void [noderef] *vaddr drivers/gpu/drm/i915/i915_gem_execbuffer.c:432:52:got void *

[Intel-gfx] [PATCH RESEND 1/2] drm/i915: workaround sparse warning on variable length arrays

Fix sparse warning: drivers/gpu/drm/i915/intel_device_info.c:195:31: warning: Variable length array is used. In truth the array does have constant length, but sparse is too dumb to realize. This is a bit ugly, but silence the warning no matter what. Fixes: 91bedd34abf0 ("drm/i915/bdw: Check for

Re: [Intel-gfx] ✗ Fi.CI.BAT: warning for Forcewake binary search & code shrink (rev6)

On ti, 2016-10-04 at 10:18 +0100, Tvrtko Ursulin wrote: >  > Joonas what do you think, worth merging on balance? >  +1 on merging. Regards, Joonas --  Joonas Lahtinen Open Source Technology Center Intel Corporation ___ Intel-gfx mailing list

[Intel-gfx] [PATCH] drm/i915: make skl_ddb_add_affected_planes static

Fix sparse warning: drivers/gpu/drm/i915/intel_pm.c:3970:1: warning: symbol 'skl_ddb_add_affected_planes' was not declared. Should it be static? Fixes: 7f60e200e254 ("drm/i915/gen9: only add the planes actually affected by ddb changes") Cc: Lyude Cc: Paulo Zanoni

[Intel-gfx] ✗ Fi.CI.BAT: warning for drm/dp/i915: Enable audio codec after the HDA audio driver is initialized

== Series Details == Series: drm/dp/i915: Enable audio codec after the HDA audio driver is initialized URL : https://patchwork.freedesktop.org/series/13265/ State : warning == Summary == Series 13265v1 drm/dp/i915: Enable audio codec after the HDA audio driver is initialized

Re: [Intel-gfx] [PATCH] drm/i915: keep CONFIG_DRM_FBDEV_EMULATION=n function stubs together

On Tue, 04 Oct 2016, Chris Wilson wrote: > On Tue, Oct 04, 2016 at 10:53:48AM +0300, Jani Nikula wrote: >> Move the outcast intel_fbdev_output_poll_changed() stub for >> CONFIG_DRM_FBDEV_EMULATION=n next to its friends. >> >> Signed-off-by: Jani Nikula

Re: [Intel-gfx] ✗ Fi.CI.BAT: warning for Forcewake binary search & code shrink (rev6)

On 04/10/2016 09:55, Chris Wilson wrote: On Tue, Oct 04, 2016 at 09:46:50AM +0100, Tvrtko Ursulin wrote: On 03/10/2016 10:27, Patchwork wrote: fi-bdw-5557u total:236 pass:220 dwarn:0 dfail:0 fail:0 skip:15 fi-bxt-t5700 total:236 pass:205 dwarn:0 dfail:0 fail:0 skip:30

Re: [Intel-gfx] ✗ Fi.CI.BAT: warning for Forcewake binary search & code shrink (rev6)

On Tue, Oct 04, 2016 at 09:46:50AM +0100, Tvrtko Ursulin wrote: > On 03/10/2016 10:27, Patchwork wrote: > >fi-bdw-5557u total:236 pass:220 dwarn:0 dfail:0 fail:0 skip:15 > >fi-bxt-t5700 total:236 pass:205 dwarn:0 dfail:0 fail:0 skip:30 > >fi-byt-j1900 total:236

Re: [Intel-gfx] ✗ Fi.CI.BAT: warning for Forcewake binary search & code shrink (rev6)

On 03/10/2016 10:27, Patchwork wrote: == Series Details == Series: Forcewake binary search & code shrink (rev6) URL : https://patchwork.freedesktop.org/series/13080/ State : warning == Summary == Series 13080v6 Forcewake binary search & code shrink

[Intel-gfx] [PATCH] drm/dp/i915: Enable audio codec after the HDA audio driver is initialized

This fixes the underruns that are seen in DP MST multi-monitor setups when audio is enabled with commit 3708d5e082c3 ("drm/i915: start adding dp mst audio"). The underruns triggered continuous cycles of display on/off cycles. Signed-off-by: Dhinakaran Pandiyan Cc:

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: keep CONFIG_DRM_FBDEV_EMULATION=n function stubs together

== Series Details == Series: drm/i915: keep CONFIG_DRM_FBDEV_EMULATION=n function stubs together URL : https://patchwork.freedesktop.org/series/13262/ State : success == Summary == Series 13262v1 drm/i915: keep CONFIG_DRM_FBDEV_EMULATION=n function stubs together

Re: [Intel-gfx] [PATCH] drm/i915: keep CONFIG_DRM_FBDEV_EMULATION=n function stubs together

On Tue, Oct 04, 2016 at 10:53:48AM +0300, Jani Nikula wrote: > Move the outcast intel_fbdev_output_poll_changed() stub for > CONFIG_DRM_FBDEV_EMULATION=n next to its friends. > > Signed-off-by: Jani Nikula Reviewed-by: Chris Wilson -Chris --

[Intel-gfx] [PATCH] drm/i915: keep CONFIG_DRM_FBDEV_EMULATION=n function stubs together

Move the outcast intel_fbdev_output_poll_changed() stub for CONFIG_DRM_FBDEV_EMULATION=n next to its friends. Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/intel_display.c | 6 -- drivers/gpu/drm/i915/intel_drv.h | 4 2 files changed, 4 insertions(+), 6

Re: [Intel-gfx] [PATCH 2/2] drm/i915: KBL - Recommended buffer translation programming for DisplayPort

On Tue, 04 Oct 2016, "Vivi, Rodrigo" wrote: > On Mon, 2016-10-03 at 13:50 +0300, Jani Nikula wrote: >> On Fri, 30 Sep 2016, Rodrigo Vivi wrote: >> > According to spec: "KBL re-uses SKL values, except where >> > specific KBL values are listed." >> >