[Intel-gfx] ✗ Fi.CI.BAT: failure for Gen8+ engine-reset

== Series Details == Series: Gen8+ engine-reset URL : https://patchwork.freedesktop.org/series/21868/ State : failure == Summary == Series 21868v1 Gen8+ engine-reset https://patchwork.freedesktop.org/api/1.0/series/21868/revisions/1/mbox/ Test pm_rpm: Subgroup basic-rte:

[Intel-gfx] [PATCH v5 13/18] drm/i915/guc: Add support for reset engine using GuC commands

This patch adds per engine reset and recovery (TDR) support when GuC is used to submit workloads to GPU. In the case of i915 directly submission to ELSP, driver manages hang detection, recovery and resubmission. With GuC submission these tasks are shared between driver and GuC. i915 is still

[Intel-gfx] [PATCH v5 07/18] drm/i915/tdr: Add engine reset count to error state

From: Arun Siluvery Driver maintains count of how many times a given engine is reset, useful to capture this in error state also. It gives an idea of how engine is coping up with the workloads it is executing before this error state. A follow-up patch will provide

[Intel-gfx] [PATCH v5 11/18] drm/i915/selftests: reset engine self tests

Check that we can reset specific engines, also check the fallback to full reset if something didn't work. Signed-off-by: Michel Thierry --- drivers/gpu/drm/i915/selftests/intel_hangcheck.c | 144 +++ 1 file changed, 144 insertions(+) diff --git

[Intel-gfx] [PATCH v5 00/18] Gen8+ engine-reset

These patches add the reset-engine feature from Gen8. This is also referred to as Timeout detection and recovery (TDR). This complements to the full gpu reset feature available in i915 but it only allows to reset a particular engine instead of all engines thus providing a light weight engine reset

[Intel-gfx] [PATCH v5 01/18] drm/i915: Fix stale comment about I915_RESET_IN_PROGRESS flag

It has been replaced by I915_RESET_BACKOFF / I915_RESET_HANDOFF. Signed-off-by: Michel Thierry --- drivers/gpu/drm/i915/i915_drv.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h

[Intel-gfx] [PATCH v5 03/18] drm/i915: Update i915.reset to handle engine resets

From: Arun Siluvery In preparation for engine reset work update this parameter to handle more than one type of reset. Default at the moment is still full gpu reset. Cc: Chris Wilson Cc: Mika Kuoppala

[Intel-gfx] [PATCH v5 16/18] drm/i915: Watchdog timeout: Ringbuffer command emission for gen8+

Emit the required commands into the ring buffer for starting and stopping the watchdog timer before/after batch buffer start during batch buffer submission. v2: Support watchdog threshold per context engine, merge lri commands, and move watchdog commands emission to emit_bb_start. Request space

[Intel-gfx] [PATCH v5 17/18] drm/i915: Watchdog timeout: DRM kernel interface to set the timeout

Final enablement patch for GPU hang detection using watchdog timeout. Using the gem_context_setparam ioctl, users can specify the desired timeout value in microseconds, and the driver will do the conversion to 'timestamps'. The recommended default watchdog threshold for video engines is 6 us,

[Intel-gfx] [PATCH v5 05/18] drm/i915/tdr: Add support for per engine reset recovery

From: Arun Siluvery This change implements support for per-engine reset as an initial, less intrusive hang recovery option to be attempted before falling back to the legacy full GPU reset recovery mode if necessary. This is only supported from Gen8 onwards.

[Intel-gfx] [PATCH v5 10/18] drm/i915: Add engine reset count in get-reset-stats ioctl

Users/tests relying on the total reset count will start seeing a smaller number since most of the hangs can be handled by engine reset. Note that if reset engine x, context a running on engine y will be unaware and unaffected. To start the discussion, include just a total engine reset count. If

[Intel-gfx] [PATCH v5 08/18] drm/i915/tdr: Export per-engine reset count info to debugfs

From: Arun Siluvery A new variable is added to export the reset counts to debugfs, this includes full gpu reset and engine reset count. This is useful for tests where they are expected to trigger reset; these counts are checked before and after the test to ensure

[Intel-gfx] [PATCH v5 09/18] drm/i915/tdr: Enable Engine reset and recovery support

From: Arun Siluvery This feature is made available only from Gen8, for previous gen devices driver uses legacy full gpu reset. Cc: Chris Wilson Cc: Mika Kuoppala Signed-off-by: Tomas Elf

[Intel-gfx] [PATCH v5 02/18] drm/i915: Rename gen8_(un)request_engine_reset to gen8_(un)request_reset_engine

As all other functions related to resetting engines are using reset_engine. Signed-off-by: Michel Thierry --- drivers/gpu/drm/i915/intel_uncore.c | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_uncore.c

[Intel-gfx] [PATCH v5 12/18] drm/i915/guc: Provide register list to be saved/restored during engine reset

From: Arun Siluvery GuC expects a list of registers from the driver which are saved/restored during engine reset. The type of value to be saved is controlled by flags. We provide a minimal set of registers that we want GuC to save and restore. This is not an issue

[Intel-gfx] [PATCH v5 06/18] drm/i915: Skip reset request if there is one already

From: Mika Kuoppala To perform engine reset we first disable engine to capture its state. This is done by issuing a reset request. Because we are reusing existing infrastructure, again when we actually reset an engine, reset function checks engine mask and issues

[Intel-gfx] [PATCH v5 18/18] drm/i915: Watchdog timeout: Export media reset count from GuC to debugfs

From firmware v8.8, GuC provides the count of media engine resets (watchdog timeout). This information is available in the GuC shared context data struct, which resides in the first page of the default (kernel) lrc context. Since GuC handled engine resets are transparent for kernel and user,

[Intel-gfx] [PATCH v5 15/18] drm/i915: Watchdog timeout: IRQ handler for gen8+

*** General *** Watchdog timeout (or "media engine reset") is a feature that allows userland applications to enable hang detection on individual batch buffers. The detection mechanism itself is mostly bound to the hardware and the only thing that the driver needs to do to support this form of

[Intel-gfx] [PATCH v5 14/18] drm/i915: Watchdog timeout: Pass GuC shared data structure during param load

For watchdog / media reset, the firmware must know the address of the shared data page (the first page of the default context). This information should be in DWORD 9 of the GUC_CTL structure. Signed-off-by: Michel Thierry --- drivers/gpu/drm/i915/intel_guc_fwif.h |

[Intel-gfx] [PATCH v5 04/18] drm/i915/tdr: Modify error handler for per engine hang recovery

From: Arun Siluvery This is a preparatory patch which modifies error handler to do per engine hang recovery. The actual patch which implements this sequence follows later in the series. The aim is to prepare existing recovery function to adapt to this new function

[Intel-gfx] [Regression report] Weekly regression report WW12

Link to FDO regression list:

[Intel-gfx] [PATCH] aubdump: Don't bail if a GEM handle of 0 is passed into execbuf

A gem handle of 0 can be used to check for whether or not 48-bit addressing is available. This keeps aubdump from failing on you if you try to do the check. --- tools/aubdump.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/tools/aubdump.c b/tools/aubdump.c index

Re: [Intel-gfx] [PATCH 08/16] drm: document drm_ioctl.[hc]

Hi Daniel, [auto build test WARNING on drm/drm-next] [cannot apply to v4.11-rc3 next-20170324] [if your patch is applied to the wrong git tree, please drop us a note to help improve the system] url: https://github.com/0day-ci/linux/commits/Daniel-Vetter/more-drmP-h-cleanup/20170325-030940

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915: Use LINEAR modifier instead of NONE

== Series Details == Series: series starting with [1/3] drm/i915: Use LINEAR modifier instead of NONE URL : https://patchwork.freedesktop.org/series/21854/ State : success == Summary == Series 21854v1 Series without cover letter

[Intel-gfx] [PATCH 1/3] drm/i915: Use LINEAR modifier instead of NONE

They're the same, so use the one which makes more sense. Signed-off-by: Ben Widawsky --- drivers/gpu/drm/i915/intel_display.c | 28 ++-- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c

[Intel-gfx] [PATCH 2/3] drm: Add new DRM_IOCTL_MODE_GETPLANE2

Originally based off of a patch by Kristian. This new ioctl extends DRM_IOCTL_MODE_GETPLANE, by returning information about the modifiers that will work with each format. It's modified from Kristian's patch in that the modifiers and formats are setup by the driver, and then a callback is used to

[Intel-gfx] [PATCH 3/3] drm/i915: Add format modifiers for Intel

This was based on a patch originally by Kristian. It has been modified pretty heavily to use the new callbacks from the previous patch. v2: - Add LINEAR and Yf modifiers to list (Ville) - Combine i8xx and i965 into one list of formats (Ville) - Allow 1010102 formats for Y/Yf tiled (Ville)

Re: [Intel-gfx] [PATCH 15/16] drm/vblank: Simplify the get_scanout_position helper hook

Hi Daniel, [auto build test WARNING on drm/drm-next] [cannot apply to v4.11-rc3 next-20170324] [if your patch is applied to the wrong git tree, please drop us a note to help improve the system] url: https://github.com/0day-ci/linux/commits/Daniel-Vetter/more-drmP-h-cleanup/20170325-030940

[Intel-gfx] [PATCH] drm/vblank: fix boolreturn.cocci warnings

drivers/gpu/drm/nouveau/nouveau_display.c:154:8-9: WARNING: return of 0/1 in function 'nouveau_display_scanoutpos' with return type bool Return statements in functions returning bool should use true/false instead of 1/0. Generated by: scripts/coccinelle/misc/boolreturn.cocci CC: Daniel Vetter

Re: [Intel-gfx] [PATCH 1/3] drm/i915: Fixup intel_write_status_page() for old CPUs without clflush

On Fri, Mar 24, 2017 at 09:04:45PM +, Chris Wilson wrote: > On Fri, Mar 24, 2017 at 10:53:18PM +0200, Ville Syrjälä wrote: > > On Fri, Mar 24, 2017 at 09:05:13PM +0200, Ville Syrjälä wrote: > > > Unfortunately the GPU still dies as soon as I fire up glxgears. 4.9 > > > seems to be working just

Re: [Intel-gfx] [PATCH 1/3] drm/i915: Fixup intel_write_status_page() for old CPUs without clflush

On Fri, Mar 24, 2017 at 10:53:18PM +0200, Ville Syrjälä wrote: > On Fri, Mar 24, 2017 at 09:05:13PM +0200, Ville Syrjälä wrote: > > Unfortunately the GPU still dies as soon as I fire up glxgears. 4.9 > > seems to be working just fine, so looks like a kernel regression. > > And bisected down to >

Re: [Intel-gfx] [PATCH 1/3] drm/i915: Fixup intel_write_status_page() for old CPUs without clflush

On Fri, Mar 24, 2017 at 09:05:13PM +0200, Ville Syrjälä wrote: > On Fri, Mar 24, 2017 at 04:35:38PM +, Chris Wilson wrote: > > Note all of our target platforms have clflush. For those without, just > > assume the status page is sufficiently coherent that we do not need our > > paranoia. > > >

Re: [Intel-gfx] [PATCH v10 3/6] drm/edid: detect SCDC support in HF-VSDB

On Mon, Mar 13, 2017 at 12:24 PM, Shashank Sharma wrote: > +/** > + * struct drm_hdmi_info - runtime information about the connected HDMI sink > + * > + * Describes if a given display supports advanced HDMI 2.0 features. > + * This information is available in CEA-861-F

Re: [Intel-gfx] [PATCH 1/3] drm/i915: Fixup intel_write_status_page() for old CPUs without clflush

On Fri, Mar 24, 2017 at 04:35:38PM +, Chris Wilson wrote: > Note all of our target platforms have clflush. For those without, just > assume the status page is sufficiently coherent that we do not need our > paranoia. > > Reported-by: Ville Syrjälä > Fixes:

Re: [Intel-gfx] [PATCH] drm/i915: Reduce Data Link N value for 1 lane DP->hdmi converters

On 03/24/2017 04:25 AM, Jani Nikula wrote: On Thu, 23 Mar 2017, Clint Taylor wrote: I would prefer a solution for B (rules for M/N), but the code doesn't appear to be broken and I don't believe we should "Fix" something that is working. The device also works by

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v2] drm: Make the decision to keep vblank irq enabled earlier (rev3)

== Series Details == Series: series starting with [v2] drm: Make the decision to keep vblank irq enabled earlier (rev3) URL : https://patchwork.freedesktop.org/series/21318/ State : success == Summary == Series 21318v3 Series without cover letter

[Intel-gfx] [PATCH v2] drm: Make the decision to keep vblank irq enabled earlier

We want to provide the vblank irq shadow for pageflip events as well as vblank queries. Such events are completed within the vblank interrupt handler, and so the current check for disabling the irq will disable it from with the same interrupt as the last pageflip event. If we move the decision on

Re: [Intel-gfx] [PATCH] drm: Make the decision to keep vblank irq enabled earlier

On Fri, Mar 24, 2017 at 04:16:28AM +0100, Mario Kleiner wrote: > Looks good to me. As a further optimization, i think we could move > the vblank_disable_fn() call outside/below the > spin_unlock_irqrestore for event_lock, as vblank_disable_fn() > doesn't need any locks held at call time, so

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Limit number of reads to stabilize rc6 counter reads

== Series Details == Series: drm/i915: Limit number of reads to stabilize rc6 counter reads URL : https://patchwork.freedesktop.org/series/21843/ State : success == Summary == Series 21843v1 drm/i915: Limit number of reads to stabilize rc6 counter reads

Re: [Intel-gfx] [PATCH 1/2] drm/i915: Disable MI_SET_CONTEXT psmi w/a for bdw

On Fri, Mar 24, 2017 at 05:01:56PM +0100, Michał Winiarski wrote: > On Fri, Mar 24, 2017 at 03:17:23PM +, Chris Wilson wrote: > > The current w/a for the gen7 psmi related hangs doesn't apply to bdw, so > > disable it if using bdw ringbuffer submission. > > > > Signed-off-by: Chris Wilson

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915: Fixup intel_write_status_page() for old CPUs without clflush

== Series Details == Series: series starting with [1/3] drm/i915: Fixup intel_write_status_page() for old CPUs without clflush URL : https://patchwork.freedesktop.org/series/21842/ State : success == Summary == Series 21842v1 Series without cover letter

Re: [Intel-gfx] [PATCH 1/3] drm/i915: Fixup intel_write_status_page() for old CPUs without clflush

On Fri, Mar 24, 2017 at 04:35:38PM +, Chris Wilson wrote: > Note all of our target platforms have clflush. For those without, just s/Note/Not/ > assume the status page is sufficiently coherent that we do not need our > paranoia. -Chris -- Chris Wilson, Intel Open Source Technology Centre

[Intel-gfx] [PATCH] drm/i915: Limit number of reads to stabilize rc6 counter reads

We have only 8bits of precise timestamps in which to complete our upper/load reads, along with the switch between precision. This is not always enough time to read the upper counter twice within the same time slice, leading to hard lockups. Limit the number of times to prevent an inifite loop (my

[Intel-gfx] [PATCH 1/3] drm/i915: Fixup intel_write_status_page() for old CPUs without clflush

Note all of our target platforms have clflush. For those without, just assume the status page is sufficiently coherent that we do not need our paranoia. Reported-by: Ville Syrjälä Fixes: 14a6bbf9e535 ("drm/i915: Replace irq_seqno_barrier on hws write with a

Re: [Intel-gfx] [PATCH] drm/i915/guc: Refactor the retrieval of guc_process_desc

On Fri, Mar 24, 2017 at 01:11:20PM +0100, Michał Winiarski wrote: > On Thu, Mar 23, 2017 at 11:00:00PM +, Chris Wilson wrote: > > Move the common "client->vaddr + client->proc_desc_offset" to its own > > function, __get_process_desc() to match the newly established pattern. > > > >

[Intel-gfx] [PATCH 2/3] drm/i915: Remove unused intel_flush_status_page()

intel_flush_status_page() is defunct since commit f8dd2934c4ec ("drm/i915: Remove BXT incoherent seqno write workaround"), time to remove it. Signed-off-by: Chris Wilson Cc: Mika Kuoppala Cc: Joonas Lahtinen

[Intel-gfx] [PATCH 3/3] drm/i915: Use BIT() for computing the engine's flag

Since the engine's flag is just the bit of its id, use BIT(). Signed-off-by: Chris Wilson Cc: Joonas Lahtinen --- drivers/gpu/drm/i915/intel_ringbuffer.h | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git

[Intel-gfx] [dim PATCH 5/7] dim: remove apply-igt subcommand

Out of scope for dim, and relies on hard coded paths. People can add the function to their .dimrc if needed. Signed-off-by: Jani Nikula --- dim | 7 --- dim.rst | 4 2 files changed, 11 deletions(-) diff --git a/dim b/dim index fc72cd619dbd..b7d6b2aafff6

[Intel-gfx] [dim PATCH 3/7] dim: add 'make mancheck' target to check all subcommands have been documented

Just a simple grep. Signed-off-by: Jani Nikula --- Makefile | 7 +++ 1 file changed, 7 insertions(+) diff --git a/Makefile b/Makefile index c1fe02c1b565..ce283114c4aa 100644 --- a/Makefile +++ b/Makefile @@ -32,6 +32,13 @@ SC_EXCLUDE := \ shellcheck:

[Intel-gfx] [dim PATCH 6/7] dim: document drm-intel specific shorthands separately from the generic ones

Hopefully increases clarity for people not working on drm-intel. Signed-off-by: Jani Nikula --- dim.rst | 57 + 1 file changed, 29 insertions(+), 28 deletions(-) diff --git a/dim.rst b/dim.rst index

[Intel-gfx] [dim PATCH 7/7] dim: group command documentation in the man page by target audiences

Group the man page by: - commands for developers - commands for committers and maintainers - advanced commands for committers and maintainers - commands for maintainers - dim help commands. We have so many commands by now that it should be helpful to group them a little. Signed-off-by: Jani

[Intel-gfx] [dim PATCH 4/7] dim: remove aliases from the man page

Increase clarity. People can list the aliases using 'dim list-aliases' and add their own. Signed-off-by: Jani Nikula --- dim.rst | 55 +-- 1 file changed, 29 insertions(+), 26 deletions(-) diff --git a/dim.rst b/dim.rst

[Intel-gfx] [dim PATCH 1/7] completion: shellcheck bash completion and fix issues

Add bash_completion to 'make shellcheck' target, and fix the failures. Signed-off-by: Jani Nikula --- Makefile| 2 +- bash_completion | 13 +++-- 2 files changed, 8 insertions(+), 7 deletions(-) diff --git a/Makefile b/Makefile index

[Intel-gfx] [dim PATCH 2/7] dim: return error exit status on unknown subcommands

Signed-off-by: Jani Nikula --- dim | 9 + 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/dim b/dim index 989674ab7a91..fc72cd619dbd 100755 --- a/dim +++ b/dim @@ -1840,11 +1840,12 @@ if ! declare -n subcmd=dim_alias_${subcommand//-/_} &> /dev/null

Re: [Intel-gfx] [PATCH 1/2] drm/i915: Disable MI_SET_CONTEXT psmi w/a for bdw

On Fri, Mar 24, 2017 at 03:17:23PM +, Chris Wilson wrote: > The current w/a for the gen7 psmi related hangs doesn't apply to bdw, so > disable it if using bdw ringbuffer submission. > > Signed-off-by: Chris Wilson > --- > drivers/gpu/drm/i915/i915_gem_context.c | 2

Re: [Intel-gfx] [PATCH] drm/i915/guc: limit forcewake to blitter domain in guc_send

On Fri, Mar 24, 2017 at 09:12:13PM +0530, Kamble, Sagar A wrote: >Reviewed-by: Sagar Arun Kamble [1] and pushed. Sagar, you might want to turn off sending html email for intel-gfx@. -Chris -- Chris Wilson, Intel Open Source Technology Centre

Re: [Intel-gfx] [PATCH] drm/i915/guc: limit forcewake to blitter domain in guc_send

Reviewed-by: Sagar Arun Kamble On 3/24/2017 8:18 PM, Daniele Ceraolo Spurio wrote: The forcewake_get call in the guc_send_mmio function was added to avoid getting and releasing forcewake on each register access. While this makes sense, all GuC registers are in the

[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/2] drm/i915: Disable MI_SET_CONTEXT psmi w/a for bdw

== Series Details == Series: series starting with [1/2] drm/i915: Disable MI_SET_CONTEXT psmi w/a for bdw URL : https://patchwork.freedesktop.org/series/21837/ State : failure == Summary == Series 21837v1 Series without cover letter

Re: [Intel-gfx] [PATCH 2/2] drm/i915: Remove obsolete ringbuffer emission for gen8+

On Fri, Mar 24, 2017 at 09:42:40AM +, Chris Wilson wrote: > Since removing the module parameter to force selection of ringbuffer > emission for gen8, the code is defunct. Remove it. To put the difference into perspective, a couple of microbenchmarks (bdw i7-5557u):

Re: [Intel-gfx] [PATCH 2/2] drm/i915: Fix semaphore emission for BDW+ RCS ringbuffer emission

On Fri, Mar 24, 2017 at 03:17:24PM +, Chris Wilson wrote: > The required number of dwords for semaphore emission on BDW RCS is 8, > not 6 - leading to ring buffer corruption and immediate GPU hangs when > using ringbuffer submission. > > Signed-off-by: Chris Wilson

[Intel-gfx] [PATCH 2/2] drm/i915: Fix semaphore emission for BDW+ RCS ringbuffer emission

The required number of dwords for semaphore emission on BDW RCS is 8, not 6 - leading to ring buffer corruption and immediate GPU hangs when using ringbuffer submission. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/intel_ringbuffer.c | 2 +- 1 file changed, 1

[Intel-gfx] [PATCH 1/2] drm/i915: Disable MI_SET_CONTEXT psmi w/a for bdw

The current w/a for the gen7 psmi related hangs doesn't apply to bdw, so disable it if using bdw ringbuffer submission. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/i915_gem_context.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/guc: limit forcewake to blitter domain in guc_send

== Series Details == Series: drm/i915/guc: limit forcewake to blitter domain in guc_send URL : https://patchwork.freedesktop.org/series/21834/ State : success == Summary == Series 21834v1 drm/i915/guc: limit forcewake to blitter domain in guc_send

[Intel-gfx] [PATCH] drm/i915/guc: limit forcewake to blitter domain in guc_send

The forcewake_get call in the guc_send_mmio function was added to avoid getting and releasing forcewake on each register access. While this makes sense, all GuC registers are in the blitter range so no need to wake all the wells. Signed-off-by: Daniele Ceraolo Spurio

Re: [Intel-gfx] [PATCH dim 2/2] dim: Curate and insert tags into patch(es)

On Fri, Mar 24, 2017 at 11:07:17AM +0200, Ville Syrjälä wrote: > On Thu, Mar 23, 2017 at 05:07:28PM -0400, Sean Paul wrote: > > Launch $EDITOR when extracting tags to curate the tags immediately. Once the > > tags are proper, automatically add them before the first Signed-off-by line > > to all

Re: [Intel-gfx] [PATCH dim 2/2] dim: Curate and insert tags into patch(es)

On Fri, Mar 24, 2017 at 09:54:15AM +0200, Jani Nikula wrote: > On Thu, 23 Mar 2017, Sean Paul wrote: > > Launch $EDITOR when extracting tags to curate the tags immediately. Once the > > tags are proper, automatically add them before the first Signed-off-by line > > to all

Re: [Intel-gfx] [PATCH 1/2] drm/i915: Sanitize display INIT power domain enabling

On Fri, Mar 24, 2017 at 02:36:54PM +0200, Imre Deak wrote: > For consistency move the INIT power domain enabling to happen at the > same call-stack level everywhere. So far we didn't do this enabling > during: > - on GEN9 big-core when resuming from system freeze > - on VLV on the

[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/2] drm/i915: Sanitize display INIT power domain enabling

== Series Details == Series: series starting with [1/2] drm/i915: Sanitize display INIT power domain enabling URL : https://patchwork.freedesktop.org/series/21827/ State : failure == Summary == Series 21827v1 Series without cover letter

[Intel-gfx] [PATCH 2/2] drm/i915: Sanitize display INIT power domain disabling

For consistency move the INIT power domain disabling to the same call-stack level with the corresponding enabling. This change will remove the disable call via intel_finish_reset() and intel_lid_notify(), but this is fine: we didn't enable the INIT power domain on these paths to begin with, so

[Intel-gfx] [PATCH 1/2] drm/i915: Sanitize display INIT power domain enabling

For consistency move the INIT power domain enabling to happen at the same call-stack level everywhere. So far we didn't do this enabling during: - on GEN9 big-core when resuming from system freeze - on VLV on the i915_drm_suspend_late() error path Fortunately neither of these depended on display

Re: [Intel-gfx] [i-g-t PATCH 2/2] igt/kms_flip: Fix set_dpms called with an idle bo

On Fri, Mar 24, 2017 at 01:55:00PM +0200, Ander Conselvan De Oliveira wrote: > On Thu, 2016-12-01 at 11:23 +, Chris Wilson wrote: > > On Thu, Dec 01, 2016 at 12:58:46PM +0200, Abdiel Janulgue wrote: > > > Signed-off-by: Abdiel Janulgue > > How is the bug that

Re: [Intel-gfx] [PATCH] drm/i915/guc: Refactor the retrieval of guc_process_desc

On Thu, Mar 23, 2017 at 11:00:00PM +, Chris Wilson wrote: > Move the common "client->vaddr + client->proc_desc_offset" to its own > function, __get_process_desc() to match the newly established pattern. > > Signed-off-by: Chris Wilson Reviewed-by: Michał Winiarski

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Enable FBC for non X-tiled FBs (rev4)

== Series Details == Series: drm/i915: Enable FBC for non X-tiled FBs (rev4) URL : https://patchwork.freedesktop.org/series/21264/ State : success == Summary == Series 21264v4 drm/i915: Enable FBC for non X-tiled FBs https://patchwork.freedesktop.org/api/1.0/series/21264/revisions/4/mbox/

Re: [Intel-gfx] [i-g-t PATCH 2/2] igt/kms_flip: Fix set_dpms called with an idle bo

On Thu, 2016-12-01 at 11:23 +, Chris Wilson wrote: > On Thu, Dec 01, 2016 at 12:58:46PM +0200, Abdiel Janulgue wrote: > > Signed-off-by: Abdiel Janulgue How is the bug that this commit fixes triggered? Reverting this change seems to fix [1] which, if I

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Enhanced disable access to stolen memory as a guest (rev2)

== Series Details == Series: drm/i915: Enhanced disable access to stolen memory as a guest (rev2) URL : https://patchwork.freedesktop.org/series/21818/ State : success == Summary == Series 21818v2 drm/i915: Enhanced disable access to stolen memory as a guest

[Intel-gfx] [PATCH v4] drm/i915: Fix FBC cfb stride programming for non X-tiled FB

When FBC is enabled for linear, legacy Y-tiled and Yf-tiled surfaces on gen9, the cfb stride must be programmed by SW as cfb_stride = ceiling[(at least plane width in pixels)/ (32 * compression limit factor)] * 8 v2: Minor fix for a build error v3: Fixed subject, register

[Intel-gfx] ✗ Fi.CI.BAT: failure for Enable OA unit for Gen 8 and 9 in i915 perf (rev3)

== Series Details == Series: Enable OA unit for Gen 8 and 9 in i915 perf (rev3) URL : https://patchwork.freedesktop.org/series/20084/ State : failure == Summary == Series 20084v3 Enable OA unit for Gen 8 and 9 in i915 perf

Re: [Intel-gfx] [PATCH] drm/i915: Reduce Data Link N value for 1 lane DP->hdmi converters

On Thu, 23 Mar 2017, Clint Taylor wrote: > I would prefer a solution for B (rules for M/N), but the code doesn't > appear to be broken and I don't believe we should "Fix" something that > is working. The device also works by changing the roundup_pow_of_two() > to

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Reduce Data Link N value for 1 lane DP->hdmi converters (rev2)

== Series Details == Series: drm/i915: Reduce Data Link N value for 1 lane DP->hdmi converters (rev2) URL : https://patchwork.freedesktop.org/series/21724/ State : success == Summary == Series 21724v2 drm/i915: Reduce Data Link N value for 1 lane DP->hdmi converters

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/dp: Validate cached link rate and lane count before retraining

== Series Details == Series: drm/i915/dp: Validate cached link rate and lane count before retraining URL : https://patchwork.freedesktop.org/series/21797/ State : success == Summary == Series 21797v1 drm/i915/dp: Validate cached link rate and lane count before retraining

Re: [Intel-gfx] [PATCH 6/6] drm/i915: Use i9xx_check_plane_surface() for sprite planes as well

On Thu, Mar 23, 2017 at 09:27:12PM +0200, ville.syrj...@linux.intel.com wrote: > From: Ville Syrjälä > > All the pre-SKL sprite planes compute the x/y/tile offsets in a > similar way. There are a couple of minor differences but the primary > planes have those as

[Intel-gfx] [PATCH] drm/i915: Reorganise intel_engine_cleanup

Merge the two vfuncs into one and so eliminate one more case of execlists/ringbuffer specialisation outside of the intel_engine_cs.c Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/i915_drv.c | 2 +- drivers/gpu/drm/i915/i915_drv.h | 2 --

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/guc: Refactor the retrieval of guc_process_desc

== Series Details == Series: drm/i915/guc: Refactor the retrieval of guc_process_desc URL : https://patchwork.freedesktop.org/series/21795/ State : success == Summary == Series 21795v1 drm/i915/guc: Refactor the retrieval of guc_process_desc

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Moar plane update optimizations (rev4)

== Series Details == Series: drm/i915: Moar plane update optimizations (rev4) URL : https://patchwork.freedesktop.org/series/21475/ State : success == Summary == Series 21475v4 drm/i915: Moar plane update optimizations https://patchwork.freedesktop.org/api/1.0/series/21475/revisions/4/mbox/

[Intel-gfx] [PATCHi v2] drm/i915: Enhanced disable access to stolen memory as a guest

commit "04a68a3 drm/i915/gvt: Disable access to stolen memory as a guest" isn't enough in GVT-d which will pass through IGD to guest and don't run vgt code. While intel_vgpu_active() is true only when vgt code run on host and guest in GVT-g. v2:GVT-g may run in non qemu (Zhenyu) Signed-off-by:

Re: [Intel-gfx] [PATCH 08/19] drm/tilcdc: Drop calls to modeset_lock_crtc

On 22/03/17 23:50, Daniel Vetter wrote: > Again this is an internal helper, not the official way to lock a crtc. > > Cc: Jyri Sarha > Cc: Tomi Valkeinen > Signed-off-by: Daniel Vetter > --- > drivers/gpu/drm/tilcdc/tilcdc_crtc.c |

[Intel-gfx] ✗ Fi.CI.BAT: failure for Some minor i915-perf prep changes (rev2)

== Series Details == Series: Some minor i915-perf prep changes (rev2) URL : https://patchwork.freedesktop.org/series/20073/ State : failure == Summary == Series 20073v2 Some minor i915-perf prep changes https://patchwork.freedesktop.org/api/1.0/series/20073/revisions/2/mbox/ Test

[Intel-gfx] [PATCH 2/2] drm/i915: Remove obsolete ringbuffer emission for gen8+

Since removing the module parameter to force selection of ringbuffer emission for gen8, the code is defunct. Remove it. References: https://bugs.freedesktop.org/show_bug.cgi?id=87725 Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/i915_debugfs.c | 44 +---

[Intel-gfx] [PATCH 1/2] drm/i915: Remove i915.enable_execlists module parameter

Execlists and legacy ringbuffer submission are no longer feature comparable (execlists now offer greater functionality that should overcome their performance hit) and obsoletes the unsafe module parameter, i.e. comparing the two modes of execution is no longer useful, so remove the debug tool.

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Replace literal tabs in ns2501 debug messages with spaces

== Series Details == Series: drm/i915: Replace literal tabs in ns2501 debug messages with spaces URL : https://patchwork.freedesktop.org/series/21787/ State : success == Summary == Series 21787v1 drm/i915: Replace literal tabs in ns2501 debug messages with spaces

Re: [Intel-gfx] [PATCH dim 2/2] dim: Curate and insert tags into patch(es)

On Thu, Mar 23, 2017 at 05:07:28PM -0400, Sean Paul wrote: > Launch $EDITOR when extracting tags to curate the tags immediately. Once the > tags are proper, automatically add them before the first Signed-off-by line > to all patches in the range. Not sure adding them before the first sob is the

Re: [Intel-gfx] [PATCH v4 03/13] drm/i915/guc: Add onion teardown to the GuC setup

On Thu, Mar 23, 2017 at 09:36:10AM -0700, Oscar Mateo wrote: > On 03/23/2017 03:57 PM, Chris Wilson wrote: > >I'm not happy with moving subfeature detection logic into the core GEM > >code. if (i915.enable_guc_loading) firstly should never be a module > >parameter (it's derived state!) and

Re: [Intel-gfx] [PATCH] drm/debugfs: Add kerneldoc

On Wed, Mar 22, 2017 at 09:54:01PM +0100, Daniel Vetter wrote: > I've decided to not document drm_debugfs_remove_files, it's on the way > out. > > The biggest part is a huge todo.rst entry with what all should be > improved. > > v2: Nits from Gabriel. > > Cc: Gabriel Krisman Bertazi

Re: [Intel-gfx] [PATCH dim 2/2] dim: Curate and insert tags into patch(es)

On Thu, 23 Mar 2017, Sean Paul wrote: > Launch $EDITOR when extracting tags to curate the tags immediately. Once the > tags are proper, automatically add them before the first Signed-off-by line > to all patches in the range. Two problems I have with this. First, I like to

Re: [Intel-gfx] [PATCH] drm/i915: Enhanced disable access to stolen memory as a guest

On 2017.03.24 15:23:24 +0800, Xiong Zhang wrote: > commit "04a68a3 drm/i915/gvt: Disable access to stolen memory as a guest" > isn't enough in GVT-d which will pass through IGD to guest and don't run > vgt code. While intel_vgpu_active() is true only when vgt code run on > host and guest in GVT-g.

Re: [Intel-gfx] [PATCH v2] drm/i915: Reduce Data Link N value for 1 lane DP->hdmi converters

On Thu, Mar 23, 2017 at 04:38:58PM -0700, clinton.a.tay...@intel.com wrote: > From: Clint Taylor > > Several major vendor USB-C->HDMI converters fail to recover a 5.4 GHz 1 lane > signal if the Data Link N is greater than 0x8. > Patch detects when 1 lane 5.4 GHz

[Intel-gfx] [PATCH] drm/i915: Enhanced disable access to stolen memory as a guest

commit "04a68a3 drm/i915/gvt: Disable access to stolen memory as a guest" isn't enough in GVT-d which will pass through IGD to guest and don't run vgt code. While intel_vgpu_active() is true only when vgt code run on host and guest in GVT-g. Signed-off-by: Xiong Zhang

Re: [Intel-gfx] [PATCH 02/19] drm: Add acquire ctx parameter to ->update_plane

On Wed, Mar 22, 2017 at 11:03:41PM +, Russell King - ARM Linux wrote: > On Wed, Mar 22, 2017 at 10:50:41PM +0100, Daniel Vetter wrote: > > diff --git a/drivers/gpu/drm/armada/armada_overlay.c > > b/drivers/gpu/drm/armada/armada_overlay.c > > index 34cb73d0db77..b54fd8cbd3a6 100644 > > ---