Re: [Intel-gfx] [PATCH 16/37] drm/hdlcd|mali: Drop drm_vblank_cleanup

On Wed, May 31, 2017 at 05:57:07PM +0100, Liviu Dudau wrote: > On Wed, May 31, 2017 at 06:41:05PM +0200, Daniel Vetter wrote: > > On Wed, May 31, 2017 at 1:22 PM, Liviu Dudau wrote: > > > On Wed, May 31, 2017 at 01:03:34PM +0200, Daniel Vetter wrote: > > >> On Wed, May 31,

[Intel-gfx] [PATCH 2/3] drm/i915/skl: New ddb allocation algorithm

From: "Kumar, Mahesh" This patch implements new DDB allocation algorithm as per HW team recommendation. This algo takecare of scenario where we allocate less DDB for the planes with lower relative pixel rate, but they require more DDB to work. It also takes care of

Re: [Intel-gfx] [PATCH] drm/i915/cnp: Panel Power sequence changes for CNP PCH.

Hi Rodrigo, [auto build test ERROR on drm-intel/for-linux-next] [also build test ERROR on v4.12-rc3 next-20170531] [if your patch is applied to the wrong git tree, please drop us a note to help improve the system] url: https://github.com/0day-ci/linux/commits/Rodrigo-Vivi/drm-i915-cnp-Panel

Re: [Intel-gfx] [PATCH v6 5/6] drm/i915/gvt: Dmabuf support for GVT-g

Hi Gerd, >-Original Message- >From: intel-gvt-dev [mailto:intel-gvt-dev-boun...@lists.freedesktop.org] On >Behalf Of Gerd Hoffmann >Sent: Wednesday, May 31, 2017 8:05 PM >To: Chen, Xiaoguang ; >alex.william...@redhat.com; ch...@chris-wilson.co.uk; intel-

Re: [Intel-gfx] [PATCH v6 4/6] vfio: Define vfio based vgpu's dma-buf operations

Hi Kirti, >-Original Message- >From: Kirti Wankhede [mailto:kwankh...@nvidia.com] >Sent: Thursday, June 01, 2017 1:23 AM >To: Chen, Xiaoguang ; Gerd Hoffmann >; alex.william...@redhat.com; ch...@chris-wilson.co.uk;

Re: [Intel-gfx] [PATCH RESEND 1/6] drm/atomic: initial support for asynchronous plane update

2017-05-31 Eric Anholt : > Gustavo Padovan writes: > > > From: Gustavo Padovan > > > > In some cases, like cursor updates, it is interesting to update the > > plane in an asynchronous fashion to avoid big delays. The current

Re: [Intel-gfx] [PATCH 04/13] drm/i915/cnp: Backlight support for CNP.

On Tue, 2017-05-30 at 15:42 -0700, Rodrigo Vivi wrote: > Split out BXT and CNP's setup_backlight(),enable_backlight(), > disable_backlight() and hz_to_pwm() into > two separate functions instead of reusing BXT function. > > Reuse set_backlight() and get_backlight() since they have > no reference

Re: [Intel-gfx] [PATCH RESEND 6/6] drm/vc4: update cursors asynchronously through atomic

2017-05-31 Eric Anholt : > Gustavo Padovan writes: > > > From: Gustavo Padovan > > > > Add support to async updates of cursors by using the new atomic > > "Add support for" > > > interface for that. Basically what this

Re: [Intel-gfx] [PATCH] drm/i915: Guard against i915_ggtt_disable_guc() being invoked unconditionally

On 5/31/2017 12:05 PM, Chris Wilson wrote: Commit 7c3f86b6dc51 ("drm/i915: Invalidate the guc ggtt TLB upon insertion") added the restoration of the invalidation routine after the GuC was disabled, but missed that the GuC was unconditionally disabled when not used. This then overwrites the

Re: [Intel-gfx] [PATCH RESEND 1/6] drm/atomic: initial support for asynchronous plane update

Gustavo Padovan writes: > From: Gustavo Padovan > > In some cases, like cursor updates, it is interesting to update the > plane in an asynchronous fashion to avoid big delays. The current queued > update could be still waiting for a fence to

Re: [Intel-gfx] [PATCH RESEND 6/6] drm/vc4: update cursors asynchronously through atomic

Gustavo Padovan writes: > From: Gustavo Padovan > > Add support to async updates of cursors by using the new atomic "Add support for" > interface for that. Basically what this commit does is do what > vc4_update_plane() did but through

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/6] drm/i915/cnp: Introduce Cannonpoint PCH.

== Series Details == Series: series starting with [1/6] drm/i915/cnp: Introduce Cannonpoint PCH. URL : https://patchwork.freedesktop.org/series/25136/ State : success == Summary == Series 25136v1 Series without cover letter

[Intel-gfx] [PATCH 4/6] drm/i915/cnp: Backlight support for CNP.

Split out BXT and CNP's setup_backlight(),enable_backlight(), disable_backlight() and hz_to_pwm() into two separate functions instead of reusing BXT function. Reuse set_backlight() and get_backlight() since they have no reference to the utility pin. v2: Reuse BXT functions with controller 0

[Intel-gfx] [PATCH 5/6] drm/i915/cnp: add CNP gmbus support

On CNP PCH based platforms the gmbus is on the south display that is on PCH. The existing implementation for previous platforms already covers the need for CNP expect for the pin pair configuration that follows similar definitions that we had on BXT. v2: Don't drop "_BXT" as the indicator of the

[Intel-gfx] [PATCH 2/6] drm/i915/cnp: Add PCI ID for Cannonpoint LP PCH

From: Dhinakaran Pandiyan The first two bytes of PCI ID for CNP_LP PCH are the same as that of SPT_LP. We should really be looking at the first 9 bits instead of the first 8 to identify platforms, although this seems to have not caused any problems on earlier

[Intel-gfx] [PATCH 6/6] drm/i915/cnp: Panel Power sequence changes for CNP PCH.

Panel Power sequences for CNP is similar to Broxton, but with only one sequencer. Main difference from SPT is that PP_DIVISOR was removed and power cycle delay has been moved to PP_CONTROL. v2: Add missed pp_div write, that is now part of PP_CONTROL[8:4] as on Broxton. (Found by DK) v3:

[Intel-gfx] [PATCH 1/6] drm/i915/cnp: Introduce Cannonpoint PCH.

Most of south engine display that is in PCH is still the same as SPT and KBP, except for this key differences: - Backlight: Backlight programming changed in CNP PCH. - Panel Power: Sligh programming changed in CNP PCH. - GMBUS and GPIO: The pin mapping has changed in CNP PCH. All of these

[Intel-gfx] [PATCH 3/6] drm/i915/cnp: Get/set proper Raw clock frequency on CNP.

RAWCLK_FREQ register has changed for platforms with CNP+. [29:26] This field provides the denominator for the fractional part of the microsecond counter divider. The numerator is fixed at 1. Program this field to the denominator of the fractional portion of reference

Re: [Intel-gfx] [PATCH v2 5/5] ACPI: Switch to use generic guid_t in acpi_evaluate_dsm()

Hi Andy, [auto build test ERROR on pm/linux-next] [also build test ERROR on v4.12-rc3 next-20170531] [if your patch is applied to the wrong git tree, please drop us a note to help improve the system] url: https://github.com/0day-ci/linux/commits/Andy-Shevchenko/ACPI-et-al-convert-to-use-new

Re: [Intel-gfx] [PATCH v2 5/5] ACPI: Switch to use generic guid_t in acpi_evaluate_dsm()

Hi Andy, [auto build test ERROR on pm/linux-next] [also build test ERROR on v4.12-rc3 next-20170531] [if your patch is applied to the wrong git tree, please drop us a note to help improve the system] url: https://github.com/0day-ci/linux/commits/Andy-Shevchenko/ACPI-et-al-convert-to-use-new

Re: [Intel-gfx] [PATCH] drm/i915/cnp: add CNP gmbus support

Hi Rodrigo, [auto build test ERROR on drm-intel/for-linux-next] [also build test ERROR on v4.12-rc3 next-20170531] [if your patch is applied to the wrong git tree, please drop us a note to help improve the system] url: https://github.com/0day-ci/linux/commits/Rodrigo-Vivi/drm-i915-cnp-add

Re: [Intel-gfx] [PATCH v2 3/5] ACPI / bus: Switch to use new generic UUID API

Hi Andy, [auto build test ERROR on pm/linux-next] [also build test ERROR on v4.12-rc3 next-20170531] [if your patch is applied to the wrong git tree, please drop us a note to help improve the system] url: https://github.com/0day-ci/linux/commits/Andy-Shevchenko/ACPI-et-al-convert-to-use-new

Re: [Intel-gfx] [PATCH v2 3/5] ACPI / bus: Switch to use new generic UUID API

Hi Andy, [auto build test WARNING on pm/linux-next] [also build test WARNING on v4.12-rc3 next-20170531] [if your patch is applied to the wrong git tree, please drop us a note to help improve the system] url: https://github.com/0day-ci/linux/commits/Andy-Shevchenko/ACPI-et-al-convert-to-use

Re: [Intel-gfx] [PATCH v2 2/5] ACPI / APEI: Switch to use new generic UUID API

Hi Andy, [auto build test ERROR on pm/linux-next] [also build test ERROR on v4.12-rc3 next-20170531] [if your patch is applied to the wrong git tree, please drop us a note to help improve the system] url: https://github.com/0day-ci/linux/commits/Andy-Shevchenko/ACPI-et-al-convert-to-use-new

Re: [Intel-gfx] [PATCH] drm/i915/cnp: Panel Power sequence changes for CNP PCH.

On Wed, 2017-05-31 at 23:46 +, Vivi, Rodrigo wrote: > On Wed, 2017-05-31 at 23:07 +, Pandiyan, Dhinakaran wrote: > > On Wed, 2017-05-31 at 14:54 -0700, Rodrigo Vivi wrote: > > > As for BXT, PP_DIVISOR was removed from CNP PCH and power > > > cycle delay has been moved to PP_CONTROL. > > >

Re: [Intel-gfx] [PATCH] drm/i915/cnp: Panel Power sequence changes for CNP PCH.

On Wed, 2017-05-31 at 23:07 +, Pandiyan, Dhinakaran wrote: > On Wed, 2017-05-31 at 14:54 -0700, Rodrigo Vivi wrote: > > As for BXT, PP_DIVISOR was removed from CNP PCH and power > > cycle delay has been moved to PP_CONTROL. > > > > v2: Add missed pp_div write, that is now part of

Re: [Intel-gfx] [PATCH] drm/i915/cnp: Panel Power sequence changes for CNP PCH.

On Wed, 2017-05-31 at 14:54 -0700, Rodrigo Vivi wrote: > As for BXT, PP_DIVISOR was removed from CNP PCH and power > cycle delay has been moved to PP_CONTROL. > > v2: Add missed pp_div write, that is now part of PP_CONTROL[8:4] > as on Broxton. (Found by DK) > > Cc: Dhinakaran Pandiyan

Re: [Intel-gfx] [PATCH v2 5/5] ACPI: Switch to use generic guid_t in acpi_evaluate_dsm()

On Wednesday, May 31, 2017 10:41:52 PM Andy Shevchenko wrote: > acpi_evaluate_dsm() and friends take a pointer to a raw buffer of 16 > bytes. Instead we convert them to use guid_t type. At the same time we > convert current users. > > acpi_str_to_uuid() becomes useless after the conversion and

Re: [Intel-gfx] [PATCH v2 3/5] ACPI / bus: Switch to use new generic UUID API

On Wednesday, May 31, 2017 10:41:50 PM Andy Shevchenko wrote: > There are new types and helpers that are supposed to be used in new code. > > As a preparation to get rid of legacy types and API functions do > the conversion here. > > Signed-off-by: Andy Shevchenko

Re: [Intel-gfx] [PATCH 2/3] drm/i915/skl: New ddb allocation algorithm

On Fri, May 26, 2017 at 08:45:45PM +0530, Mahesh Kumar wrote: > This patch implements new DDB allocation algorithm as per HW team > recommendation. This algo takecare of scenario where we allocate less DDB > for the planes with lower relative pixel rate, but they require more DDB > to work. > It

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [01/13] drm/i915/cnp: Introduce Cannonpoint PCH. (rev3)

== Series Details == Series: series starting with [01/13] drm/i915/cnp: Introduce Cannonpoint PCH. (rev3) URL : https://patchwork.freedesktop.org/series/25070/ State : success == Summary == Series 25070v3 Series without cover letter

Re: [Intel-gfx] [PATCH] drm/i915: Always recompute watermarks when distrust_bios_wm is set, v2.

On Wed, May 31, 2017 at 05:42:36PM +0200, Maarten Lankhorst wrote: > On some systems there can be a race condition in which no crtc state is > added to the first atomic commit. This results in all crtc's having a > null DDB allocation, causing a FIFO underrun on any update until the > first

[Intel-gfx] [PATCH] drm/i915/cnp: Panel Power sequence changes for CNP PCH.

As for BXT, PP_DIVISOR was removed from CNP PCH and power cycle delay has been moved to PP_CONTROL. v2: Add missed pp_div write, that is now part of PP_CONTROL[8:4] as on Broxton. (Found by DK) Cc: Dhinakaran Pandiyan Cc: Jani Nikula

Re: [Intel-gfx] [PATCH v10 2/3] drm/i915: Add option to support dynamic backlight via DPCD

On Wed, 2017-05-31 at 14:37 -0700, Puthikorn Voravootivat wrote: > > > On Tue, May 30, 2017 at 9:18 PM, Pandiyan, Dhinakaran > wrote: > On Fri, 2017-05-26 at 18:42 -0700, Puthikorn Voravootivat > wrote: > > This patch adds option to enable

Re: [Intel-gfx] [PATCH v10 3/3] drm/i915: Set PWM divider to match desired frequency in vbt

On Tue, May 30, 2017 at 8:40 PM, Pandiyan, Dhinakaran < dhinakaran.pandi...@intel.com> wrote: > The patch looks good overall, it would have been easier to merge if > you'd sent this as the first patch in this version. Some comments > inline. > > > Will re-order to make this the first patch in the

Re: [Intel-gfx] [PATCH 06/13] drm/i915/cnp: Panel Power sequence changes for CNP PCH.

On Wed, 2017-05-31 at 21:08 +, Pandiyan, Dhinakaran wrote: > On Tue, 2017-05-30 at 15:42 -0700, Rodrigo Vivi wrote: > > As for BXT, PP_DIVISOR was removed from CNP PCH and power > > cycle delay has been moved to PP_CONTROL. > > > > Cc: Jani Nikula > > Signed-off-by:

Re: [Intel-gfx] [PATCH v10 2/3] drm/i915: Add option to support dynamic backlight via DPCD

On Tue, May 30, 2017 at 9:18 PM, Pandiyan, Dhinakaran < dhinakaran.pandi...@intel.com> wrote: > On Fri, 2017-05-26 at 18:42 -0700, Puthikorn Voravootivat wrote: > > This patch adds option to enable dynamic backlight for eDP > > panel that supports this feature via DPCD register and > > set

Re: [Intel-gfx] [PATCH] drm/i915/cnp: add CNP gmbus support

>-Original Message- >From: Rodrigo Vivi [mailto:rodrigo.v...@gmail.com] >Sent: Wednesday, May 31, 2017 11:29 AM >To: Vivi, Rodrigo ; Srivatsa, Anusha > >Cc: intel-gfx ; Nikula, Jani

Re: [Intel-gfx] [PATCH 06/13] drm/i915/cnp: Panel Power sequence changes for CNP PCH.

On Tue, 2017-05-30 at 15:42 -0700, Rodrigo Vivi wrote: > As for BXT, PP_DIVISOR was removed from CNP PCH and power > cycle delay has been moved to PP_CONTROL. > > Cc: Jani Nikula > Signed-off-by: Rodrigo Vivi > --- >

Re: [Intel-gfx] [PATCH v2 5/5] ACPI: Switch to use generic guid_t in acpi_evaluate_dsm()

On Wed, May 31, 2017 at 10:41:52PM +0300, Andy Shevchenko wrote: > acpi_evaluate_dsm() and friends take a pointer to a raw buffer of 16 > bytes. Instead we convert them to use guid_t type. At the same time we > convert current users. Acked-by: Mark Brown signature.asc

[Intel-gfx] [PATCH] tests/kms_setmode: Dynamic crtc/connector combinations

Create crtc/connector combinations based on actual adapter information obtained from drmModeRes. Also set MAX_CRTCs to 6 for AMD GPUs. Signed-off-by: Harry Wentland --- tests/kms_setmode.c | 52 1 file changed, 32

Re: [Intel-gfx] [PATCH i-g-t] tests/kms_setmode: increase MAX_CRTCS to 6

On 2017-05-31 09:32 AM, Harry Wentland wrote: On 2017-05-31 05:37 AM, Daniel Vetter wrote: On Tue, May 30, 2017 at 04:01:40PM -0400, Harry Wentland wrote: AMD GPUs can have 6 CRTCs. This requires us to allocate the combinations on the heap. Signed-off-by: Harry Wentland

Re: [Intel-gfx] [PATCH v2 0/5] ACPI et al: convert to use new UUID API

On Wed, 2017-05-31 at 22:41 +0300, Andy Shevchenko wrote: > [1]: git://git.infradead.org/users/hch/uuid.git > > Changelog v2: > - append tags I have got so far > - split single patch to few (5) > - rebased on top of latest version of uuid-types branch [1] Fengguang, looking to the above I just

[Intel-gfx] ✗ Fi.CI.BAT: failure for ACPI et al: convert to use new UUID API

== Series Details == Series: ACPI et al: convert to use new UUID API URL : https://patchwork.freedesktop.org/series/25121/ State : failure == Summary == CHK include/config/kernel.release CHK include/generated/uapi/linux/version.h CHK include/generated/utsrelease.h CHK

Re: [Intel-gfx] [PATCH v2 0/5] ACPI et al: convert to use new UUID API

On Wed, May 31, 2017 at 10:41:47PM +0300, Andy Shevchenko wrote: > This series converts ACPI and users of acpi_evaluate_dsm() to new UUID > API which includes new types and methods. > > Patches are based on uuid tree [1] from Christoph Hellwig and supposed to > go through it. > > (Christoph, I

[Intel-gfx] [PATCH v2 4/5] ACPI / extlog: Switch to use new generic UUID API

There are new types and helpers that are supposed to be used in new code. As a preparation to get rid of legacy types and API functions do the conversion here. Cc: Borislav Petkov Signed-off-by: Andy Shevchenko --- drivers/acpi/acpi_extlog.c |

[Intel-gfx] [PATCH v2 2/5] ACPI / APEI: Switch to use new generic UUID API

There are new types and helpers that are supposed to be used in new code. As a preparation to get rid of legacy types and API functions do the conversion here. Cc: Borislav Petkov Signed-off-by: Andy Shevchenko --- drivers/acpi/apei/ghes.c | 8

[Intel-gfx] [PATCH v2 5/5] ACPI: Switch to use generic guid_t in acpi_evaluate_dsm()

acpi_evaluate_dsm() and friends take a pointer to a raw buffer of 16 bytes. Instead we convert them to use guid_t type. At the same time we convert current users. acpi_str_to_uuid() becomes useless after the conversion and it's safe to get rid of it. Cc: Borislav Petkov Cc: Dan

[Intel-gfx] [PATCH v2 0/5] ACPI et al: convert to use new UUID API

This series converts ACPI and users of acpi_evaluate_dsm() to new UUID API which includes new types and methods. Patches are based on uuid tree [1] from Christoph Hellwig and supposed to go through it. (Christoph, I think it would be nice to attach them to your stuff) [1]:

[Intel-gfx] [PATCH v2 1/5] acpi, nfit: Switch to use new generic UUID API

There are new types and helpers that are supposed to be used in new code. As a preparation to get rid of legacy types and API functions do the conversion here. Cc: Dan Williams Signed-off-by: Andy Shevchenko ---

[Intel-gfx] [PATCH v2 3/5] ACPI / bus: Switch to use new generic UUID API

There are new types and helpers that are supposed to be used in new code. As a preparation to get rid of legacy types and API functions do the conversion here. Signed-off-by: Andy Shevchenko --- drivers/acpi/bus.c | 6 +++--- 1 file changed, 3 insertions(+),

Re: [Intel-gfx] [PATCH 05/15] drm/i915: align the vma start to the largest gtt page size

On Wed, May 31, 2017 at 07:52:00PM +0100, Matthew Auld wrote: > When inserting into a 48bit PPGTT we should the align the vma start > address to the required page size boundary, to guarantee we use said > page size in the gtt. If we are dealing with multiple page-sizes, we > can't guarantee

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Guard against i915_ggtt_disable_guc() being invoked unconditionally

== Series Details == Series: drm/i915: Guard against i915_ggtt_disable_guc() being invoked unconditionally URL : https://patchwork.freedesktop.org/series/25119/ State : success == Summary == Series 25119v1 drm/i915: Guard against i915_ggtt_disable_guc() being invoked unconditionally

Re: [Intel-gfx] [PATCH 04/15] drm/i915: introduce gem object page_sizes

On Wed, May 31, 2017 at 07:51:59PM +0100, Matthew Auld wrote: > err = mutex_lock_interruptible(>mm.lock); > @@ -2533,7 +2543,33 @@ int __i915_gem_object_get_pages(struct > drm_i915_gem_object *obj) > > unlock: > mutex_unlock(>mm.lock); > - return err; > + > + if (err) > +

Re: [Intel-gfx] [PATCH 03/15] drm/i915: introduce page_size_mask to dev_info

On Wed, May 31, 2017 at 07:51:58PM +0100, Matthew Auld wrote: > diff --git a/drivers/gpu/drm/i915/selftests/mock_gem_device.c > b/drivers/gpu/drm/i915/selftests/mock_gem_device.c > index 7f038ea15ef5..bb12e6fe24ec 100644 > --- a/drivers/gpu/drm/i915/selftests/mock_gem_device.c > +++

Re: [Intel-gfx] [PATCH 01/15] drm/i915: really simple gemfs

On Wed, May 31, 2017 at 07:51:56PM +0100, Matthew Auld wrote: > Not a fully blown gemfs, just our very own tmpfs kernel mount. Doing so > moves us away from the shmemfs shm_mnt, and gives us the much needed > flexibility to do things like set our own mount options, namely huge= > which should

[Intel-gfx] ✓ Fi.CI.BAT: success for huge gtt pages

== Series Details == Series: huge gtt pages URL : https://patchwork.freedesktop.org/series/25118/ State : success == Summary == Series 25118v1 huge gtt pages https://patchwork.freedesktop.org/api/1.0/series/25118/revisions/1/mbox/ fi-bdw-5557u total:278 pass:267 dwarn:0 dfail:0

Re: [Intel-gfx] [PATCH 07/15] drm/i915: pass mm.gtt_page_sizes to ppgtt insert_entries

On Wed, May 31, 2017 at 07:52:02PM +0100, Matthew Auld wrote: > In preparation for supporting huge-pages for the ppgtt, we need to know > the details of mm.page_sizes at insertion time, such that we can we can > easily determine the page sizes we are allowed to use. This is > especially true for

[Intel-gfx] [PATCH] drm/i915: Guard against i915_ggtt_disable_guc() being invoked unconditionally

Commit 7c3f86b6dc51 ("drm/i915: Invalidate the guc ggtt TLB upon insertion") added the restoration of the invalidation routine after the GuC was disabled, but missed that the GuC was unconditionally disabled when not used. This then overwrites the invalidate routine for the older chipsets, causing

[Intel-gfx] [PATCH 14/15] drm/i915: enable platform support for 2M pages

For gen8+ enable platform level support for 2M pages. Also enable for mock testing. Signed-off-by: Matthew Auld Cc: Joonas Lahtinen --- drivers/gpu/drm/i915/i915_pci.c | 9 ++---

[Intel-gfx] [PATCH 10/15] drm/i915: support huge gtt pages for the 48b PPGTT

Support inserting huge gtt pages into the 48b PPGTT, including mixed-mode where we allow a mixture of gtt page sizes. Signed-off-by: Matthew Auld Cc: Joonas Lahtinen Cc: Chris Wilson Cc: Daniel Vetter

[Intel-gfx] [PATCH 15/15] drm/i915: enable platform support for 1G pages

For gen8+ enable platform level support for 1G pages. Also enable for mock testing. Signed-off-by: Matthew Auld Cc: Joonas Lahtinen --- drivers/gpu/drm/i915/i915_pci.c | 9 ++---

[Intel-gfx] [PATCH 12/15] drm/i915/debugfs: include some gtt page size metrics

Good to know, mostly for debugging purposes. Signed-off-by: Matthew Auld Cc: Joonas Lahtinen --- drivers/gpu/drm/i915/i915_debugfs.c | 40 ++--- 1 file changed, 37 insertions(+), 3 deletions(-) diff --git

[Intel-gfx] [PATCH 13/15] drm/i915: enable platform support for 64K pages

For gen9+ enable platform level support for 64K pages. Also enable for mock testing. Signed-off-by: Matthew Auld Cc: Joonas Lahtinen --- drivers/gpu/drm/i915/i915_pci.c | 6 --

[Intel-gfx] [PATCH 01/15] drm/i915: really simple gemfs

Not a fully blown gemfs, just our very own tmpfs kernel mount. Doing so moves us away from the shmemfs shm_mnt, and gives us the much needed flexibility to do things like set our own mount options, namely huge= which should allow us to enable the use of transparent-huge-pages for our shmem backed

[Intel-gfx] [PATCH 03/15] drm/i915: introduce page_size_mask to dev_info

In preparation for huge gtt pages expose a page_size_mask as part of the device info, to indicate the page sizes supported by the HW. Currently only 4K is supported. Signed-off-by: Matthew Auld Cc: Joonas Lahtinen Cc: Mika Kuoppala

[Intel-gfx] [PATCH 04/15] drm/i915: introduce gem object page_sizes

We need to track the possible page sizes given the layout of the sg table, in preparation for supporting huge gtt pages. Note that this does in any way represent the real gtt page size usage. Signed-off-by: Matthew Auld Cc: Joonas Lahtinen

[Intel-gfx] [PATCH 06/15] drm/i915: align 64K objects to 2M

We can't mix 64K and 4K pte's in the same page-table, so for now we align 64K objects to 2M to avoid any potential mixing. This is potentially wasteful but in reality shouldn't be too bad since this only applies to the virtual address space of a 48b PPGTT. Suggested-by: Chris Wilson

[Intel-gfx] [PATCH 07/15] drm/i915: pass mm.gtt_page_sizes to ppgtt insert_entries

In preparation for supporting huge-pages for the ppgtt, we need to know the details of mm.page_sizes at insertion time, such that we can we can easily determine the page sizes we are allowed to use. This is especially true for 64K where we can't just arbitrarily use it, since we require

[Intel-gfx] [PATCH 05/15] drm/i915: align the vma start to the largest gtt page size

When inserting into a 48bit PPGTT we should the align the vma start address to the required page size boundary, to guarantee we use said page size in the gtt. If we are dealing with multiple page-sizes, we can't guarantee anything and just align to the largest. For soft pinning we don't force any

[Intel-gfx] [PATCH 09/15] drm/i915: disable GTT cache for 2M/1G pages

When SW enables the use of 2M/1G pages, it must disable the GTT cache. Signed-off-by: Matthew Auld Cc: Joonas Lahtinen --- drivers/gpu/drm/i915/intel_pm.c | 12 ++-- 1 file changed, 6 insertions(+), 6 deletions(-) diff --git

[Intel-gfx] [PATCH 11/15] drm/i915: accurate page size tracking for the ppgtt

Now that we support multiple page sizes for the ppgtt, it would be useful to track the real usage for debugging purposes. Signed-off-by: Matthew Auld Cc: Joonas Lahtinen --- drivers/gpu/drm/i915/i915_gem_gtt.c | 10 ++

[Intel-gfx] [PATCH 02/15] drm/i915: enable THP for gemfs

Enable transparent-huge-pages through gemfs by mounting with huge=within_size. Signed-off-by: Matthew Auld Cc: Joonas Lahtinen Cc: Chris Wilson --- drivers/gpu/drm/i915/i915_gemfs.c | 23 +++

[Intel-gfx] [PATCH 00/15] huge gtt pages

Not too different from the last posting, except we now request thp through our own tmpfs mount and try to support mixed gtt page sizes for a given object. Matthew Auld (15): drm/i915: really simple gemfs drm/i915: enable THP for gemfs drm/i915: introduce page_size_mask to dev_info

[Intel-gfx] [PATCH 08/15] drm/i915: enable IPS bit for 64K pages

Before we can enable 64K pages through the IPS bit, we must first enable it through MMIO, otherwise the page-walker will simply ignore it. Signed-off-by: Matthew Auld Cc: Joonas Lahtinen --- drivers/gpu/drm/i915/i915_gem.c | 11

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [01/13] drm/i915/cnp: Introduce Cannonpoint PCH. (rev2)

== Series Details == Series: series starting with [01/13] drm/i915/cnp: Introduce Cannonpoint PCH. (rev2) URL : https://patchwork.freedesktop.org/series/25070/ State : success == Summary == Series 25070v2 Series without cover letter

Re: [Intel-gfx] [PATCH] drm/i915/cnp: add CNP gmbus support

Anusha, when going to merge I noticed that we had the wrong version here. The incorrect version would break hdmi on CFL. The right workaround is not to respect the CNL bios for the pin number. So, I hope I can keep your rv-b on this one, but I'd like you to confirm please. Thanks, Rodrigo. On

[Intel-gfx] [PATCH] drm/i915/cnp: add CNP gmbus support

On CNP PCH based platforms the gmbus is on the south display that is on PCH. The existing implementation for previous platforms already covers the need for CNP expect for the pin pair configuration that follows similar definitions that we had on BXT. v2: Don't drop "_BXT" as the indicator of the

Re: [Intel-gfx] [PATCH] drm: Extract drm_vblank.[hc]

Hi Daniel, [auto build test WARNING on drm/drm-next] [also build test WARNING on next-20170531] [cannot apply to v4.12-rc3] [if your patch is applied to the wrong git tree, please drop us a note to help improve the system] url: https://github.com/0day-ci/linux/commits/Daniel-Vetter/drm

Re: [Intel-gfx] [PATCH] drm/i915/dvo: fix debug logging on unknown DID

On 05/31/2017 03:16 AM, Jani Nikula wrote: Print DID not VID on the DID error path. Looks like a copy-paste error from the VID error path. Clarify and clean up error logging, making them distinguishable from each other, while at it. Reviewed-by: Clinton Taylor

Re: [Intel-gfx] [PATCH] drm/i915: Always recompute watermarks when distrust_bios_wm is set, v2.

Reviewed-by: Mahesh Kumar On Wednesday 31 May 2017 09:12 PM, Maarten Lankhorst wrote: On some systems there can be a race condition in which no crtc state is added to the first atomic commit. This results in all crtc's having a null DDB allocation, causing a FIFO

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/ddi: Avoid long delays during system suspend / eDP disabling

== Series Details == Series: drm/i915/ddi: Avoid long delays during system suspend / eDP disabling URL : https://patchwork.freedesktop.org/series/25116/ State : success == Summary == Series 25116v1 drm/i915/ddi: Avoid long delays during system suspend / eDP disabling

Re: [Intel-gfx] [PATCH 06/13] drm/i915/cnp: Panel Power sequence changes for CNP PCH.

Reviewed-by: Clinton Taylor -Clint On 05/30/2017 03:42 PM, Rodrigo Vivi wrote: As for BXT, PP_DIVISOR was removed from CNP PCH and power cycle delay has been moved to PP_CONTROL. Cc: Jani Nikula Signed-off-by: Rodrigo Vivi

Re: [Intel-gfx] [PATCH v6 4/6] vfio: Define vfio based vgpu's dma-buf operations

On 5/31/2017 11:48 AM, Chen, Xiaoguang wrote: > Hi, > >> -Original Message- >> From: Gerd Hoffmann [mailto:kra...@redhat.com] >> Sent: Monday, May 29, 2017 3:20 PM >> To: Chen, Xiaoguang ; >> alex.william...@redhat.com; ch...@chris-wilson.co.uk; intel- >>

Re: [Intel-gfx] [PATCH] drm/i915/ddi: Avoid long delays during system suspend / eDP disabling

On Wed, May 31, 2017 at 08:05:35PM +0300, Imre Deak wrote: > Atm disabling either DP or eDP outputs can generate a spurious short > pulse interrupt. The reason is that after disabling the port the source > will stop sending a valid stream data, while the sink expects either a > valid stream or the

[Intel-gfx] [PATCH] drm/i915/ddi: Avoid long delays during system suspend / eDP disabling

Atm disabling either DP or eDP outputs can generate a spurious short pulse interrupt. The reason is that after disabling the port the source will stop sending a valid stream data, while the sink expects either a valid stream or the idle pattern. Since neither of this is sent the sink assumes

[Intel-gfx] [RFC i-g-t 1/1] tests/gem_bad_address: Fix and update gem_bad_address

When writing to an invalid memory location, the HW should be clever enough to silently discard the write without disrupting execution. gem_bad_address aim at just that. The test has been updated to move away from the libDrm wrappers and use the IOCTL wrappers instead. Also the invalid address has

[Intel-gfx] [RFC i-g-t 0/1] Introducing HW focused tests

The IGT test suite aims at testing the functionalities of the i915 graphics driver. Because of an increasing effort to move development and validation to the early stages in the development of new platforms, it is necessary to provide some form of coverage for scenarios where the driver assumes

Re: [Intel-gfx] [PATCH 16/37] drm/hdlcd|mali: Drop drm_vblank_cleanup

On Wed, May 31, 2017 at 06:41:05PM +0200, Daniel Vetter wrote: > On Wed, May 31, 2017 at 1:22 PM, Liviu Dudau wrote: > > On Wed, May 31, 2017 at 01:03:34PM +0200, Daniel Vetter wrote: > >> On Wed, May 31, 2017 at 12:57 PM, Liviu Dudau wrote: > >> > On

Re: [Intel-gfx] [PATCH 2/3] pwm: lpss: Add intel-gfx as consumer device in lookup table

Hi Shobhit, [auto build test ERROR on drm-intel/for-linux-next] [also build test ERROR on v4.12-rc3 next-20170531] [if your patch is applied to the wrong git tree, please drop us a note to help improve the system] url: https://github.com/0day-ci/linux/commits/Shobhit-Kumar/drm-i915

Re: [Intel-gfx] [PATCH 16/37] drm/hdlcd|mali: Drop drm_vblank_cleanup

On Wed, May 31, 2017 at 1:22 PM, Liviu Dudau wrote: > On Wed, May 31, 2017 at 01:03:34PM +0200, Daniel Vetter wrote: >> On Wed, May 31, 2017 at 12:57 PM, Liviu Dudau wrote: >> > On Wed, May 24, 2017 at 04:51:51PM +0200, Daniel Vetter wrote: >> >> IRQs

Re: [Intel-gfx] [PATCH 16/37] drm/hdlcd|mali: Drop drm_vblank_cleanup

On Wed, May 24, 2017 at 04:51:51PM +0200, Daniel Vetter wrote: > IRQs are properly shut down, so it almost works as race-free shutdown. > Except the irq is stopped after the vblank stuff, so boom anyway. > Proper way would be to call drm_atomic_helper_shutdown before any of > the kms things gets

Re: [Intel-gfx] [PULL] topic/e1000e-fix

On Wed, May 31, 2017 at 5:08 PM, David Miller wrote: > From: Daniel Vetter > Date: Wed, 31 May 2017 08:10:45 +0200 > >> On Wed, May 31, 2017 at 7:54 AM, Daniel Vetter >> wrote: >>> On Wed, May 31, 2017 at 1:06 AM, Dave Airlie

Re: [Intel-gfx] [PATCH 1/2] drm/i915/guc: Get rid of the enable_guc_loading module parameter

On 05/18/2017 05:41 PM, Michal Wajdeczko wrote: On Fri, May 05, 2017 at 01:23:17PM +, Oscar Mateo wrote: The decission to enable GuC loading shouldn't be left to the user. Provided the HW supports the GuC, there are only two reasons to load it: - The user has requested GuC submission. -

Re: [Intel-gfx] [PULL] topic/e1000e-fix

On Wed, 31 May 2017, David Miller wrote: > And we can't understand why respinning with the requested change is > less work than making several postings such as this one. When our CI hits tons of non-drm issues every merge window, I imagine our developers can start to get a

[Intel-gfx] [PATCH v2 1/1] e1000e: Undo e1000e_pm_freeze if __e1000_shutdown fails

From: Chris Wilson An error during suspend (e100e_pm_suspend), [ 429.994338] ACPI : EC: event blocked [ 429.994633] e1000e: EEE TX LPI TIMER: 0011 [ 430.955451] pci_pm_suspend(): e1000e_pm_suspend+0x0/0x30 [e1000e] returns -2 [ 430.955454] dpm_run_callback():

[Intel-gfx] [PATCH] drm/i915: Always recompute watermarks when distrust_bios_wm is set, v2.

On some systems there can be a race condition in which no crtc state is added to the first atomic commit. This results in all crtc's having a null DDB allocation, causing a FIFO underrun on any update until the first modeset. Changes since v1: - Do not take the connection_mutex, this is already

Re: [Intel-gfx] [PATCH v2 01/11] drm: Add HDMI 2.0 VIC support for AVI info-frames

Regards Shashank On 5/31/2017 6:11 PM, Ville Syrjälä wrote: On Tue, May 30, 2017 at 10:00:12PM +0530, Sharma, Shashank wrote: Regards Shashank On 5/30/2017 9:43 PM, Ville Syrjälä wrote: On Tue, May 30, 2017 at 05:43:40PM +0530, Shashank Sharma wrote: HDMI 1.4b support the CEA video

Re: [Intel-gfx] [PATCH v2 02/11] drm/edid: Complete CEA modedb(VIC 1-107)

Regards Shashank On 5/31/2017 6:09 PM, Ville Syrjälä wrote: On Tue, May 30, 2017 at 09:56:56PM +0530, Sharma, Shashank wrote: Regards Shashank On 5/30/2017 9:48 PM, Ville Syrjälä wrote: On Tue, May 30, 2017 at 05:43:41PM +0530, Shashank Sharma wrote: CEA-861-F specs defines new video

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/opregion: let user specify override VBT via firmware load

== Series Details == Series: drm/i915/opregion: let user specify override VBT via firmware load URL : https://patchwork.freedesktop.org/series/25105/ State : success == Summary == Series 25105v1 drm/i915/opregion: let user specify override VBT via firmware load

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